Our analog signal processor, shown in Fig. 3.3, is fabricated on a 0.5àmstandard CMOS process available through MOSIS. This integrated circuit is 2.25mm2, and consumes only 3àW when biased for speech frequencies. The intent is to make a low-power, but discrimi- nating, event detector which can call attention to compelling characterisitics of a signal. The detection approach is to identify when the signal matches a binary spectral template. This integrated circuit has two stages: a spectral analysis stage; and an event detection stage, formed by combining an array of comparators with external logic.
Brandon D. Rumberg Chapter 3. Hibernets 1.0 15
Vτl Vτh
C2 Vout
C1 CW Vin CL
M1 M2
M3 M4
101 102 103 104
-15 -10 -5
0 Octave
101 102 103 104
-30 -20 -10
0 1/2 Octave
Normalized Gain (dB)
101 102 103 104
-40 -20
0 1/3 Octave
Frequency (Hz)
(c) (a) out1
vτh,high vτh,low
out2 out3 out4 out8
vin
vτl,high vτl,low
(b)
Figure 3.4: (a) Schematic of our filter array and biasing structure. Each of the eight filters receive the input signal in parallel. Two resistive lines are used to bias the corner frequencies of all of the filters. Since the filters are operated in the subthreshold regime, linear spacing of the bias voltages translates into exponentially spaced center frequencies. (b) Schematic of our bandpass filter. The corner frequencies are electronically tunable and are independent of each other; they are established by biasingVτ l andVτ h, respectively. (c) Frequency response of the filter bank for octave spacing, 1/2 octave spacing, and 1/3 octave spacing.
The spectral decomposition front-end is composed of a filter bank with subband RMS detection circuits. This spectral analysis system is used for frequency-based event detection, and for offloading some of the signal processing which would otherwise be performed by the mote. Since the outputs of all of the filters and RMS circuits are multiplexed to a single pin, a mote can select the filter output or RMS output of any frequency band in order to acquire a frequency-domain representation of the signal.
3.4.1 Filter Bank
The constant-relative-bandwidth filter bank, shown in Fig. 3.4, is created with an eight- channel array of bandpass filters. The filters—schematic shown in Fig. 3.4(b)—are an early version of the filter described in Chapter 4, and so we will forego any details in this Chapter.
3.4.2 Resistive Biasing
Since the filters are operated in weak inversion, the transconductance values of the tran- sistors (and thus the operating frequency of the circuit) vary exponentially with bias volt- ages Vτ l and Vτ h. This exponential relationship between voltage and frequency allows us to achieve the desired log-frequency spacing across the whole filter bank using a simple re- sistive divider, internal to the chip. The configuration that is used to bias the filter bank is shown in Fig. 3.4(a), where two large resistive lines are used to generate linearly spaced bias voltages for each channel’s Vτ l and Vτ h, respectively. The voltages on either end of the resistive dividers can be tuned to cover different frequency ranges and spacings, similar to the procedure that was done with early silicon cochlear models (e.g. [74–76]). We use the 1/N octave spacing convention [77], which is common in vibrational and acoustical analyses.
In fractional-octave spacing, there are N filters per octave, and the filters cross at their−3dB points. Figure 3.4(c) demonstrates the ability to set the filter bank for one, two, or three filters per octave. These data, and all subsequent data (unless otherwise specified), were obtain from our 0.5àm standard-CMOS integrated circuit, shown previously in Fig. 3.3.
One significant benefit to using resistive lines for biasing is the ease of use when incor- porated into the larger system with the digital mote. In-the-field reconfiguration, which is a highly desirable attribute of WSNs, is easily obtained by connecting the ends of the resistive lines to digitally programmed voltage supplies (e.g. DACs or digital potentiometers). Only a small number of biases must be changed to alter the frequency range and bandwidths of the filters.
While using a resistive divider to bias the filter bank makes the ASP easy to use, there are a few drawbacks. First, the accuracy of the filter parameters depends on the matching of the resistors, which is generally poor. The effects of this mismatch can be observed by looking at the variation in gain across the AC sweeps in Fig. 3.4(c). Second, if using the mote’s DAC to permit run-time modification of the biases, resistive biasing will require the mote’s DAC to remain turned-on all the time, adding to the quiescent power draw. Both of these issues can be solved by using floating-gate transistors for parameter biasing, as we show in Chapter 4. Floating-gate transistors allow precise programming of each parameter;
also, since floating-gate transistors are non-volatile, they do not require any external biasing once they have been programmed. Consequently, in our improved front-end in Chapter 9, we use floating-gate transistors to provide better accuracy and control to our ASP/WSN systems.
3.4.3 Magnitude Detector
For sub-band magnitude detection, we use an early version of the detector presented in Chapter 5. The schematic of this magnitude detector is shown in Fig. 3.5(a). Figure 3.5(c) demonstrates the combination of the filter bank and magnitude detector. In Fig. 3.5(c), our spectral decomposition system is set for 1/2-octave spacing, starting at 250Hz. The input to the filter bank is a logarithmic chirp signal. Shown below the input are the responses of the second, fourth, sixth, and eigth bands of the decomposition system. As the chirp sweeps to higher frequencies, the response of the higher-frequency subbands increases, and the response of the lower-frequency subbands decreases. Note that the output of the magnitude circuit is
Brandon D. Rumberg Chapter 3. Hibernets 1.0 17
M1A M1B
M2 CP
GM1 GM2
VD CL
VIN
VPD
VOUT
0 0.02 0.04 0.06 0.08 0.1 0.12
1.4 1.5 1.6
Input
0 0.02 0.04 0.06 0.08 0.1 0.12
1.4 1.5 1.6
Tap 2 354Hz Band
0 0.02 0.04 0.06 0.08 0.1 0.12
1.4 1.5 1.6
Tap 4 707Hz Band
0 0.02 0.04 0.06 0.08 0.1 0.12
1.4 1.5 1.6
Tap 6 1414Hz Band
0 0.02 0.04 0.06 0.08 0.1 0.12
1.4 1.5 1.6
Tap 8 2828Hz Band
Time (s) (a)
(b) (c)
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 1.62
1.63 1.64 1.65 1.66 1.67 1.68
Time
Voltage
VIN VPD
Figure 3.5: (a) Schematic of the circuit used for magnitude detection. (b) Peak detection waveforms. (c) Demonstration of the spectral decomposition front end. The input (top plot) is a logarithmic chirp. The rest of the plots show the response of four of the subbands to obtain an estimate of the RMS of the signal. Note that each channel’s response is frequency dependent, and that the RMS outputs represent spectral characteristics of the signal.
the signal content in that band.
3.4.4 Event Detection
By combining the spectral analysis system with comparators and digital logic, we form a simple yet selective event-detection system, with flexibility to define what constitutes an event. Figure 3.6 provides a simple example in which an event is defined as occuring when signal content is present in one of two channels, but not both. The two bands being compared are 500Hz and 1.4kHz. The input consists of a 500Hz sine wave and a 1.4kHz sine wave which overlap for 10 milliseconds. The wakeup signal is generated by combining the comparator outputs for those two bands using an exclusive-or (XOR) operation, so that the interrupt is asserted only when one band exceeds the threshold. In [78], we also illustrated an example in which we detected harmonically related content, which is a scenario that is straightforward to establish using a filter array with 1/N octave spacing, such as ours. For example, we defined an event to contain spectral activity in multiple harmonically related bands with the simultaneous absence of spectral activity in non-harmonically related bands.
In these examples, we observe that there is some lag-time between when the event occurs and when the interrupt signal is asserted. The lag-time is caused by the RMS circuit, and is a result of filtering the peak-detected signal. By adjusting the parameters of the RMS circuit,
0.02 0.025 0.03 0.035 0.04 0.045 0.05 1.2
1.4 1.6 1.8 2
Voltage (V)
0.02 0.025 0.03 0.035 0.04 0.045 0.05 1.5
1.55 1.6 1.65
Time (s)
RMS Detector Output (V)
500Hz Band Input Interrupt
1.4kHz Band Threshold
Figure 3.6: Demonstration of multi-band detection using an exclusive-or template. The input consists of two overlapping sine waves. The bottom plot shows the magnitude outputs for the 500Hz and 1.4kHz bands. The comparator outputs of those two bands are combined via an exclusive-or to generate an interrupt when only one band exceeds the threshold.
the phase-lag can be reduced, at the expense of reduced RMS tracking accuracy. This lag time is related to the frequency, f, of the subband, and is approximately 4/f for the RMS circuit biasing used in this Chapter. For an application where the mote should record the event, this phase-lag could cause the onset of the event to be overlooked. Regardless of how small the phase lag is, we will miss the prelude to the event. This problem will be present in all systems which wake up based on event detection. To solve the phase-lag problem, the designer can include a memory buffer. This buffer may take the form of an analog delay line (continuous-time continuous-value), an array of sample-and-holds (discrete-time continuous- value), or low-power ADC and RAM (discrete-time discrete-value). This memory can also have a second use of adding memory to the event detection algorithm. Appendix B provides further consideration of such memory buffers.
3.4.5 Power Consumption
The power consumed by our analog integrated circuit is dominated by the bandpass fil- ters, and to a lesser extent, the magnitude circuits. As we presented in [79], which describes the circuit that this BPF is based upon, the power consumed by the BPF is linearly pro- portional to its center frequency. This relationship is shown in Fig. 3.7 for a filter tuned to a 1/2-octave bandwidth. This relationship enables the system designer to determine the maximum frequency of operation available at a given power budget.
As described for the BPF, the power consumption of the RMS circuit also scales with frequency. Additionally, the RMS circuit can be tuned in various fashions within a given frequency band f0; for example, this circuit can follow either the envelope or the RMS of a
Brandon D. Rumberg Chapter 3. Hibernets 1.0 19
101 102 103 104
10−10 10−8 10−6 10−4 10−2
Center Frequency, Highest Frequency (Hz)
Power Dissipation (W)
Single BPF at f
0
Magnitude at f
0
Filter Bank (BPF+Mag) w/ Highest f
0
Mote in Sleep Mode Digital Bandpass Filter
Figure 3.7: The power consumed by our analog spectral-decomposition block depends pri- marily on the center frequency of the bandpass filter of the highest-frequency subband. The x-axis shows the center frequency for the filter and RMS circuit, and also shows the center fre- quency of the highest-frequency subband for an array that performs spectral analysis. These are extrapolated from circuit simulations. Also included are power measurements from the digital mote including the minimum measured power consumption in sleep mode and also the power consumption of the mote performing a simple, single bandpass filtering operation (at multiple frequency locations). Note that this mote was unable to simultaneously sample and filter data at frequencies above approximately 1kHz.
signal. Therefore, this circuit has a range of power-consumption values for a givenf0. Figure 3.7 shows the worst-case scenario (i.e. highest power consumption) for operation within a given frequency band, f0.
The overall power consumption of our analog spectral-decomposition block is set by the center frequency of the highest filter tap. The power consumption of the entire spectral- decomposition system is described by a geometric series, resulting in a total power consump- tion of
Ptot = PBP F,high+PRM S,high
1−2−1/N (3.1)
wherePBP F,high and PRM S,high represent the power consumed by the BPF and RMS circuits in the highest-frequency subband, and N indicates the number of filters per octave. The total amount of power consumed by the analog block is shown in Fig. 3.7 for the case of 1/2-octave spacing. Included in Fig. 3.7 is the measured power consumption of the TelosB mote in sleep mode (25.4àW, which is within the specified bounds of 15−60àW). For the entire audio frequency band, our spectral-decomposition block consumes less power than a sleeping mote.
ASP