8.2.1 Charge Pump Topologies
A “charge pump,” sometimes called a “voltage multiplier,” is a type of switched-capacitor circuit that is used for voltage conversion. To step up a voltage Va, a charge pump first samples Va onto a capacitor and then raises the bottom plate of the capacitor by Vb, at which point the voltage of the top plate of the capacitor is Va+Vb. By alternately sampling voltages onto multiple capacitors, the voltage can be increased in a succession of stages.
Some charge pump topologies have exponential voltage growth as the number of stages increases [164], but the charge-transfer switches in these topologies are subjected to exponen- tially higher voltages in each stage. This voltage stress is a limitation, and as a result, charge pump topologies with linear voltage growth are more common [165]. The Cockcroft-Walton charge pump (which Cockcroft and Walton built for their Nobel-prize winning experiments in which they disintegrated the atomic nucleus [166]) has linear voltage growth and is commonly used for charge pumps that are built from discrete parts. However, the Cockcroft-Walton topology connects the capacitors in series, making it highly sensitive to stray capacitance on the bottom plates, which can be large in integrated circuits—the Cockcroft-Walton topology is thus inappropriate for integration [167].
Figure 8.3(a) shows an idealized Dickson charge pump [167], which is the standard charge pump topology for integrated circuits because of its linear voltage growth and its insensitivity to stray bottom-plate capacitance. The charge pump shown in the Figure has two stages that are clocked by alternating clock phases φ1 and φ2. The sequential operation of the charge pump is illustrated in Fig. 8.3(b). In the first stage, whenφ1 is open andφ2 is closed, nodeV1 is charged to Vdd. Sinceφ1 is low at this time, the voltage across the first pumping capacitor (Cp1) is Vdd. Then φ2 opens and φ1 goes high, thus raising the bottom terminal of Cp1 to Vdd. Since Cp1 has sampled Vdd, V1 is raised to 2Vdd. This process repeats in the second stage, where Cp2 is charged by Cp1 while φ1 is closed. Although Cp1 and Cp2 form a capacitive divider that attenuates the voltage that was sampled onto Cp1 in the previous cycle, in steady-state, Cp2 has charge from the previous cycle such that V2 is sampled at
Cp2 Cp1
φ1 φ2
φ1
V1 V2
Vdd Vout
CL IL
φ2 φ2
(a)
φ1 φ2
V1 V2 Vout
Vdd 2Vdd 3Vdd
(b)
Figure 8.3: (a) Ideal charge pump. (b) Operation of the ideal charge pump.
2Vdd.1 Then φ2 goes high and V2 is raised to 3Vdd. The final output voltage is obtained by sampling the last stage onto the load capacitor CL. Higher voltages can be generated by cascading more stages (N). Each stage adds Vdd to obtain a total open-circuit output voltage ofVout = (N + 1)Vdd.
When a load current (IL) is drawn from the charge pump,Voutis reduced. In equilibrium, the load draws a charge ofILT during each cycle of durationT. During a cycle, each pumping capacitor replenishes this charge to its successor. As a result, the voltage to which each capacitor pumps is reduced by ILT /Cp. This lost voltage accumulates for each capacitor and yields a total voltage of
Vout = (N + 1)Vdd−N IL
Cpf (8.2)
wheref = 1/T is the pumping frequency [168]. A nonideal charge pump will have additional sources of voltage loss caused by the “on” resistance of the switches and also caused by the stray capacitance of the switches, which forms a capacitive divider with the pumping capacitors. However, these losses can be minimized by designing the switches to have a small voltage drop for the expected load current and by designing the pumping capacitors to be much larger than the stray capacitance.
8.2.2 Charge Pump Regulation
When a charge pump is used to generate write/erase voltages, Vout must be stable and consistent to facilitate accurate floating-gate programming. However, it is evident from (8.2) that Vout has an amplified dependence on the supply voltage Vdd, which may be inconsis- tent and noisy in a battery-powered sensor node with a duty-cycled radio. Vout also has a
1For example, on thej-th cycle ofφ1, the voltage atV2is the superposition of the voltage that is sampled at V1 on the previous half-cycle (which is raised byVdd when the bottom plate goes high) and the voltage atV2 on the previous cycle
V2(j) = Cp1(V1(j−1/2) +Vdd) +Cp2V2(j−1) Cp1+Cp2
(8.1) The circuit is designed withCp1=Cp2 andV1 equalsVdd on the half cycles. If the circuit is in equilibrium, thenV2(j) =V2(j−1) = 2Vdd.
Brandon D. Rumberg Chapter 8. Charge Pump 91
(b) ROL
Ctot (N+1) Vdd Vtun
IL
Charge Pump
Current- controlled
oscillator
Vtarg
R1
R2 clk Clock
Driver
Vdd
IL Vout
+ − (a)
Vfb
ROL
IL Vout
RF
(c)
+-
+- (N+1) Vdd
K (r Vtarg−Vout)
Ctot
Figure 8.4: (a) Block diagram of a regulated charge pump. (b) Linear model of an unregu- lated charge pump. (c) Small-signal model of a regulated charge pump.
dependence on the load current IL, which may vary as memory cells begin and finish pro- gramming. Furthermore, Vout is set to integer multiples of Vdd, which is a limitation for setting the sensitive program voltages to optimal values. To achieve reliable programming, the charge pump should be regulated to a constant output voltage.
Examining (8.2), only two quantities can be adjusted at runtime to regulate the output voltage: Vdd andf. Regulation usingVdddoes not actually modulate the supply voltage, but instead modulates the clocking voltages φ1 and φ2 [169, 170]. These clocking voltages con- tribute theN Vdd portion ofVout. These variable-pump-voltage regulators have the advantage of reducing the level of clock-feedthrough ripple on Vout, which must otherwise be removed with a large load capacitor. However, variable-pump-voltage regulators have the disadvan- tage that they constantly operate at their maximum frequency, which results in wasted power from unnecessarily charging and discharging all parasitic capacitances. Variable-frequency regulators are thus a more efficient alternative. The simplest type of variable-frequency reg- ulator is the “skip” regulator, which “turns on” a constant-frequency oscillator whenVout is less than the desired voltage and otherwise turns the oscillator off [171]. Some regulators have used a combination of variable-voltage and skip-mode [172,173]. Skip regulators exhibit sporadic bursts of pumping which create large ripple on the output. A better alternative is a true “variable-frequency” regulator that linearly increases or decreases the frequency to regulate Vout. Aaltonen and Halonen previously used this method of regulation [174], and we have used the same basic method. Our charge pump achieves higher efficiency, smaller size, and better load regulation.
A generic block diagram for a variable-frequency regulated charge pump is shown in
Fig. 8.4(a). A voltage-divider (R1,2) reduces the output voltage to the chip’s rated voltage range. The difference between this reduced voltage and the desired voltage (Vtarg) is used to modulate the pumping frequency until the output voltage locks onto the desired value. In addition to setting the output voltage, regulation also reduces the output resistance, increases the power-supply rejection, and shortens the start-up time compared to an open-loop charge pump.
The performance of an open-loop charge pump can be obtained by modeling it as the RC circuit shown in Fig. 8.4(b). From (8.2), the open-circuit voltage is (N + 1)Vdd and the open-loop output resistance is ROL = N/(Cpf). The total capacitance at the output (Ctot) combines the true load capacitance (CL) with the distributed charge pump capacitance Ceq=N Cp/3 [168]. The open-loop performance parameters are summarized in Table 8.1.
Table 8.1: Charge Pump Performance
Open loop Closed loop
Output resistance ROL =N/(Cpf) RCL=ROL/K Power supply rejection PSRROL = 1/(N + 1) PSRRCL =KPSRROL
Start-up time constant τOL =ROLCtot τCL=τOL/K
It is more difficult to determine the closed-loop regulation performance because ofROL’s dependence on the operating point (i.e.ROLdepends uponf, which is a function of Vout and IL), which makes the regulation loop nonlinear. To simplify the analysis, the small-signal model from [174] is adapted and shown in Fig. 8.4(c). The variables are all defined in Table 8.2. The dc voltage source has been replaced by two small-signal dependent sources. The bottom source models the circuit’s sensitivity to Vdd. The top source models the effect of the frequency-modulating feedback. The loop gain, K, is the product of 1) the attenuation due to the voltage divider (1/r), 2) the voltage-to-frequency conversion gainKF of the error amplifier and oscillator, and 3) the frequency-to-voltage conversion gain of the charge pump
KCP = dVout
df = ILN
f2Cp (8.3)
Also, the resistorRF models the resistance of the voltage divider, which may consist of linear resistors or may be implemented with a chain of diode-connected pFETs to save space.
To solve for the regulation performance, first equate the currents at Vout 1
ROL[(N + 1)Vdd+K(rVtarg −Vout)−Vout] =Vout
sCtot+ 1 RF
+IL (8.4) Then solve for Vout, noting that by design RK
OL R1
OL + R1
F
Vout = rVtarg +N+1K Vdd− RKOLIL
sCtotKROL + 1 = rVtarg + PSRR1
CLVdd−RCLIL
sτCL+ 1 (8.5)
The output consists of a superposition of three components: the scaled-up target voltage, which is the desired output, as well as unwanted contributions from the supply voltage and
Brandon D. Rumberg Chapter 8. Charge Pump 93 Table 8.2: Charge Pump Variables
N number of stages
Vtarg target voltage
IL load current
ROL output resistance of open-loop charge pump
RF resistance of voltage divider
Ctot =CL+Ceq total output capacitance
CL load capacitance
Ceq =N Cp/3 distributed charge pump capacitance
K =KFKCP/r loop gain
KF voltage-to-frequency gain of the error amplifier and oscillator KCP =ILN/(f2Cp) frequency-to-voltage gain of the charge pump
r value of voltage division
the load current, which are both suppressed by the loop gain. The closed-loop performance parameters, which are summarized in Table 8.1, are all improved by a factor of the loop gain compared to the open-loop performance. It should be noted that the regulation circuitry adds little area and power compared to the charge pump. In Section 8.5, we will connect these performance parameters to actual circuit parameters.
In the remainder of this Chapter, we describe the subcircuits and the measured perfor- mance of the regulated charge pump.