The primary challenge when designing a charge pump that approaches the ideal charac- teristics in (8.2) is the design of the charge-transfer switches (CTS). Early integrated charge pump designs used diodes or diode-connected transistors to implement the CTS [167]. Such designs rely upon the uni-directional current flow of diodes to only allow charge transfer onto a pumping capacitor when its voltage is exceeded by the voltage of the preceding stage.
These designs suffer from poor voltage gain and poor efficiency because of the accumulation of diode voltage drops. As a result, several charge pump circuits have been developed over the past two decades to dynamically control the on/off state of the CTS and thus achieve superior performance.
As illustrated in Fig. 8.2(b), Fowler-Nordheim tunneling requires voltages so large that the drain-to-body junction will break down. To avoid break down, transistors in the CTS must inhabit isolated wells so that all voltage differentials within the CTS are at safe values.
Since it is not always possible to isolate nFETs in CMOS processes, it is best for high-voltage charge pumps to use pFETs exclusively.
Most all-pFET CTS circuits are based upon the circuit shown in Fig. 8.5(b) [175]. The CTS is shown within the dashed line and consists of 1) Msw, the switch that transfers charge between neighboring stages; 2) Mbt, a “boosting” switch that enforces the correct dc
operating point onto the otherwise capacitively-coupled gate ofMsw; and 3)Cbt, a capacitor that ac-couples the on/off clock (φ1b) up to the higher local voltage of the CTS.
(a) (b)
Msw Mbt Vx
Cbt Cp
Cp
φ1 φ1b φ2
V2 V1
Cp Cp
φ1 φ2
φ1
V1 V2
φ1, V1
φ2, V2 φ1b, Vx
(c)
Figure 8.5: (a) Charge-transfer switch. (b) A common all-pFET charge-transfer switch. (c) Non-overlapping clock scheme for the all-pFET charge-transfer switch in (b).
Figure 8.5(c) shows the clock sequence that yields correct operation of the all-pFET CTS.
First, φ1 goes high to prepare for charge transfer. When φ1 goes high, it shuts off Mbt, thus sampling the source ofMsw (V2) onto the gate of Msw (Vx), which keepsVx at the correct dc operating point (i.e. the gate is referenced to the source). Next, φ2 is taken low to prepare for charge transfer. φ2 goes low afterφ1 goes high so that the correct voltage is sampled onto node Vx. To transfer charge, φ1b is taken low to turn on Msw. After charge transfer, φ1b is raised to disconnect V2 from V1. φ1b goes high before φ2 so that no charge leaks backwards fromV2 toV1.
The charge pump circuit that we use is based upon the charge pump presented by Li et alin [176] (simulation results only). The charge pump’s CTS is similar to the all-pFET CTS in Fig. 8.5(b), but has modifications (described below) that reduce the voltage stress on the transistors and also to reduce the ripple on the output voltage. This charge pump is shown in Fig. 8.6(a).
Each stage has two parallel paths—a top path through Msw1 and Msw3, and a bottom path through Msw2 and Msw4. The parallel paths conduct in opposite phases, which helps to reduce the ripple. Furthermore, the opposing phases of the parallel paths offers a low- complexity means for clocking the second set of switches (Msw3 and Msw4). This second set of switches reduces the voltage stress on the transistors in the off-phase. In a standard charge pump, the voltage across an off switch is 2Vdd. By adding the extra switches in this charge pump, the off voltage is divided across the series switches so that no pair of terminals on the transistors is exposed to a voltage higher than Vdd [176].
To provide the correct voltage for the transistor wells, the active well-biasing technique is used [177]. This technique is implemented by “bulk-biasing” transistors Mbb∗. Each pair of Mbb∗ transistors connects the well to the higher voltage terminal of the source or the drain.
In the original implementation of this charge pump [176], active well-biasing was not used for switches Msw3 and Msw4, but instead the wells were connected to Vstage,out. In steady- state, this was acceptable because they included a grounded capacitor atVstage,out to hold the higher of Vm1 and Vm2. However, we have removed this capacitor and included well-biasing on these switches to avoid activating the parasitic vertical BJT during startup. Reducing
Brandon D. Rumberg Chapter 8. Charge Pump 95
φ1b φ2 φ2b φ1
φ2 φ1b
φ1 φ2b
clk
(b) Msw1
Mbt1
Mbb1 Mbb2
Cbt1 Cp1
Msw3
Mbb5 Mbb6 Vx1
Vm1
Msw2
Mbt2 Mbb3 Mbb4
Cbt2 Cp2 Msw4
Mbb7 Mbb8 Vx2
Vm2
Vstage,in Vstage,out
φ1b φ2
φ2b φ1 Charge
Pump Stage Vdd
φ1 φ1b φ2 φ2b
Charge Pump Stage
Charge Pump Stage
Vout
(a)
Figure 8.6: (a) The all-pFET charge pump stage [176] that is used throughout this work.
(b) Our 4-phase non-overlapping clock generator circuit. Feedback of all outputs via NAND gates has been added to guarantee thatφ1 and φ2 do not overlap.
the startup power is important for charge pumps that are used for tunneling because the startup energy dominates the overall energy for the short tunneling pulses.
We have fabricated this charge pump in a standard 0.35àm CMOS process. The size of the charge pump, including all regulation circuitry, is 230àm ì 300àm (a die photograph is shown in Fig. 8.7). The design specifications are summarized in Table 8.3. The area- optimization routine in [168] was used to obtain initial values for the number of stages and Cp, which were further optimized via simulation.
Although the charge pump contains many devices, its size is dominated by the pumping capacitors Cp∗. Each Cp in a double-branch charge pump is only half of the value that it would be in a single-branch charge pump with commensurate performance, so the total capacitance is no more than for a single-branch charge pump.
The clock generator circuit is shown in Fig. 8.6(b). In contrast to the clock generator in the previous implementation [176], which used a non-overlapping clock to trigger the two
Figure 8.7: Die photograph of the complete regulated charge pump circuit. The size is 230àmì 300àm.
non-overlapping paths, we have enclosed the left and right halves of the clock generator circuit into a global loop to ensure that φ1 and φ2 are non-overlapping. Most of the area of the clock generator is consumed by the clock drivers for φ1 and φ2, which are necessary for all charge pumps.
In summary, this all-pFET charge pump fulfills the requirements of reliably and efficiently generating high voltages for Fowler-Nordheim tunneling. Measured open-loop performance is shown alongside the closed-loop performance in Section 8.5.