A commonly cited application of FPAAs is sensor interfacing. As the Internet of Things continues to emerge, the quantity of sensing devices will increase while the energy per device will need to decrease. With this in mind, we have developed a large-scale, low-overhead FPAA for systems which have severe power constraints.
To be used in a sensor network, the FPAA’s reprogramming infrastructure has been designed to be simple enough to be controlled with 8-/16-bit microcontrollers with minimal impact on microcontroller resources. A tradeoff study of this aspect of the design is given in the following Chapter.
To facilitate the synthesis of large signal-processing systems, we have designed Netamorph 2.0 with a mixture of computational elements and a parallelized signal-flow topology. The system in Fig. 10.16 has 52 analog parameters and 89 nets (a synthesized channel readout scanner is not shown). To our knowledge, this is the largest-scale published system to be implemented in reconfigurable analog fabric.
Brandon D. Rumberg Chapter 10. Netamorph: FPAAs for WSNs 141 No consistent figure of merit exists for FPAAs. This is understandable because the intended usage of FPAAs is also not consistent. We will suggest a path toward developing a figure of merit that may allow comparison of a wide variety of FPAAs and may also allow automatic optimization of FPAAs. One recurring figure of merit is bandwidth, which is limited by the switch fabric parasitics. Bandwidth measurements in FPAAs have previously been performed on either synthesized filters or on local lines. Such measurements do not capture the performance of a nontrivial system synthesized in an FPAA. For example, the bandwidth of a local line may be very high but the design of the FPAA may prevent most nets from being routed on local lines; as a result, the typical bandwidth limitations of the switch fabric will be much more severe than the limitations indicated by the specified bandwidth.
A figure of merit that is representative of real designs can be acquired by extracting statistics about parasitics from a corpus of designs, similar to the distribution that we shown in Fig. 11.4 in the next Chapter. Combining such information with modeling of the parasitics of a single switch, it is possible to estimate the typical full-system power cost of maintaining a given bandwidth and signal resolution within the switch matrix. Such a metric is independent of the performance of the CAB elements, but instead combines all of the design tradeoffs that are inherent to FPAA design: parasitics of the switch fabric, number of devices and routing tracks per CAB, organization of CABs by function, and place-and-route algorithms.
Further development of this metric can be used to compare FPAAs and to automatically optimize FPAA design parameters.
Differential-to- single-ended amplifier
1.25V In−
In+
Second gain
stage Lowpass filter Sensor interfacing/conditioning
Conditioned
R-to-R interval Time-to-voltage
converter Asym.
Integ.
Inverter w/
nonoverlap gate drive Debouncing
Peak Detector Maxima detector
Heart-rate extraction
Period 1.25V
1.25V Out of range
Shift Reg AND (LUT)
OR (LUT) Alarm
Window
Heart-rate alarm
0 5 10 15 20 25 30 35 40
-1 0 1 2 3
In+−In− (mV)
0 5 10 15 20 25 30 35 40
0.92 0.94 0.96
Conditioned (V)
0 5 10 15 20 25 30 35 40
0 1 2
Period (V)
0 5 10 15 20 25 30 35 40
0 1 2
Time (s)
Alarm (V)
OR (LUT)
(a)
(b)
72 bpm 50 bpm 72 bpm 110 bpm
VH
VL
VL VH
Figure 10.15: (a) Heart-rate monitoring system which was synthesized in Netamorph 2.0.
After passing through the conditioning block, a time-to-voltage converter is clocked by the peaks of the R wave to extract the period. The period is compared with user-defined high/low thresholds. If two recent periods are outside of the safe range, then an alarm is generated.
(b) Measured response of the heart-rate monitoring system. The input is a 2mV differential cardiac signal with varying heart rate and 200mV 60Hz common-mode noise. The outputs of the conditioning, extraction, and alarm subsystems are plotted. The bottom plot shows successful detection of out-of-range heart rates.
Brandon D. Rumberg Chapter 10. Netamorph: FPAAs for WSNs 143
1.25V
x02
Σxi2 Σxi2−x02 x02
Out0= x02 Σxi2−x02+σ2 BPF Envelope
Detector
LPF x0 Gilbert Multiplier x
y
1.25V
x12
Σxi2 Σxi2−x12 x12 BPF Envelope
Detector
LPF x1 Gilbert Multiplier x
y In
σ2
σ2
Out1= x12 Σxi2−x12+σ2
(b)
(c)
Time (s)
0 0.5 1 1.5 2 2.5 3
Frequency (H
z) 800 635 504 400 317 252 200
0 0.5 1 1.5 2 2.5 3
Frequency (H
z) 800 635 504 400 317 252 200
(a)
Figure 10.16: (a) Audio spectrum normalization system which was synthesized in Netamorph 2.0. Only 2 of 7 channels are shown for clarity. (b & c) Measured response of the system to a 500Hz tone and chirp combination. (b) Without normalization: xi. (c) With normalization:
Outi. Note that normalization reduces leakage of the 500Hz tone into neighboring bands, and observe how the 500Hz band is inhibited during the chirp.
Chapter 11
Tradeoffs in Designing Reconfigurable Analog Sensor Interfaces for Wireless Sensing Applications
In the previous Chapter, we described the implementation and application of two “Neta- morph” FPAAs (field-programmable analog array) for wireless sensor networks. We showed that these FPAAs extend the range of applications and improve the ease of use of our Hibernets paradigm (Chapter 3), wherein sensor nodes are augmented with analog signal processing.
In this Chapter, we examine the tradeoffs for designing FPAAs for wireless sensors.
Section 11.1 describes the background of FPAAs. Section 11.2 analyzes FPAA architecture tradeoffs. Section 11.3 studies the cost of reconfiguring analog circuitry and Section 11.4 examines the implications of the cost of reconfiguration in the higher-level context of wireless sensor networks.
The study of reconfiguration costs in this Chapter was published in the Proceedings of the International Midwest Symposium on Circuits and Systems [205].