Wireless sensor networks are capable of a myriad of tasks, from monitoring critical infras- tructure such as bridges to monitoring a person’s vital signs in biomedical applications. One
Field-Programmable Analog Array
Connection Box Switch
Box
Computational Analog Block Circuit Biasing Sensor Conditioning
S e n so r N o d e
Settings SPI Pre-processed
Sensor Data Wake-up
Signal
ADC Interrupt
S e n so rs Pin
Connection Box Switch
Box
Computational Analog Block Circuit Biasing
Connection Box Switch
Box
Computational Analog Block Circuit Biasing
Connection Box Switch
Box
Computational Analog Block Circuit Biasing Analog Pre-processing Event Detection
Figure 10.1: A field-programmable analog array (FPAA) used as a reconfigurable sensor interface in a wireless sensor node. The FPAA may be used for conditioning a variety of sensor outputs, to perform low-power event detection to wake up the rest of the sensor node, or to extract relevant features of the signal to reduce the bandwidth requirements of the data converter and processor.
of the primary challenges in these applications is to maximize the network’s knowledge of its environment while using only the energy available within that environment. This limited energy is mostly spent on communication [7, 194], which illustrates the need for in-network pre-processing to reduce the data locally and thereby minimize this communication overhead.
In the signal path of a data acquisition system, all environmental information initially passes through the analog sensor interface, so the interface plays a critical role in efficiently collecting environmental information. A sensor interface that is optimized for the application can minimize the overall energy consumption by extracting only the necessary information—
since this information is extracted early in the signal chain, minimal additional processing is required prior to transmission. For example, we demonstrated in [41] how an interface that uses analog signal processing can reduce power consumption by providing event detection for wake-up scenarios. On the other hand, a sensor interface that poorly matches the application will waste energy by capturing unneeded data, or worse, will limit the bandwidth/precision of the data so as to be unusable. Thus, an application-optimized interface is crucial for maximizing the knowledge that can be collected with the available energy. Custom analog signal processing devices are too application-specific to be a universal solution to the “efficient information collection” problem.
To enable applications developers to create interfaces that are optimized for their appli- cations, we present a reconfigurable version of our Hibernets paradigm shown in Fig. 10.1.
Here, a sensing-oriented FPAA efficiently performs sensor interfacing and information ex- traction. By utilizing an FPAA locally at individual nodes, an application developer can easily morph the sensor interface to the dynamic needs of the network—hence “Netamorph.”
FPAAs have received increasing attention in attempts to bring the advantages of FPGAs (e.g. rapid prototyping) to traditional analog applications, such as filtering and sensor inter-
Brandon D. Rumberg Chapter 10. Netamorph: FPAAs for WSNs 121
Computational Analog Block
(CAB)
Connection Box (CB)
Switch Box (SB)
Connection Box Switch
Switch Box Switch (b)
(c)
Field-programmable analog array
Events Settings
Sensors
Logic & Memory Timing
Sensor interfacing
Discriminant functions
Signal decomposition
Continuous to discrete
Data (a)
Channels
Stages Signal flow
Figure 10.2: (a) Parallelized FPAA architecture for sensor networks. (b) Structure of a single computational block and its associated routing infrastructure. The computational analog block (CAB) contains a collection of circuits that are suited for the type of computation done in that stage. The connection box (CB) is used to connect the terminals of circuits within the CAB. The switch box (SB) is used to connect nodes in the CB to other CBs.
(c) CB switches make a single connection between crossing lines. SB switches make any combination of six connections between four converging lines for flexible routing.
facing [195–197]. Further work has exploited the complex large-signal behavior of transistors to efficiently map signal processing and classification algorithms into analog circuits [198,199].
This potential convergence of rapid sensor-interface design with low-power signal processing makes FPAAs an enticing choice for resource-constrained sensing applications.
Prior FPAAs have not been designed for low-resource applications such as sensor net- works, nor have they been streamlined to provide functionality spanning from sensor inter- facing to event detection. Consequently, we have focused on developing an FPAA that meets these specific needs of sensor networks. With event detection applications in mind, we have developed a parallelized architecture, which is shown abstractly in Fig. 10.2(a). Sensor data propagates through stages from sensor interfacing through to the final extracted data, and in the process, the data morphs from a continuous-time/continuous-valued representation to a mixed-domain and then fully discrete representation. Signal decomposition is performed early in the chain, after which, data are processed in parallel channels, which allows the remaining processing to be low bandwidth and low power.
Circuits in the FPAA are located in computational analog blocks (CABs), which are similar to computational logic blocks in FPGAs, and are arranged in a grid of channels and stages as shown in Fig. 10.2(a). Each stage has an intended computational role, and
the circuits contained in the CABs reflect this role. For example, the stages devoted to discriminant functions contain a variety of voltage-to-current circuits with different shapes, which can be summed together to synthesize discriminant functions. For a given stage, the same type of CAB is included in each channel so that the same programmable functions can be implemented in parallel.
CAB circuits are connected using the switch structure shown in Fig. 10.2(b&c), which is essentially the “island-style” switch structure used in most FPGAs [200]. The terminals of CAB circuits are available in the connection box, where these terminals can be connected to other circuits using simple switches. Connections to adjacent stages and channels are made via the switch box, which contain “4-point switches” that can make connections between all pairs of converging tracks. This is known as a “disjoint” switch box, because it allows any connection within a track, but does not allow connections to other parallel tracks [200].
These “4-point switches” allow many types of connections; for example, connections can be opened to keep a net local to a block, nets can pass through the switch point using straight or right-angle connections, or two nets can pass through the same switch point (e.g.
one net can pass vertically while a separate net passes horizontally). This “island-style”
structure—with local connections in the connection box and higher-level connections in the switch box—enables flexible routing while reducing the parasitics caused by routing nets on long wires with many switches.
Compared to a fixed-purpose ASP, FPAAs suffer some performance degradation from routing nets through switches. Therefore, minimizing switch parasitics is one of the primary concerns of FPAA research. Figure 10.3 illustrates the parasitics in a switch matrix. If the switch is unbuffered—such as a transmission gate, a pass transistor, or a voltage-controlled resistor [201]—then the parasitics of each switch consist of four basic components. These components include 1) a switch resistance, Rswitch, that is not zero when “on” nor infinite when “off,” 2) a capacitance across the switch,Ccouple, that causes nets in the switch matrix to interfere, 3) a capacitance to ac ground,Cpar, that loads the nets (thus requiring more power), and 4) a leakage current, Ipar, that limits the ability to route nets with long time constants in the switch matrix. Every net that passes through the switch matrix encounters a network of switches as the parasitics. Most of the switches are “off.” If the “on” switch resistance is small enough that the net is not segmented by the resistance, and if the “off” switch resistance and coupling capacitance are sufficiently large/small to isolate the net from other lines, then the total parasitics on a net can be modeled as the parallel combination of Cpar and Ipar. These parasitics require extra power to achieve a given performance. Minimizing the parasitics is therefore of concern when designing FPAAs for low-power sensor nodes, and in Section 11.2 we examine how FPAA architecture choices impact the amount of parasitics encountered by a typical net.
From the above discussion, it is clear that reconfigurability adds many new optimization tradeoffs to the design of a processor. In Chapter 11, we deal with these tradeoffs in more detail—particularly in the context of wireless sensors. In the remainder of this Chapter, we describe the implementation and application of our two Netamorph FPAAs.
Brandon D. Rumberg Chapter 10. Netamorph: FPAAs for WSNs 123
CAB NR = 3
NT = 4
Ipar Ccouple
Rswitch
Cpar Cpar
Ipar
Ipar(2NR+NT) Cpar(2NR+NT)
Switch symbol A possible switch implementation
Switch parasitics
(a)
(b)
Figure 10.3: (a) Whether a switch is implemented with a complementary transmission gate (as shown), a pass transistor, or voltage-controlled resistors [201], the parasitics can be modeled the same. (b) For a net that is routed in a switch matrix, most of the switches connected to the line are “off.” IfRswitch is small enough for “on” switches and large enough for “off” switches, then the parasitics for the line can be modeled as the parallel combination of the capacitance and leakage to ground.