In FG transistors, erasure—and often writing—is achieved by tunneling electrons through the tunneling junction, Ctun. The design of this junction has significant implications on the speed, efficiency, and long-term reliability of writing and erasure. In this Section, the charac- teristics of the two basic tunneling junction structures in standard CMOS are compared, and the junction size that achieves minimal tunneling duration and oxide degradation is derived.
Brandon D. Rumberg Chapter 7. Floating-Gate Modeling 77
0.75 0.8 0.85 0.9 0.95 1 1.05 1.1
10-14 10-12 10-10
1/Eox, nm/V J tun, A/àm2
n+, 0.35àm, 3.3V tox n+, 0.5àm, 5V tox
p+, 0.35àm, 3.3V tox p+, 0.35àm, 5V tox p+, 0.5àm, 5V tox
185.5exp(−32.8tox/Vox)
Vtun
d
n+ Vfg Vtun Vtun
n- n+ p+ Tunnelling
Junction
a
Vfg Ctun Vtun Itun
Vfg Vtun Itun
Ctun
CT − Ctun
b c
p+
p+ n+
Vfg Vtun Vtun
n-
n+ Tunnelling Junction
Figure 7.1: Fowler-Nordheim tunneling characteristics. (a) Schematic of floating-gate tran- sistor. (b) Equivalent tunneling circuit. (c) Structure of tunneling junctions. (d) Fowler- Nordheim voltage-current measurements.
7.1.1 Fowler-Nordheim Tunneling Current
Fowler-Nordheim tunneling occurs when the electric field across the Ctun dielectric is sufficiently high to distort the energy band such that the effective barrier thickness is re- duced to 5nm [146]. An electric field (Eox) of 0.64V/nm is required to initiate tunneling for the 3.2eV Si-SiO2 interface (from the floating gate to the oxide dielectric) [146]. The com- plete expression for Fowler-Nordheim tunneling into SiO2 is derived in [147]. By neglecting temperature dependence, by neglecting oxide barrier-lowering from image charge (which is small at moderate fields in SiO2 [148]), and by dropping the pre-exponential electric field term (which, within the region of interest, only has an affect on the curve fit values), the tunneling current expression can be approximated by [149]
Jtun=αexp (−βtox/Vox) (7.1)
where tox is the thickness of the oxide barrier, Vox is the voltage across the barrier, and α and β are constants related to the fabrication process and junction type. A thin oxide is desired to minimize the tunneling voltage. In standard CMOS, the gate oxide is typically used because it is thin and also of high quality, which benefits reliability and predictability.
Oxides thinner than 5nm should be avoided to deter direct tunneling; consequently, higher voltage I/O devices for 2.5V (5nm), 3.3V (7–8nm), or 5V (14–15nm) operation are typically
used in fine-geometry processes [137]. Thus, our results using 3.3V and 5V devices from 0.35àm and 0.5àm processes provide a relevant insight into tunneling in new processes, as well.
To remove electrons from the FG, Vtun is raised to a high voltage, typically higher than the reverse breakdown voltage of the source/drain diffusions, but less than the breakdown of the well-to-substrate junction. To avoid reverse breakdown, tunneling junctions are generally placed within a well. Fig. 7.1(c) shows the two basic types of tunneling junctions: a p+ MOS capacitor formed as a standard pFET and an n+ MOS capacitor formed with n+ diffusions along the gate. The n+ junctions have traditionally been favoured for analog memory applications [149], but p+ junctions are becoming common for standard CMOS Flash applications [137]. In this Section, the static and transient characteristics of p+ and n+ junctions are compared to determine recommendations for junction design.
FG programming characteristics can be engineered via the design of the tunneling junc- tion: the width, length,tox, and diffusion type. Fig. 7.1(d) shows measured Fowler-Nordheim tunneling characteristics for a variety of junction designs. Each trace was obtained by reading Vf g through a buffer during a pulse to Vtun (i.e. typical tunneling conditions). All terminals exceptVtun andVf g were held fixed, so the circuit can be modeled by Fig. 7.1(b). By reading Vf g, we obtain Eox = (Vtun−Vf g)/tox and Itun =CTdtd(Vf g), where CT is the total capaci- tance connected to the node. Four different Ctun dimensions were used on a 0.5àm process (àmìàm): 1.5ì0.6, 3ì0.6, 1.5ì1.2, and 3ì1.2. Five dimensions were used for the 0.35àm p+ junctions (àmìàm): 0.5ì0.5, 0.5ì1, 0.5ì2, 1ì0.5, and 2ì0.5. The 0.35àm n+ junction was 0.4àmì0.35àm.
The p+ junction curves in Fig. 7.1(d) all align and are excellently described by the values α=185.5A/àm2 andβ=32.8V/nm. The traces align when normalized by area (i.e. plotted as current density), which illustrates that, at least for large enoughVox to achieve fast tunneling, the current comes from the full junction area rather than from the edges [149].
The curves for the n+ junctions correspond to the time after which the junctions have recovered from depletion and have begun to tunnel (more details in the next Subsection).
For 0.5àm, the difference between the p+and n+ junctions is likely caused by their different flat-band voltages. The low current andVtun-dependence of the 0.35àm n+ junction may be explained by variations in the effective oxide thickness due to finite charge depth [150].
In summary, p+ junctions are more consistent from process to process and the p+ tun- neling current is significantly higher in the 0.35àm process.
7.1.2 Temporal Dynamics of Tunneling Junctions
In addition to the Fowler-Nordheim tunneling traces, the temporal dynamics of the junc- tions must also be considered. The variable capacitance of the MOS capacitor structures can cause complex transient characteristics. Fig. 7.2a shows measured transient responses of 0.5àm FGs for 20V Vtun pulses. This experiment is analogous to block erasure in which all FGs, regardless of their initial value, should tunnel to approximately the same value.
The pulse duration for the p+ junctions is 340às and the durations for the n+ junctions have been adjusted to achieve an approximately equal amount of tunneling. Based on the equivalent circuit in Fig. 7.1(b),Vf g will rise as electrons tunnel through Ctun. AsVf g rises, the tunneling rate decreases due to a decreasing Vox. As a result, FGs with different ini-
Brandon D. Rumberg Chapter 7. Floating-Gate Modeling 79 tial voltages approach the same final voltage [see the p+ junctions in Fig. 7.2(a)]. The p+ junctions perform as expected given (7.1). The n+ junctions, however, experience a voltage- dependent delay before they begin to tunnel. This delay is a result of the depletion region that is formed underneath the gate in response to the Vtun pulse. Most of the tunneling voltage is dropped across the depletion capacitance, resulting in a small oxide voltage and thus no tunneling current. The depletion region collapses slowly as carriers are generated from thermal generation and band-to-band tunneling, after which tunneling begins [151]. In both processes, the p+ junctions had no measurable delay.
0 1 2
0 1 2 3 4
time, ms
floating-gate voltage, V
0.7 0.8 0.9 1 1.1 10-1
100
(Vtun − V
fg)/t
ox, V/nm
depletion recovery, s
n+, 0.5V n+, 1V p+, 0.5V p+, 1V
1.5 0.6 3 0.6 1.5 1.2 3 1.2 Ctun0.5àm, àm àm 0.35àm
0.4 0.35 Ctun, àm àm
a b
Figure 7.2: Tunneling junction transient characteristics. (a) Transient characteristics of n+ and p+ junctions with different initial voltages. (b) Depletion recovery time of n+ junctions.
Fig. 7.2(b) shows that the depletion recovery time of the n+ junctions (duration between the beginning of the tunneling pulse and the start of tunneling) is independent of the junction area when plotted in terms ofVtun−Vf g. However, larger junctions have a smallerVtun−Vf g
due to the capacitive division [Fig. 7.1(b)]; as a result, the delay time increases with Ctun. Another result of the voltage-dependence is that the delay time is exponentially related to the initial FG voltage. This is problematic for memory arrays because, for short erase times, the post-erase distribution of FG values can have a complex and non-monotonic relation to the initial distribution of FG voltages. These transient depletion characteristics are more pronounced for typical tunneling voltages in the 0.5àm process than in the 0.35àm process.
But in both processes, the p+junctions achieve faster tunneling times because of their higher Itun in 0.35àm and because of their lack of a depletion recovery delay.
Overall, we suggest that p+ junctions are the best choice because they are faster, less power to operate (since they are faster, the high-voltage generation circuitry operates for less time), more consistent from process to process, and always available in CMOS process design kits.
To verify reliability using high-voltage tunneling pulses, we have performed 100k write/
erase cycles on a 0.35àm FG with a p+ tunneling junction and a 200fF gate capacitor. The FG’s threshold voltage was shifted 1V up and down in each cycle, transferring an accumulated 20nC of charge through Ctun. We observed only a 30% reduction in tunneling current.
7.1.3 Sizing of Tunneling Junctions for Speed and Reliability
Tunneling junctions are often made to be minimum size to minimize the coupling from Vtun to Vf g. However, we will derive the optimal Ctun/CT ratio that minimizes the time to tunnel to the post-erasure FG voltage, Vf g,e. Increasing the junction size has two opposing trends: larger area increases the tunneling current, but it also increases the coupling onto the FG which reduces the final voltage when Vtun steps down. To find the junction size that tunnels to the final voltage in the shortest duration, we first write the tunneling current in terms of Ctun and Vf g,e as
Itun=α(Ctun/γ) exp
− βtox
1−CCtun
T
Vtun−Vf g,e
(7.2)
where γ is the unit capacitance (aF/àm2) of Ctun. By taking the derivative with respect to Ctun and setting the LHS to ‘0’, we find that tunneling is maximized for the following coupling ratio.
Ctun
CT = βtox
2Vtun 1 + 2Vtun−Vf g,e
βtox − s
1 + 4Vtun−Vf g,e
βtox
!
(7.3) This equation is verified in Fig. 7.3 for 0.5àm FGs. ForVtun=20V, Vf g,e=2.5V, tox ≈14nm, and β=32.8V/nm, the optimal coupling ratio is calculated to be approximately 3.1%. It can be seen that the junction with 3.2% coupling reaches the final voltage 23% faster than the larger junction (which suffers from excessive coupling) and 44% faster than the smaller junction (which suffers from insufficient tunneling area, thus limiting Itun). In addition to reducing the duration compared to a minimum-sized tunneling junction, the larger sizing also increases the long-term reliability. This is because oxide degradation is related to the charge-density that has passed through the junction [152]. By using a larger junction, the charge-density is reduced, which contributes to an increase in long-term reliability. For digital Flash applications, CT may not be large enough to achieve such a ratio, but analog FG applications use large control-gate capacitors, often 100fF or more, and so will benefit from this sizing.
-100 0 100 200 300 400 500 600
1 2 3 4
time, às V fg, V
Ctun/CT = 5.7%
Ctun/CT = 3.2%
Ctun/CT = 2%
Figure 7.3: Optimal tunneling junction sizing.
Brandon D. Rumberg Chapter 7. Floating-Gate Modeling 81
7.1.4 Conclusion of Tunneling-Junction Study
Non-volatile memory is increasingly being included in standard CMOS products. Tun- neling is used in most of these non-volatile memories, and so design methods for tunneling junctions are of interest if they can improve speed, reliability, and/or energy efficiency. We have presented answers to tunneling junction design decisions that offer improvement in all three categories.