CMOS FGs, particularly analog FGs, are often programmed using hot-electron injection.
In non-FG transistors, injection can still occur and is undesirable because of the damage that constant injection can cause to the gate oxide. As a result, extended drain implants are added to nFETs to minimize injection by reducing the electric field at the drain. Such prevention measures are not added to pFETs, because the lower mobility and shorter mean-free path of holes already inhibits injection in pFETs [153]. Nevertheless, pFETs are preferred for injection in CMOS FGs because they do not have extended drains.
Modeling of injection is more complex than modeling of tunneling because injection is a multivariate phenomena (i.e. it depends upon both the channel current and the channel-to- drain electric field) and because injection is defined by a larger number of process parameters.
Most injection modeling has focused on nFETs, which further complicates injection modeling for CMOS FGs wherein pFETs are preferred over nFETs. To improve modeling of CMOS FGs, we present injection data from 30 FGs with varying widths, lengths, oxide thicknesses, and junction depths. We show that two extracted parameters are sufficient to describe these data.
7.2.1 Injection Measurement
Figure 7.4(a) shows our setup for measuring injection. The FG transistor is placed in a linearized loop, as described in Chapter 6. The loop maintains constant Id and constant Vsd; consequently, Iinj is constant. To obtain Iinj, the voltage at Vcg is measured during the experiment. Electrons injected onto the floating gate give the FG voltage a more negative charge, which the linearization loop counteracts by raising Vcg. As a result, Iinj =CgdVdtcg.
Figure 7.4(b) shows the measurement of one value ofIinj. The slope of Vcg is used to ob- tainIinj for one pair ofId andVsd values. A full injection characterization of a FG transistor is obtained by repeating this measurement for multiple values of Id and Vsd, which are con- troled byV1 andV2, respectively. An ammeter is used to measureIdat each value ofV1. The op-amp forces Vsd =V2. The full injection characterization for one FG transistor is shown in Fig. 7.4(c). In the remainder of this Section, we describe a method for parameterizing injection in pFETs.
A V1
V2
Iinj
Id Vcg
Vs
0 0.5 1 1.5 2
0 1 2 3 4 5 6 7
Time (s)
Voltage
Vcg (Measured) Vcg (Fit)
10-9 10-8 10-7 10-6 10-5
10-4 10-3 10-2 10-1 100 101 102
Drain Current (A) d/dt Vcg(V/s)
(b) (a)
(c)
Vds = 3.5V Vds = 5.5V
Figure 7.4: Methodology for characterizing injection. (a) Measurement setup. The injection current is obtained by measuring the change inVcg under constant drain current and source- to-drain voltage. (b) Measurement of the change inVcg. The slope is extracted to obtain the injection current. (c) Measured injection rate at various drain currents and source-to-drain voltages.
7.2.2 Injection Parameterization
Hot-electron injection in pFETs is a multi-event process [149]. First, a hole crossing the channel is accelerated in the high-field region of the drain. Second, this hot hole impacts
Brandon D. Rumberg Chapter 7. Floating-Gate Modeling 83 the lattice and thus releases a hot electron. And third, this hot electron is swept over the gate-oxide potential-barrier to the more positive voltage of the gate. Each event relies on the previous and has a limited probability of occurring.
Various models of the injection process have been developed [154, 155]. We have ob- tained the best matching to experimental data using the “lucky-electron model,” which was developed by Shockley in 1961 for p-n junctions [156], applied to hot-carrier gate current in nFETs by Hu in 1979 [157, 158], and then extended to pFETs by Ong in 1990 [154].
In the lucky-electron interpretation, each carrier has a limited probability of causing the chain of events that lead to an electron being injected onto the gate. Therefore, increasing the channel current increases the injection current by simply increasing the number of injection opportunities. Additionally, increasing the source-to-drain voltage will increase the electric field near the drain (while the device remains in saturation) and will thus increase the probability that a hole will create a hot electron. The last key to facilitate injection is that the gate-to-drain voltage should be high enough to sweep the hot electrons over the gate-oxide potential barrier.
Before we introduce the lucky-electron equation, let us revisit the subthreshold-region injection approximation that we used to simplify hand calculations in Chapter 6:
Iinj ≈βIsαeVsd/Vinj (7.4)
whereIsis the source current, and β,α, andVinj are device-dependent fits [136,159]. In Fig.
7.4(c), the subthreshold region is approximately the range whereId<1àA. Since the slope, α, is a weak function of Vsd in the subthreshold region, (7.4) is valid if Vsd is constrained to a limited range. This equation is consistent with the interpretation of injection that was described above: greater current tranlates to more opportunities for injection and greater source-to-drain voltage translates to higher probability of injection. However, (7.4) is clearly not sufficient for all operating regions.
The equation that we use for lucky-electron injection, shown below in (7.8), comes from [160]; here we summarize the elements that make up the equation. The form of the lucky- electron equation is [154]
Iinj =γIdEmexp
− δ Em
(7.5) where γ and δ are fits that are invariant to the fabrication process and to the dimensions of the device, and Em is an approximation for the maximum field at the drain. The maximum field can be calculated as [160]
Em= Vsd−Vsd,sat
l = Vgd+VT0
l (7.6)
whereVsd,sat is the saturation voltage,VT0 is the threshold voltage, and l is the length of the velocity saturation region near the drain, which can be calculated as [160]
l= 0.22t1/3ox x1/2j (7.7)
where tox is the gate oxide thickness and xj is the diffusion-area junction depth, both of which can be obtained from simulation model files. Combining these yields the expression
10-8 10-7 10-6 10-5 10-16
10-15 10-14 10-13 10-12 10-11 10-10
Id I inj
0.35àm, 3V 0.35àm, 5V 0.5àm, 5V
(b) (c)
(a)
2.5 3 3.5 4 4.5 5
x 10-8 10-11
10-10 10-9 10-8 10-7 10-6 10-5
(0.22 t ox 0.33 X
j 0.5)/(V
gd+V t) Iinj/[Id (Vgd+Vt)]
0.35àm, 3V 0.35àm, 5V 0.5àm, 5V Fit
0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 10-11
10-10 10-9 10-8 10-7 10-6 10-5
1/(Vgd+V t) Iinj/[Id (Vgd+Vt)]
0.35àm, 3V 0.35àm, 5V 0.5àm, 5V
Figure 7.5: Extraction of injection parameters. (a) Raw injection current data for 30 FG transistors with various dimensions and in different processes. (b) Injection curves normal- ized for transistor W and L and also for Vsd. (c) Injection curves further normalized for oxide thickness and junction depth. The fit uses (7.8) withγ = 3 and δ= 4.9×108.
that we use to model injection
Iinj =γId Vgd+VT0
0.22t1/3ox x1/2j exp −δ0.22t1/3ox x1/2j Vgd+VT0
!
(7.8) To extract the parameters γ and δ, we characterized 30 FG transistors:
1. In a 0.35àm CMOS process: Seven different transistor dimensions (W /L) were used for the FGs (àm/àm): 2/0.5, 2/1, 2/2, 1/0.7, 4/0.7, 8/0.7, and 8/2. For each size,
Brandon D. Rumberg Chapter 7. Floating-Gate Modeling 85 both a thin-oxide (3V) and a thick-oxide (5V) device are included for a total of 14 devices.
2. In a 0.5àm CMOS process: Sixteen different transistor dimensions (W /L) were used for the FGs (àm/àm): 3/0.6, 6/0.6, 12/0.6, 24/0.6, 3/1.2, 6/1.2, 12/1.2, 24/1.2, 3/2.4, 6/2.4, 12/2.4, 24/2.4, 3/4.8, 6/4.8, 12/4.8, and 24/4.8. The 0.5àm FGs were all thin- oxide (5V) devices.
The 0.5àm devices were measured at Vsd=5V. The 0.35àm devices were measured for six linearly spaced Vsd values from 4.6V to 5.5V.
All of the measured data are shown in their raw form in Fig. 7.5(a). These data are first normalized by transforming them into the form of (7.8), but without normalizing forl.
This normalization is achieved by plotting the data using 1/(Vgd+VT0) for the x-axis and using Iinj/[Id(Vgd+VT0)] for the y-axis. The result is shown in Fig. 7.5(b). Each of the three device types cluster into straight lines, regardless of the source-to-drain voltage and regardless of the width (W) and length (L) of the transistor. If Vsd and Id are held fixed, then increasing W/L will increase the injection current because a smaller value of Vsg will be required, which will thus increase Vgd. However, when the data are visualized in terms of Vgd, then the dependence onW/L disappears.
The final step in extracting the injection parameters is to normalize across device types.
In Fig. 7.5(b), the two 0.35àm devices have the same junction depth xj, and the two 5V devices have approximately the same oxide thicknesstox. By further normalizing the data by l, all three devices cluster on a single line. Consequently, devices with varying size and across different processes can be described by a single equation, (7.8), and by two parameters,γ = 3 and δ = 4.9×108. The only other parameters (tox, xj, and VT0) can be obtained from the device model. As a result, it is simple to incorporate injection into floating-gate simulation models, such as [144].