Apple macbook pro a1278 820 3115 b (MLB j30) 051 9058

ININOUT OUTIN ININOUT OUTIN I TO MAINTAIN THIS DOCUMENT IN CONFIDENCEIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT EMI TALL POGO PINS USB Signals Unus

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TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

2 ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC

3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK APPD

C

A

D DATE

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

1 OF 109 6.0.0 051-9058

12/21/2011 YONAS_J30

45 49 SMC

02/15/2011 K90I_MLB

44 48

Front Flex Support

07/08/2011 J31_MLB

11/08/2011 YONAS_J30

02/15/2011 K90I_MLB

06/23/2011 K90I_MLB

39 42

FireWire Port & PHY Power

02/15/2011 K90I_MLB

37 40

Ethernet Connector

06/15/2011 J31_MLB

02/15/2011 K90I_MLB

35 38

T29 Power Support

02/15/2011 K90I_MLB

33 36

T29 Host (1 of 2)

02/15/2011 K90I_MLB

06/13/2011 J31_MLB

31 34

DDR3/FRAMEBUF VREF MARGINING

11/03/2011 YONAS_J30

02/15/2011 K90I_MLB

29 31

DDR3 SO-DIMM Connector B

02/15/2011 K90I_MLB

09/19/2011 LINDA_J30

02/15/2011 K90I_MLB

06/13/2011 J31_MLB

02/15/2011 K90I_MLB

06/13/2011 J31_MLB

16 18

PCH SATA/PCIe/CLK/LPC/SPI

02/15/2011 MASTER

09/27/2011 JACK_J30

14 16

CPU DECOUPLING-I

02/15/2011 MASTER

12 13

CPU POWER

02/15/2011 MASTER

02/15/2011 K90I_MLB

Power Aliases

02/15/2011 K90I_MLB

BOM Configuration

02/15/2011 K90I_MLB

03/26/2009 K20A_MLB

02/15/2011 MASTER

02/15/2011 109

86

02/15/2011 108

85

02/15/2011 106

84

02/15/2011 105

83

02/15/2011 104

82

02/15/2011 103

81

02/15/2011 102

80

02/15/2011 101

79

02/15/2011 100

78

07/08/2011 97

77

02/15/2011 94

76

02/15/2011 93

75

02/15/2011 90

74

02/15/2011 79

73

02/15/2011 78

72

07/28/2011 77

71

09/28/2011 76

70

07/28/2011 75

69

08/03/2011 74

68

07/28/2011 73

67

08/22/2011 72

66

09/28/2011 71

65

09/27/2011 70

64

07/29/2011 69

63

02/20/2012 68

62

11/10/2011 67

61

07/25/2011 66

60

07/25/2011 65

59

02/16/2012 64

58

07/25/2011 62

57

02/15/2011 61

56

02/15/2011 59

55

09/28/2011 58

54

07/01/2011 57

53

02/15/2011 56

52

08/01/2011 55

51

11/03/2011 54

50

09/28/2011 53

49

02/15/2011 52

48

06/15/2011 51

47

TITLE=MLB

01/02/2012 50

K90I_MLB

SCHEM,MLB,J30 SCH CRITICAL1

051-9058

1820-3115 PCBF,MLB,J30 PCB CRITICAL

SCHEM,MLB,J30

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCEIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

USB

IR Controller

PG 25

HUB USB

1 2 3

KEYBOARD

XHCI EHCI U2760

PG 40

E-NET CONN

CONN

SD Card

PG 30

PG 61 J6700 J6701 U6400

PG 37

U6610, U6620, U6630

PG 60

SPEAKER AMPs

CONNs AUDIO

PG58MIC BIAS

EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT

PG 57

Codec AUDIO

From PCH

PG 23

PCH XDP CONN

PG 63-73

POWER SUPPLY

SPI Boot ROM

U5511

PSOC TP/KB

I2C

PG 45

SMCSMS ADC Ser

051-9058 6.0.0

2 OF 109

2 OF 86

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ENABLE

3.425V G3HOT

R7640PM6640

PP3V3_S5_REGPP5V_S3_REG

PP3V3_ENETQ7922

U3900

BCM57765

14 22

14-1 14-1

P3V3S3_EN

RC

DELAY

PM_SLP_S4_LU1800

13-1 15 11

R6990J30 POWER SYSTEM ARCHITECTURE

MAX15119GTMVR_ON

PGOOD VLDOIN

PGOOD

(PAGE 63)U6990

PP3V42_G3H_REG

22-1

R5320SMC_CPU_VSENSE

PM_RSMRST_LPM_DSW_PWRGD

30

10 12

PM_DSW_PWRGD

26

4 6-1

CPUIMVP_VR_ONPM_RSMRST_L

PM_SYSRST_L

SMC_RESET_LPM_PWRBTN_L

4

SN0903048(PAGE 44)U5010SMC PWRGD

SMC_GFX_VSENSE

3

R5330

VCPU VCORE

1.05VISL95870

VCC

U7600

VIN

21 15

2

D6990

AR5400

R6905

Q5300V

26-1

16

Q7801PP1V5_S3RS0_FET

23-1 23

SLP_S5_L(P95)

PWR_BUTTON(P90) RSMRST_IN(P13)

U4900(PAGE 43)

PM_SLP_S5_L

RSMRST_PWRGD

PM_SLP_S4_L PM_SLP_S3_L

19

U7960

VMON_Q2 VMON_Q4 VMON_Q3

EN

PPVTT_S0_DDR_LDO

VOUT1 VOUT2

VIN

1.5V

0.75VS5S3

VOUT PGOOD

15

VID1

VCC EN

PP5V_S0_FETQ7860

SMC_RESET_L

Q5310VSMC_DCIN_ISENSE

F69056A FUSE

13 7

PBUSVSENS_ENP3V3S0_EN

(PAGE 16~21)

P5VS0_EN

21 21

17 19

1V05_S0_LDO_ENCPUVCCIOS0_EN

3 OF 109

www.qdzbwx.com

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PROTO:

Revision History

SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011

051-9058 6.0.0

4 OF 109

4 OF 86

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TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

BOM OPTIONS BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEMBOM OPTIONS

BOM NAME BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

QTY

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

Programmable Parts

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN

516S0806 1 J3100 CRITICAL SODIMM:FOXCONN

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2514B J30_DEBUG:PVT

J30_DEVEL:ENG BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS_CONN:YES,LOADISNS:YES,DDRVREF_DAC,S0PGOOD_ISL

MIKEY,TPAD:Z2,RAMCFG_SLOTJ30_COMMON2

J30_COMMON ALTERNATE,COMMON,J30_COMMON1,J30_COMMON2,J30_DEBUG:ENG,J30_PROGPARTS,T29BST:Y,TBTHV:P15V

J30_COMMON1 BATT_3S,CPUMEM_S0,USBHUB2513B,HUB_3NONREM,T29:YES,SDRV_PD,SDRVI2C:MCU,AXG_PHASE1,BTPWR:S4,UV_GLUE_J30

LPCPLUS_CONN:YES,XDP_CONN J30_DEVEL:PVT

DEVEL_BOM,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO_DAC J30_DEBUG:ENG

J30_CMNPTS,CPU_2_9GHZ,SODIMM:HYBRID,EEEE_F1YH639-3756 PCBA,MLB,HYB,2.9G,J30

PCBA,MLB,MOL,2.9G,J30 J30_CMNPTS,CPU_2_9GHZ,SODIMM:MOLEX,EEEE_F1YK639-3752

POWER FETS PAIR,RENESAS,PBUS_CHARGER,J30 CHARGER_POWER_FET:REN607-9311

LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

516S0805 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX J3100 CRITICAL SODIMM:HYBRID

J30_CMNPTS,CPU_2_9GHZ,SODIMM:FOXCONN,EEEE_F1YGPCBA,MLB,FOX,2.9G,J30

607-8722 POWER_FETS PAIR,FAIRCHILD,5V_S3,J30 CSET2 CRITICAL

FET_PAIRCSET1

1607-8721 POWER_FETS PAIR,FAIRCHILD,DDR,J30 CRITICAL

EEEE_F1YL[EEEE:F1YL] CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM826-4393 1

EEEE_F1YM[EEEE:F1YM]

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL

EEEE_F1YJ[EEEE:F1YJ]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_F1YG[EEEE:F1YG] CRITICAL

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_F1YH[EEEE:F1YH]

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL

CRITICAL085-3092 1 J30 MLB DEVELOPMENT DEVEL DEVEL_BOM

CRITICAL J30_CMNPTSCMNPTS

CMN PTS,PCBA,MLB,J301

607-8895

Coilcraft alt to Murata

152S1499

155S0367 155S0578

Renesas alternate to fairchild

Fairchild alt to Fairchild 376S0958

Murata alt to Taiyo ALL

138S0660 138S0684

Coilcraft alt to Murata

CRITICAL ENET_PROG341S3096 1 IC ENET,1!MBITFLAH,CIV REV01,K9x U3990

U9330IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

337S3997 1 CRITICAL T29MCU:BLANK

1341S3365 IC,PROGRMD,T29,PORT MCU,K90IA,K91A,K92A U9330 CRITICAL T29MCU:PROG

CMN PTS,PCBA,MLB,J30 J30_COMMON,FET_PAIR607-8895

POWER FETS PAIR,FAIRCHILD,DDR,J30

J30_CMNPTS,CPU_2_5GHZ,SODIMM:HYBRID,EEEE_F1YJPCBA,MLB,HYB,2.5G,J30

639-3755

J30_CMNPTS,CPU_2_5GHZ,SODIMM:MOLEX,EEEE_F1YMPCBA,MLB,MOL,2.5G,J30

639-3751

POWER FETS PAIR,RENESAS,5V_S3,J30 5V_S3_POWER_FET:REN607-9310

1343S0534 IC,BCM57765B0,ENET&SD,8X8 U3900 CRITICAL

IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA

337S4265 1 U1000 CRITICAL CPU_2_9GHZ

CONN,204P,SODIMM,DDR3,P=0.6MM,MOLEX

516-0245 1 J2900 CRITICAL SODIMM:MOLEX

1 IC,T29,PRQ,S LJJY,FCBGA,15x15MM,C1338S1072 U3600 CRITICAL T29:YES

516-0246 1 CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN J2900 CRITICAL SODIMM:HYBRID

516S0805 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX J3100 CRITICAL SODIMM:MOLEX

IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN353S3055 1 U9390 CRITICAL

1337S4269 PANTHERPOINT,C1,SLJ8C,PRQ,BD82HM77 U1800 CRITICAL

337S4113 1 IC,IVB,2C,35W,1023BGA U1000 CRITICAL CPU_IVB_2C

337S4264 1 IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA U1000 CRITICAL CPU_2_5GHZ

SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB

BOM Configuration

BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,LOADISNS:NO,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2513B J30_DEBUG:PROD

J30_PROGPARTS BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG

IC,SMC,EXTERNAL,FSB,A3,J30341S3300 1 U4900 CRITICAL SMC_PROG

IC,T29 EEPROM,LR,J30/J31341S3430 1 U3690 CRITICAL T29ROM:PROG

T29ROM:BLANK335S0550 1 IC,EEPROM,SERIAL,SPI,4Kx8,1.8V,MLP8,LF U3690 CRITICAL

U3990335S0862 1 IC,FLASH,SERIAL,SPI,!MBIT,2V7,REV F CRITICAL ENET_BLANK

1 IC,EFI,V00C7,J30/J31 U6100 CRITICAL BOOTROM_PROG341S3558

051-9058 6.0.0

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(NEED 2 TP)(NEED 2 TP)

I273 I274 I275 I278

I280 I281

I282 I283

I285 I287

I288

I289 I290 I292 I293

I294 I295

I297

I298 I299 I300 I301 I302 I303

I330

I331 I332 I333

I334 I335

I336 I337 I338 I339 I340 I341 I342 I343

I344 I345 I346

I347

I348 I349

I350

I351 I352

I353

I354 I355

I356

I357 I358 I359 I360 I361

I362 I363 I364 I365 I366 I368 I369 I370

I371 I372 I374 I375

I376

I377

I380 I382 I383 I386 I388 I390 I391 I392

I394

I407

I408 I409 I410

I414

I416

I417

I418 I419

I491 I492

I493 I494 I495 I496 I497 I498 I499 I500

I517 I518 I519 I520 I521 I522

I540 I541 I542 I543 I544 I545 I546 I547

I593 I594 I595

I596 I597 I598 I599 I600 I601 I602 I603 I604 I605 I606 I607 I608 I610 I611 I612 I613 I614 I616 I617 I618 I619 I620 I622 I625

PP3V3_WLANTRUE

PP18V5_Z2TRUE

Z2_MISOTRUE

SMC_SSD_THROTTLE_RTRUE

SPKRAMP_R_P_OUTTRUE

BI_MIC_SHIELDTRUE

NC_CRT_IG_DDC_DATAMAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

NC_SATA_C_R2D_CNMAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RNTRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RPTRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CNMAKE_BASE=TRUE

TRUENC_FW643_FW620_L

TRUE MAKE_BASE=TRUE

NC_FW643_TMSTRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

NC_FW643_TCKTRUE

NC_FW643_SMMAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE NC_HDA_SDIN2MAKE_BASE=TRUE

TRUE NC_HDA_SDIN1TP_HDA_SDIN1

TP_PCH_LVDS_VBGTP_LVDS_IG_CTRL_DATATP_LVDS_IG_CTRL_CLK

PP3V3_WLANTRUE

Z2_DEBUG3TRUE

Z2_MOSITRUE

LPC_CLK33M_LPCPLUSTRUE

PP5V_S0TRUE

WS_KBD11TRUE

WS_KBD16_NUMTRUE

WS_KBD18TRUE

WS_KBD17TRUE

TP_PCI_PME_LTP_CRT_IG_VSYNC

TP_SATA_D_R2D_CPTP_SATA_D_D2RPTP_SATA_D_D2RNTP_CLINK_DATA

TP_PCH_GPIO65_CLKOUTFLEX1TP_PCH_GPIO66_CLKOUTFLEX2TP_PCH_GPIO67_CLKOUTFLEX3TP_PCH_GPIO64_CLKOUTFLEX0TP_XDP_PCH_HOOK5TP_XDP_PCH_HOOK4

TP_SATA_E_R2D_CPTP_SATA_F_D2RNTP_SATA_F_D2RPTP_SATA_F_R2D_CNTP_SATA_F_R2D_CP

TP_SDVO_STALLPTP_SDVO_INTNTP_SDVO_INTPTP_SDVO_STALLNTP_SDVO_TVCLKINN

SMC_BS_ALRT_L

TP_LVDS_IG_B_CLKPTP_LVDS_IG_B_CLKNTP_LVDS_IG_BKL_PWMTP_T29_PCIE_RESET3_L

TP_EDP_TX_P<0 3>

TP_EDP_AUX_P TP_EDP_TX_N<0 3>

TP_CPU_THERMDA TP_CPU_THERMDC

TP_EDP_AUX_N

=PEG_R2D_C_N<8 11>

TP_CRT_IG_BLUETP_CRT_IG_GREEN

TP_HDA_SDIN3TP_PCI_CLK33M_OUT3

TP_PCIE_CLK100M_PEBN

TP_CRT_IG_HSYNCTP_CRT_IG_DDC_CLKTP_CRT_IG_RED

TP_FW643_OCR10_CTLTP_FW643_FW620_LTP_FW643_TMSTP_FW643_SMTP_FW643_SDA

TP_XDPPCH_HOOK3TP_XDP_PCH_OBSFN_D<0 1>

TP_FW643_TDITP_FW643_AVREGTP_FW643_VBUF

LPC_FRAME_LTRUE

LPCPLUS_GPIOTRUE

LPC_AD<3>

TRUE

LPC_SERIRQTRUE

WS_KBD1TRUE

WS_KBD9TRUE

MAKE_BASE=TRUE TRUE NC_SATA_F_R2D_CN

NC_CLINK_RESET_LMAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE NC_CLINK_CLK

TRUE MAKE_BASE=TRUENC_PCH_GPIO67_CLKOUTFLEX3MAKE_BASE=TRUE

TRUE NC_PCH_GPIO65_CLKOUTFLEX1MAKE_BASE=TRUE

TRUE NC_PCH_GPIO64_CLKOUTFLEX0

NC_TP_XDP_PCH_HOOK4MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUENC_FW643_AVREGTRUE

MAKE_BASE=TRUENC_FW643_TDI

XDP_AP_CLKREQ_LTRUE

XDP_PCH_AUD_IPHS_SWITCH_ENTRUE

XDP_FW_CLKREQ_LTRUE

XDP_PCH_PWRBTN_LTRUE

XDP_PCH_ISOLATE_CPU_MEM_LTRUE

XDP_PCH_S5_PWRGDTRUE

XDP_PCH_SDCONN_DET_LTRUE

XDP_PCH_ENET_PWR_ENTRUE

XDP_PCH_SDCONN_STATE_RST_LTRUE

XDP_PCH_AP_PWR_ENTRUE

XDP_PCH_USB_HUB_SOFT_RST_LTRUE

NC_FW0_TPBNTRUE

NC_FW0_TPAPTRUE

NC_FW0_TPBPTRUE

TRUE NC_FW2_TPAPTRUE NC_FW2_TPANTRUE NC_FW2_TPBIAS

NC_FW2_TPBNTRUE

NC_FW2_TPBPTRUE

MAKE_BASE=TRUE TRUE NC_TP_XDP_PCH_OBSFN_A<0 1>

NC_LVDS_IG_BKL_PWMTRUE

MAKE_BASE=TRUE

WS_KBD12TRUE

TRUE

MAKE_BASE=TRUE TRUE NC_SATA_E_R2D_CN

TRUE MAKE_BASE=TRUE

NC_SATA_E_D2RN

NC_PCIE_CLK100M_PE6PMAKE_BASE=TRUE

TRUE TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6NNC_PCIE_CLK100M_PE5PTRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

WS_LEFT_SHIFT_KBDTRUE

MAKE_BASE=TRUE TRUE NC_SDVO_STALLPTRUE

MAKE_BASE=TRUE

NC_SDVO_STALLN

NC_SMC_BS_ALRT_LTRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKNMAKE_BASE=TRUE

TRUENC_LVDS_IG_B_CLKPTRUE

MAKE_BASE=TRUE

PCH_VSS_NCTF<12>

TRUEPCH_VSS_NCTF<11>

TRUEPCH_VSS_NCTF<9>

TRUE TRUE PCH_VSS_NCTF<5>

TRUE PCH_VSS_NCTF<2>

TRUE PCH_VSS_NCTF<1>

TRUE MAKE_BASE=TRUETP_T29_PCIE_RESET2_LMAKE_BASE=TRUE

TRUE TP_T29_PCIE_RESET1_L

TRUE MAKE_BASE=TRUE NC_TBT_MONDC0TRUE

MAKE_BASE=TRUE NC_TBT_MONOBSPTRUE

MAKE_BASE=TRUE NC_TBT_MONOBSN

MAKE_BASE=TRUE TRUE TP_T29_PCIE_RESET3_L

MAKE_BASE=TRUE TRUE TP_T29_PCIE_RESET0_L

MAKE_BASE=TRUE TRUE NC_SDVO_TVCLKINPTRUE

NC_PCIE_CLK100M_PE4P

TRUE MAKE_BASE=TRUE

NC_CRT_IG_REDNC_CRT_IG_GREENTRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNCTRUE

MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLKTRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNCTRUE

NC_LVDS_IG_CTRL_CLKMAKE_BASE=TRUE

TRUENC_LVDS_IG_CTRL_DATAMAKE_BASE=TRUE

TRUE

NC_PCH_LVDS_VBGMAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE NC_CLINK_DATA

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

NC_PCI_CLK33M_OUT3TRUE

MAKE_BASE=TRUE

NC_FW643_OCR10_CTLTRUE

MAKE_BASE=TRUE

NC_FW643_VBUFTRUE

MAKE_BASE=TRUE

NC_FW643_SDAMAKE_BASE=TRUE

TRUE

PP1V8_S0TRUE

NC_SATA_D_R2D_CPMAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE NC_TP_XDPPCH_HOOK2MAKE_BASE=TRUE

TRUE NC_TP_XDP_PCH_OBSFN_B<0 1>

TRUE MAKE_BASE=TRUENC_TP_XDPPCH_HOOK3

TRUE NC_SATA_E_R2D_CPMAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_SDVO_INTN

MAKE_BASE=TRUE NC_EDP_TXP<0 3> TRUE

NC_CRT_IG_BLUETRUE

MAKE_BASE=TRUE

NC_PCI_PME_LTRUE

MAKE_BASE=TRUE

NC_SATA_C_R2D_CPMAKE_BASE=TRUE

TRUE

WS_KBD14TRUE

TRUE MAKE_BASE=TRUE NC_TBT_MONDC1

WS_KBD4TRUE

WS_LEFT_OPTION_KBDTRUE

WS_CONTROL_KBDTRUE

PP5V_S3TRUE

PP18V5_DCIN_FUSETRUE

TP_XDPPCH_HOOK2TP_XDP_PCH_OBSFN_B<0 1>

TP_XDP_PCH_OBSFN_A<0 1>

MAKE_BASE=TRUE TRUE NC_SATA_F_D2RP

TP_SATA_D_R2D_CNTP_SATA_C_R2D_CPTP_SATA_C_R2D_CNTP_SATA_C_D2RNTP_PSOC_P1_3

TP_PCIE_CLK100M_PE5NTP_PCIE_CLK100M_PE4PTP_PCIE_CLK100M_PE4N

NC_PEG_D2RN<8 11>

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_SATA_C_D2RPTRUE

MAKE_BASE=TRUE

NC_SATA_C_D2RNTRUE NC_PSOC_P1_3MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7PTRUE

MAKE_BASE=TRUETP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE6PTP_PCIE_CLK100M_PE6NTP_CLINK_CLK

TP_CLINK_RESET_LTP_PCIE_CLK100M_PEBP

TP_FW643_TCK

TRUE MAKE_BASE=TRUENC_TP_XDP_PCH_OBSFN_D<0 1>

TP_TBT_MONOBSNTP_TBT_MONOBSPTP_TBT_MONDC1TP_TBT_MONDC0

TRUE MAKE_BASE=TRUE

NC_SATA_F_D2RN

TP_DP_T29SRC_ML_CP<0 3>

TP_DP_T29SRC_ML_CN<0 3> MAKE_BASE=TRUE

TRUE NC_DP_T29SRC_ML_CP<0 3>MAKE_BASE=TRUE

TRUE NC_DP_T29SRC_ML_CN<0 3>TRUE

MAKE_BASE=TRUENC_DP_T29SRC_AUXCH_CNTRUE

MAKE_BASE=TRUENC_DP_T29SRC_AUXCH_CPTP_T29_PCIE_RESET2_L

TP_T29_PCIE_RESET1_LTP_T29_PCIE_RESET0_LTP_DP_T29SRC_AUXCH_CNTP_DP_T29SRC_AUXCH_CP

Z2_RESETTRUE

PSOC_MOSITRUE

PSOC_SCLKTRUE

SMBUS_SMC_2_S3_SCLTRUE

SMBUS_SMC_2_S3_SDATRUE

PSOC_F_CS_LTRUE

PICKB_LTRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

Z2_CS_LTRUE

PP3V3_S4TRUE

SMBUS_SMC_2_S3_SCLTRUE

SPI_ALT_CS_LTRUE

SPI_ALT_CLKTRUE

SPI_ALT_MISOTRUE

SPIROM_USE_MLBTRUE

SPI_ALT_MOSITRUE

TRUE MAKE_BASE=TRUENC_PCH_GPIO66_CLKOUTFLEX2

NC_TP_XDP_PCH_HOOK5MAKE_BASE=TRUE

TRUE

PM_SLP_S4_LTRUE

SMC_PM_G2_ENTRUE

PP1V5_S3TRUE

PP4V5_AUDIO_ANALOGTRUE

Z2_BOOST_ENTRUE

PP5V_S0TRUE

SPKRAMP_SUB_N_OUTTRUE

LED_RETURN_1TRUE

LED_RETURN_3TRUE

LED_RETURN_5TRUE

LVDS_CONN_A_CLK_F_PTRUE

Trang 7

Chipset "VCore" Rails

"G3Hot" (Always-Present) Rails

2A max supply

21

XW0800

SM

21

VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP1V05_SUSMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MMPP1V05_S0_PCH

=PP3V3_S4_BT

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE VOLTAGE=3.3VPP3V3_S4

MAKE_BASE=TRUE

VOLTAGE=18.5VPPDCIN_G3HMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE

PP3V3_SUSMIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

MAKE_BASE=TRUEPPVCORE_S0_AXGMIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

VOLTAGE=1.05VPP1V05_S0_CPU_VCCPQEMAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM MAKE_BASE=TRUE VOLTAGE=1.0VPP1V0_FW_FWPHY

MAKE_BASE=TRUE VOLTAGE=12.8V MIN_NECK_WIDTH=0.2 MMPPVP_FW

MAKE_BASE=TRUE

PP3V3_FW_FWPHYMIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V VOLTAGE=12.8V

PPVIN_SW_T29BST

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP1V05_T29MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PPVCORE_S0_CPUMIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.25V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=1.5V MIN_NECK_WIDTH=0.2 MMPP1V5_S3_CPU_VCCDQMIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05VPP1V05_S0_PCH_VCCADPLL

=PP5V_S0_BKL

=PP5V_S3_ODD

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8VPPBUS_G3H

PP5V_S0_HDDMIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_NECK_WIDTH=0.2 MMPP1V8_S0

PP1V5_S3_DDRMIN_LINE_WIDTH=0.8 MM MAKE_BASE=TRUE VOLTAGE=1.5V

PP1V5_S3MIN_LINE_WIDTH=0.8 MM VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm VOLTAGE=0.75V MAKE_BASE=TRUEPP0V75_S0_DDRVTTMIN_NECK_WIDTH=0.17 mm

=PP0V75_S0_MEM_VTT_A

VOLTAGE=0.75V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PPVTTDDR_S3MIN_LINE_WIDTH=0.3 MM

PP3V3_S0MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

=PP3V3_S3_USBMUX

=PP3V3_S3_ISNS

051-9058 6.0.0

Trang 8

ININOUT

OUTIN

ININOUT

OUTIN

EMI TALL POGO PINS

USB Signals

Unused T29 Ports

EMI IO (SHORT) POGO PINS

MLB MOUNTING (TO C BRACKET) SCREW HOLES

MLB MOUNTING (TO TOPCASE) SCREW HOLES

OMIT3R2P5

1

ZS09091.4DIA-SHORT-SILVER-K99 SM

1

ZS09021.4DIA-SHORT-SILVER-K99 SM

3R2P5OMIT

1Z0909

3R2P5OMIT

1Z0910

OMIT3R2P5

1Z0907

3R2P5OMIT

402 MF-LF

05%

MF-LF 5%

402100K

2.2K

2

1

R09242.2K

402MF-LF5%

33

21R0960

5%

805

01/8W

21R0970201 51

21R0971201 1/20W515%

21R0973201 1/20W

21R0972201 5%

1/20W51

2

1

R0940

1/16W5%

1K

MF-LF402

Signal Aliases

MIN_NECK_WIDTH=0.2MMGND

VOLTAGE=0V

T29_A_BIAS

JTAG_ISP_TCKMAKE_BASE=TRUE

T29_A_BIAS_R2DP1

USB_EXTD_XHCI_NUSB_EXTD_XHCI_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_USB_EXTD_XHCIP

NO_TEST=TRUE MAKE_BASE=TRUE

NC_USB_EXTD_XHCIN

USB3_EXTC_RX_NUSB3_EXTC_RX_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_USB3_EXTC_RXPNC_USB3_EXTC_RXN

MAKE_BASE=TRUETP_CPU_VTT_SELECT CPU_VTTSELECT

TP_CPU_THERMDNMAKE_BASE=TRUE

CPU_THERMD_NTP_CPU_THERMDP

MAKE_BASE=TRUE

CPU_THERMD_P

CPU_VCCIO_SEL

USB_TPAD_PMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_USB_EXTCN

USB3_EXTC_TX_P

MAKE_BASE=TRUET29_LSOE<3>

T29_LSEO<2>

USB3_EXTD_RX_P

NC_USB_EXTCP

USB_SMC_NUSB_IR_PMAKE_BASE=TRUE

USB_IR_NMAKE_BASE=TRUE

USB_EXTC_PUSB_SMC_P

NC_USB3_EXTC_TXNTP_PCH_CLKOUT_DPP

JTAG_ISP_TDIMAKE_BASE=TRUE

NC_USB_EXTD_EHCIPMAKE_BASE=TRUE NO_TEST=TRUE

=PEG_D2R_P<12 15>

MAKE_BASE=TRUE NO_TEST=TRUENC_USB3_EXTD_TXPNC_USB3_EXTD_RXNMAKE_BASE=TRUE NO_TEST=TRUENC_USB3_EXTD_RXP

=PP1V05_S0_CPU_VCCPQE

=PP3V3_S0_DP_DDC

DPLL_REF_CLKNMAKE_BASE=TRUE MAKE_BASE=TRUEDPLL_REF_CLKP

MAKE_BASE=TRUENC_T29_D2RP<2 3>

NO_TEST=TRUE

T29_R2D_C_N<2 3>

DPA_IG_DDC_CLK

TP_LVDS_IG_B_CLKPMAKE_BASE=TRUE

DPB_IG_HPDTP_DP_IG_C_MLP<3 0>

TP_DP_IG_C_MLN<3 0>

DPB_IG_AUX_CH_PDPB_IG_AUX_CH_NTP_DP_IG_D_HPD

MAKE_BASE=TRUEDP_IG_D_CTRL_DATA

PPBUS_SW_LCDBKLT_PWRMAKE_BASE=TRUE

PM_SLP_S3_LMAKE_BASE=TRUEDPLL_REF_CLK_N

=TBT_S0_EN

=PP3V3_S0_DP_DDC

DP_EXTA_DDC_CLKMAKE_BASE=TRUE

DPA_IG_DDC_DATAMAKE_BASE=TRUE

DP_EXTA_DDC_DATANC_PCIE_PCH_D2RN<5 8>

MAKE_BASE=TRUE TRUEDPA_IG_AUX_CH_P

NC_PEG_CLK100MPMAKE_BASE=TRUE

TRUE NC_PCIE_PCH_R2D_CP<5 8>

MAKE_BASE=TRUE

NC_PCIE_PCH_R2D_CN<5 8>

TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE NC_PCIE_PCH_D2RP<5 8>

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_P<3 0>

MAKE_BASE=TRUEUSB_BT_N

NC_PCH_CLKOUT_DPN TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_TXPMAKE_BASE=TRUE NO_TEST=TRUE

NC_USB_EXTD_EHCINMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUEDP_EXTA_HPD

MAKE_BASE=TRUE VOLTAGE=12.6V MIN_NECK_WIDTH=0.375 MM MIN_LINE_WIDTH=0.5 MMPPBUS_SW_BKL

MAKE_BASE=TRUEDP_IG_D_CTRL_CLK

MAKE_BASE=TRUET29_LSOE<2>

DP_T29SNK0_AUXCH_C_PMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_T29SNK1_HPD

MAKE_BASE=TRUE

DP_T29SNK1_AUXCH_C_N

MAKE_BASE=TRUE

DP_T29SNK0_AUXCH_C_NMAKE_BASE=TRUE

DP_T29SNK0_ML_C_N<3 0>

MAKE_BASE=TRUETP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUEDP_T29SNK0_HPD

MAKE_BASE=TRUE NO_TEST=TRUENC_T29_D2RN<2 3>

NC_T29_R2D_CN<2 3>

MAKE_BASE=TRUE NO_TEST=TRUE

NC_T29_R2D_CP<2 3>

MAKE_BASE=TRUEFW643_WAKE_L

JTAG_ISP_TDOMAKE_BASE=TRUE

NC_PEG_CLK100MNMAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CN

MAKE_BASE=TRUEFW_PLUG_DET_L

DP_T29SNK1_ML_C_P<3 0>

DP_T29SNK1_AUXCH_C_P

TP_LVDS_IG_B_CLKNMAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<0 3>

NO_TEST=TRUENC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE MAKE_BASE=TRUELVDS_DDC_CLK

LCD_BKLT_PWMMAKE_BASE=TRUE MAKE_BASE=TRUELVDS_DDC_DATA

MAKE_BASE=TRUEDPB_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RPTRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RN

TRUE MAKE_BASE=TRUE NC_PCH_CLKOUT_DPP

NC_PCIE_CLK100M_EXCARDPTRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUENC_PCIE_CLK100M_EXCARDNMAKE_BASE=TRUE

TRUE NC_PCIE_EXCARD_R2D_CP

MAKE_BASE=TRUEMEMVTT_EN

DP_EXTA_ML_C_N<3 0>

MAKE_BASE=TRUEDP_EXTA_AUXCH_C_NMAKE_BASE=TRUE

DP_EXTA_AUXCH_C_PMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_EXTA_ML_C_P<3 0>

PCIE_PCH_R2D_C_P<5 8>

USBHUB_DN1_NUSBHUB_DN1_P

T29_A_BIAS

USB3_EXTD_TX_N

JTAG_TBT_TCKJTAG_TBT_TDI

TP_DP_IG_C_CTRL_CLKTP_DP_IG_C_CTRL_DATATP_DP_IG_D_CTRL_CLKTP_DP_IG_D_CTRL_DATA

PCIE_EXCARD_R2D_C_P

PCIE_PCH_D2R_N<5 8>

PCIE_PCH_D2R_P<5 8>

FW_PME_LTP_DP_IG_B_MLN<3 0>

BCM57765_CE_L_MS_INS_L

LVDS_IG_B_CLK_NLVDS_IG_B_DATA_P<0 3>

LVDS_IG_B_DATA_N<0 3>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_DDC_CLKLVDS_IG_BKL_PWMLVDS_IG_DDC_DATALVDS_IG_PANEL_PWRLVDS_IG_BKL_ONTP_PCH_CLKOUT_DPN

SMC_EXCARD_PWR_EN

DPA_IG_AUX_CH_N

=FW_PME_L

PCIE_EXCARD_D2R_NPCIE_EXCARD_D2R_PPCIE_EXCARD_R2D_C_NPCIE_CLK100M_EXCARD_N

USB3_EXTD_RX_NUSB3_EXTD_TX_P

USB3_EXTC_TX_NUSB_EXTC_NUSB_EXTD_EHCI_PUSB_EXTD_EHCI_NDPLL_REF_CLK_P

NO_TEST=TRUENC_LVDS_IG_B_DATAP<0 3>

MAKE_BASE=TRUE

NC_BCM57765_CE_L_MS_INS_L

PCIE_T29_R2D_C_P<3 0>

MAKE_BASE=TRUE

NO_TEST=TRUENC_USB3_EXTD_TXNMAKE_BASE=TRUE

NO_TEST=TRUENC_USB_SMCP

MAKE_BASE=TRUE

USBHUB_DN2_N

NO_TEST=TRUENC_USB_SMCN

MAKE_BASE=TRUEUSBHUB_DN2_PUSBHUB_DN3_PUSB_TPAD_N

MAKE_BASE=TRUE

USB_BT_PMAKE_BASE=TRUE

051-9058 6.0.0

Trang 9

INININ

OUT

IN

INININININININININININININININ

IN

ININININ

ININININININ

INININININOUT

OUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUT

ININININININININININININININININININOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTINININININ

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNCNC

NC

NCNC

NCNCNCNCNCNCNCNCNC

EDP_TX_3

EDP_TX_0EDP_TX_1EDP_TX_2

EDP_COMPIOEDP_HPDEDP_ICOMPOFDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3FDI1_TX_1FDI1_TX_0FDI1_TX_2FDI1_TX_3FDI0_FSYNCFDI1_FSYNCFDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1FDI0_TX_0FDI0_TX_2

DMI_RX_2*

DMI_RX_0DMI_RX_1DMI_RX_2DMI_RX_3DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0* PEG_ICOMPI

PEG_ICOMPOPEG_RCOMPOPEG_RX_2*

(1 OF 9)

NCNC

RSVD_26RSVD_27RSVD_25

RSVD_23RSVD_24RSVD_22RSVD_21RSVD_19RSVD_18

RSVD_16RSVD_17RSVD_15RSVD_14RSVD_13RSVD_12

DC_TEST_BG1DC_TEST_BD1DC_TEST_BE1

DC_TEST_BG3DC_TEST_BE3DC_TEST_BG4DC_TEST_BG58DC_TEST_BG59

DC_TEST_BE59DC_TEST_BG61

DC_TEST_BD61DC_TEST_BE61DC_TEST_D61

DC_TEST_A61DC_TEST_C61

DC_TEST_A59DC_TEST_C59DC_TEST_A58

DC_TEST_D3DC_TEST_D1DC_TEST_C4DC_TEST_A4

RSVD_45RSVD_44

RSVD_39RSVD_40RSVD_38RSVD_36RSVD_33

RSVD_31RSVD_32

RSVD_30CFG_3

CFG_2CFG_1CFG_0

CFG_9CFG_8CFG_7CFG_6

CFG_14CFG_12CFG_10

CFG_16CFG_17VCC_VAL_SENSE

RSVD_8RSVD_7RSVD_6

CFG_15CFG_13CFG_11

CFG_5CFG_4

VSS_VAL_SENSEVAXG_VAL_SENSEVCC_DIE_SENSEVSSAXG_VAL_SENSE

RSVD_11

RSVD_9RSVD_10

RSVD_20

SB_DIMM_VREFDQSA_DIMM_VREFDQ

RESERVED

NCNCNCNC

OUTOUT

Therefore, an inverting level shifter is required on the motherboard

(refer to latest Processor EDS for DC specifications)

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

FOR IVYBRIDGE PROCESSOR

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

This signal can be left as no-connect if entire eDP interface is disabled

If HPD is disabled while eDP interface is still enabled,

to low voltage signals for the processor

NOTE: The EDP_HPD processor input is a low voltage active low signal

shared with other interfaces

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals

These can be Placed close to J2500 and Only for debug access

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1

this alnalog sense due to accuracy concern

NOTE: Intel validation sense lines per

NOTE: Intel does not recommend to use

Note VOLTAGE=0VNote VOLTAGE=1.05VNote VOLTAGE=0VNote VOLTAGE=1.25V

even if internal Graphics is disabled since they are

to convert the active high signal from Embedded DisplayPort sink device

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard

1%

24.9

402 MF-LF PLACE_NEAR=U1000.G3:12.7MM

1K NOSTUFF

2

1

R1043

201 1/20W MF 5%

1K NOSTUFF

2

1

R1041

201 1/20W MF 5%

1K NOSTUFF

2

1

R1040

201 1/20W MF 5%

1K NOSTUFF

1%

MF-LF PLACE_NEAR=U1000.AF3:12.7MM

24.9

402

2 1R1031

402 1/16W

201 1/20W MF 5%

1K EDP

2

1R1046

201 1/20W MF

1/16W 402 MF-LF

49.9

1/16W 402 1%

AG4AF4

BGA

OMIT_TABLE

CRITICAL

K45K43H43

F48H45

BG7BE7

W14U14P13

N50

N42

M14M13L47L45L42

K48

K24

H48

BG26BG22

BF23BE26BE24BE22BD26BD25BD22BD21

BB21BB19BA22BA19

AY22AY21AV19

AU21AU19

AT49

AT21

AM15AM14

AH2AG13

D61

D3D1

C61C59C4

BG61BG59BG58BG4BG3BG1

BE61BE59

BE3BE1BD61

BD1

A61A59A58A4

H51A55H49C55C53A51D53B54

L53D52F51L51G53F53K53K49

C51B50

CPU_DC_TEST_C4_BE3_BG3 TP_CPU_DC_TEST_BG4 TP_CPU_DC_TEST_BG58 CPU_DC_TEST_BG59_BG61 CPU_DC_TEST_BE59_BE61 TP_CPU_DC_TEST_BD61 TP_CPU_DC_TEST_D61 CPU_DC_TEST_C61_A61 TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3 TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_A4

TP_EDP_AUX_N TP_EDP_AUX_P

PPCPU_MEM_VREFDQ_A

VOLTAGE=0.75V MIN_NECK_WIDTH=0.2 MM

PPCPU_MEM_VREFDQ_B

051-9058 6.0.0

Trang 10

IN

OUT

ININ

OUT

OUTBI

BI

NC

OUT

SM_RCOMP_2SM_RCOMP_1SM_RCOMP_0SM_DRAMRST*

BCLK_ITPBCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLKBCLK*

BCLK

RESET*

SM_DRAMPWROKUNCOREPWRGOODPM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMSTRST*

TDITDODBR*

INOUT

ININ

INOUTIN

ININ

IN

OUTBIBIBI

(IPU)(IPU)

(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)

(IPU)(IPU)

(IPU)

(IPU)(IPU)

MF-LF 402 1/16W 1%

1

R1113

MF-LF 402

B46

J58L55D45

L59M60L56

BG43BE43BF44AT30

BE45D44

C45

F49C57

N55N53

C48A48

AG1AG3

K58C49

J61J59H60G59G55E59E55G58

N58N59

H2J3

U1000

BGA

2C-35W IVY-BRIDGE

OMIT_TABLE

CRITICAL

8

8 2

MF 1/20W 201

200

1/16W 402 MF-LF 1%

R1121

130

402 1%

MF 1/20W 201

PLT_RESET_LS1V1_L PM_MEM_PWRGD_R CPU_PWRGD PM_SYNC

XDP_CPU_PREQ_L

XDP_CPU_TMS XDP_CPU_TRST_L XDP_CPU_TDI

XDP_DBRESET_L XDP_BPM_L<0>

Trang 11

OUT

OUTOUT

OUT

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUTOUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

SA_MA_14SA_MA_15

SA_MA_12SA_MA_13SA_MA_11

SA_MA_9SA_MA_10SA_MA_8SA_MA_7SA_MA_6SA_MA_5SA_MA_4SA_MA_3SA_MA_2SA_MA_1SA_MA_0SA_DQS_7

SA_DQS_5SA_DQS_6

SA_DQS_3SA_DQS_4SA_DQS_2

SA_DQS_0SA_DQS_1

SA_CS_0*

SA_CKE_1SA_CK_1*

SA_CK_1SA_CKE_0SA_CK_0*

SA_DQ_62SA_DQ_63SA_DQ_61SA_DQ_60SA_DQ_59SA_DQ_58SA_DQ_57SA_DQ_56SA_DQ_55SA_DQ_54SA_DQ_53SA_DQ_52

SA_DQ_50SA_DQ_51SA_DQ_49SA_DQ_48SA_DQ_47SA_DQ_46SA_DQ_45SA_DQ_44

SA_DQ_42SA_DQ_43SA_DQ_41

SA_DQ_39SA_DQ_40SA_DQ_38SA_DQ_37SA_DQ_36

SA_DQ_34SA_DQ_35

SA_DQ_29SA_DQ_30

SA_DQ_11SA_DQ_12

SA_DQ_9SA_DQ_10SA_DQ_8SA_DQ_7SA_DQ_6SA_DQ_5SA_DQ_4SA_DQ_3SA_DQ_2SA_DQ_1SA_DQ_0

(3 OF 9)

SB_MA_15SB_MA_14

SB_MA_12SB_MA_13SB_MA_11SB_MA_10SB_MA_9

SB_MA_7SB_MA_8SB_MA_6SB_MA_5SB_MA_4SB_MA_3SB_MA_2SB_MA_1SB_MA_0SB_DQS_7SB_DQS_6SB_DQS_5SB_DQS_4SB_DQS_3SB_DQS_2SB_DQS_1SB_DQS_0SB_DQS_7*

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1SB_CK_1*

SB_CK_0*

SB_CKE_0SB_CK_0

SB_DQ_37SB_DQ_36

SB_DQ_34SB_DQ_35SB_DQ_33

SB_DQ_31SB_DQ_32SB_DQ_30SB_DQ_29

SB_DQ_26SB_DQ_27SB_DQ_28

SB_DQ_24SB_DQ_25

SB_DQ_21SB_DQ_22SB_DQ_23SB_DQ_20SB_DQ_19SB_DQ_18SB_DQ_17SB_DQ_16SB_DQ_15SB_DQ_14SB_DQ_13SB_DQ_12SB_DQ_11SB_DQ_10

SB_DQ_8SB_DQ_9SB_DQ_7SB_DQ_6

SB_DQ_4SB_DQ_5SB_DQ_3SB_DQ_2SB_DQ_1SB_DQ_0

SB_DQ_39SB_DQ_38SB_DQ_40SB_DQ_41SB_DQ_42SB_DQ_44SB_DQ_43SB_DQ_46SB_DQ_45SB_DQ_47SB_DQ_49SB_DQ_48SB_DQ_51SB_DQ_50SB_DQ_52SB_DQ_54SB_DQ_53SB_DQ_56SB_DQ_55SB_DQ_57SB_DQ_59SB_DQ_58SB_DQ_61SB_DQ_60SB_DQ_62SB_BS_0SB_DQ_63SB_BS_2SB_BS_1SB_RAS*

BA41AY40

AV32AY32AT32BB32AU34AT34BD35BE35

AU26AY28AW41BC30BA30BE37

BB34BG35

AK56AG55AN52AN55

AL8

AG53AG56AN53AN57AP52AP56AT54AV54AP53AP50

AJ8

AV56BA55BB55BA53AU49BB49AY53BB51AV49BA49

AJ10

AY48AT48AR45BC45BC48AW48AR43BA45BB17BB14

AL6

AU14BA14AR19AY17AR14AV14AY13BB9BA9BA7

AP11

BB11BA13BB7BC7AU13AT13AP8AR6AV9AU6

AJ6AG6

BC41BB40BB26

AY26AU40AT40

AV36AU36

BE39BA28BF36BD37

BG47AT43

BE28BE30BD29BG30AV30BD30AU30BD33

AU22AT26BD46AV28AT28BD43

BE33BF32

AH60AF61AL59AM60

AN4

AG59AG58AL58AK58AR58AN58AU61AU59AN59AN61

AK3

AU58AW58AW59BA58BG54BE54AY60BC59BE57BF56

AK4

BE53BD54BE49BD49BF52BD53BF48BD50BF19BG18

AR4

BG14BE14BE21BE18BE17BF16BE13BD14BD10BF8

AN3

BF12BD13BD9BE9BA3AY2AR3AU3BA4AV4

AL1AL4

BE47BE41BF27

AR22BB36BA36

AY34BA34

AV43AT22BD42BG39

12 OF 109

Trang 12

OUTOUT

OUT

OUTIN

BI

OUT

VCCIO_29VCCIO_28VCCIO_27VCCIO_26VCCIO_25VCCIO_24VCCIO_23VCCIO_22VCCIO_21VCCIO_20VCCIO_19VCCIO_18VCCIO_17VCCIO_16VCCIO_15VCCIO_14VCCIO_13VCCIO_12VCCIO_11VCCIO_10VCCIO_9VCCIO_8VCCIO_7VCCIO_6

VCCIO_49VCCIO_48

VCCIO_5VCCIO_4VCCIO_3

VCCIO_47VCCIO_46VCCIO_45VCCIO_44VCCIO_43

VCCIO_1

VCCIO_42VCCIO_41VCCIO_40VCCIO_39VCCIO_38VCCIO_37VCCIO_36VCCIO_35VCCIO_34VCCIO_33VCCIO_32VCCIO_31VCCIO_30

VCCIO_51VCCIO_50

VCC_76VCC_75VCC_74VCC_73VCC_72VCC_71VCC_70VCC_69VCC_68VCC_67VCC_66VCC_64VCC_63VCC_62VCC_61VCC_60VCC_59VCC_58VCC_57VCC_56VCC_55VCC_54VCC_53VCC_52VCC_51VCC_50VCC_49VCC_48VCC_47VCC_46VCC_45VCC_44VCC_43VCC_42VCC_41VCC_40VCC_39VCC_38VCC_37VCC_36VCC_35VCC_34VCC_33VCC_32VCC_31VCC_30VCC_29VCC_28VCC_27VCC_26VCC_25VCC_24VCC_23VCC_22VCC_21VCC_20VCC_19VCC_18VCC_17VCC_16VCC_15VCC_14VCC_13VCC_12VCC_11VCC_10VCC_9VCC_8VCC_7VCC_6VCC_5VCC_4VCC_3VCC_2VCC_1

VCCIO_SELVCCPQE_1VCCPQE_2VIDALERT*

VIDSCLKVIDSOUTVCC_SENSEVSS_SENSEVCCIO_SENSEVSS_SENSE_VCCIO

VAXG_1VAXG_2VAXG_4VAXG_3VAXG_5VAXG_6VAXG_7VAXG_8VAXG_9VAXG_10VAXG_11VAXG_12VAXG_13VAXG_14VAXG_15VAXG_16VAXG_17VAXG_18VAXG_19VAXG_20VAXG_21VAXG_22VAXG_23VAXG_24VAXG_25VAXG_28

VAXG_26VAXG_27VAXG_30VAXG_29

VAXG_33

VAXG_31VAXG_32VAXG_35VAXG_34VAXG_36VAXG_37VAXG_38VAXG_39VAXG_40VAXG_41VAXG_42VAXG_43VAXG_45VAXG_44VAXG_46VAXG_47VAXG_48VAXG_49VAXG_50VAXG_51VAXG_52VAXG_53VAXG_54VAXG_55VAXG_56VAXG_SENSEVSSAXG_SENSEVCCPLL_1VCCPLL_2VCCPLL_3VCCSA_2VCCSA_1VCCSA_3VCCSA_4VCCSA_5VCCSA_6VCCSA_7VCCSA_8VCCSA_9VCCSA_10VCCSA_11VCCSA_12VCCSA_13VCCSA_15VCCSA_14VCCSA_16

Note VOLTAGE=0VNote VOLTAGE=1.05VNote VOLTAGE=0VNote VOLTAGE=1.25V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side

130

MF-LF 1%

PLACE_NEAR=U1000.C44:2.54mm

2

1R1300

201 1/20W MF 1%

75PLACE_NEAR=R1310.2:2.54mm

21R1310

201 1/20W MF

435%

PLACE_NEAR=U1000.A44:38mm2

1R1311

201 1/20W0 5% MF

21R1312

402100MF-LF 1%

PLACE_NEAR=U1000.F43:50.8mmPLACE_SIDE=BOTTOM

NOSTUFF

1/16W 1%

PLACE_NEAR=U1000.AN16:50.8mm

2

1R1361

402

1001%

1/16W

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.G43:50.8mm

NOSTUFF

2

1R1363

402 1%

1/16W

PLACE_NEAR=U1000.AN17:50.8mmNOSTUFF

PLACE_SIDE=BOTTOM100

2

1R1314

201 1/20W MF

10K

5%

2

1R1313

201 1/20W MF 5%

10K

2

1R1370

402

NOSTUFFPLACE_NEAR=U1000.F45:50.8mm

402

PLACE_NEAR=U1000.BC43:50.8mm

MF-LF1001%

PLACE_SIDE=BOTTOM

2

1R1371

402

1001%

1/16W

PLACE_NEAR=U1000.BA43:50.8mmPLACE_SIDE=BOTTOM

2

1R1331

402 5%

1/16WPLACE_NEAR=U1000.BJ44:2.54mm 1K

2

1R1330

402PLACE_NEAR=U1000.BJ44:2.54mm 5%

1/16W1K

2

1C1330

10%

0.1UF0402 X7R-CERMPLACE_NEAR=U1000.BJ44:2.54mm

2

1R1382

402 1%

MF-LF1001/16W

PLACE_NEAR=U1000.U10:50.8mm

65

AN17G43

C44B43A44AN22AM25

W17W16

AN16BC22

AN48AN45AN42AN20AM47AM43AM21AM17AM16AL48AL45AL26AL22AL20AL16AL15AL14AK51AK50AJ47AJ43AJ25AJ21AJ17

AJ15AJ14

AG51AG50AG48

AG21AG20AG17AG16AG15AF46

AF20AF18AF16AE15AE14AD21AD18AD16AC13AB20AB17AA15AA14

F43

N38N34N30N26L40L36L33L28L25K42K39K37K35K34K32K29K27K26J42J40J38J37J35J34J32J29J28J26J25H40H38H37H35H34H32H29H28H26H25G42F42F38F37F34F32F28F26F25E38E37E34E32E28E26D42D39D37D34D32D27C42C39C37C34C32C27C26A42A39A38A35A34A31A29

BG33BB28BA40AW26AV41AR40AR36AR34AR32AR30AR28AR26AN38AN34AN30AM40AM36AM33AL42AL38AL34AL30AJ40AJ36AJ33AJ28

W20

D49D48

V21V18V17V16U15

U10

R21R18R16P20P17N22N20N16L21L17BC4BC1BB3

AN26AM28

Y61Y48W61W56W55W53W52W51W50V59V58V56V55V53V52V51V50V48V47U46T61T59T58T48

F45

P61P56P55P53P52P51P50P48P47N45AE46AD59AD58AD56AD55AD53AD52AD51AD50AD48AD47AC61AB59AB58AB56AB55AB53AB52AB51AB50AB47AA46

Trang 13

(8 OF 9)VSS

VSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSS

VSSVSS

VSS

VSSVSS

VSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSS

VSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

VSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTFVSS_NCTFVSS_NCTF

(9 OF 9)VSS

BG9BE5

BD8

BD56BD52BD48BD44BD40BD36BD32BD27BD23BD19BD16BD12BC57BC5BC13BB53BA51BA48BA32BA26BA21BA17BA11BA1

AY9

AY58AY55AY49AY45AY41AY4

AY36AY30AY19AY14

AW7

AW61AW43AW13AV55AV48AV40AV34AV22AV21AV17AU7

AU51AU32AU28AU11AU1AT58AT52AT45AT4

AT36AT19AT14

AR7

AR61AR48AR41AR21AR17AR13

AP7

AP55AP51AP10AN54AN50AN47AN43AN40AN36AN33AN28AN25AN21AN1AM58AM48AM45AM42

AM4

AM38AM34

AM30AM26AM22AM20AM13AL61AL47AL43AL40AL36AL33AL28AL25AL21AL17AL13AL10AK52AK1AJ7

AJ48AJ45AJ42AJ38AJ34AJ30AJ26AJ22AJ20AJ16AJ13AH58AH4

AG7

AG61AG52AG47AG18AG14AG10AF59AF58AF56AF55AF53AF52AF51AF50AF48AF47AF21AF17AF1

AE8AE13AD61

AD4AD20AD17

AC6

AC46AC14AC10AB61AB48AB21AB18AB16

AA8

AA56AA55AA53AA52AA51AA50AA13AA1A9

A53A49A45A40A37A33A28A25A21A17A13

W8

W46W21W18W15W13V61V20U8U13T56T55T53T52T51T50T47T1R46R4R20R17

P9

P59P58P21P18P16P14

E61E1D59C58C3BG57BG5BE58BE4BD59BD3BC61A57A5

N61N56N52N51N48N47N43N40N36N33N28N25N21N17N1

M6

M58

M4

M15M11

L61L48L43L38L34L30L26L22L20L16

K8

K51K21K11J55J49J1H58H53H4

H21H17H14H10G61G6G51G48F55F40F35F29F19F15F13E40E35E3E29E25

D6

D58D54D50D46D43D40

D4

D35D29D26D22D18D14D10

C40C35C29BG53BG49BG45BG41BG37BG28BG24BG21BG17

CPU GROUNDS

051-9058 6.0.0

14 OF 109

Trang 14

DESCRIPTION REFERENCE DES BOM OPTION QTY

PLACEMENT_NOTE (C1667-C1679):

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

CPU VCORE DECOUPLING

Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Note:The smallest 10mOhm available in the library are 0805s

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

2 1

R1601

0603 1%

1/4W MF

2.2UF

4022

1C1608

402

2.2UF

X5R4V20%

2.2UF

2

1C1698

10V1UFX5R

2

1C1637

X5R4V40220%

CRITICAL

4022

1C1640

CRITICAL

2.2UF

4024V20%

2

1C160Z

20%

CASE-D2-SM2VPOLY

Place near U1000 on bottom side

2

1C162A

10UF

CERM-X5R 6.3V

6.3V CERM-X5R

1C167G

330UF

20%

TANTCASE-B2-SM12.5V2

1C167D

330UF

TANT20%

1C167J

CASE-B2-SM1TANT20%

2

10%

1UF402

2

1C1684

10%

1UF402Place on bottom side of U1000

3 2

1C1680

Place near inductors on bottom side

D2T-SM1 POLY-TANT 2.0V 20%

3 2

1C1681

D2T-SM1 POLY-TANT 2.0V 20%

6.3V603

2

1UF10V 402

2

10%

1UF402 10V

2.2UFCRITICAL

20%

4V402

2

1C1604

2.2UF

4024V20%

CRITICAL

2

402 10%

2

10%

1UF402

2

10%

4021UF

2

10%

1UF402

2

10%

1UF402

2

402 10%

1UF

2

402 10%

X5R1UF10V

2

10%

1UFX5R 2

10%

X5R1UF402

2

10%

X5R1UF402

2

1C1697

X5R1UF10%

1C1674

CRITICAL

X5R-CERM-120%

6.3V603

2

1C1675NOSTUFF

CRITICAL

6.3V20%

22UF

603X5R-CERM-1

2

1C1663

22UFCRITICAL

20%

6.3V603X5R-CERM-1NOSTUFF

2

402 10V1UF10%

2

1C1695

10%

1UF10V 402

2

10%

X5R1UF402

2

1C161F

0402-1 20%

6.3V CERM-X5R

2 1

R1600

402 5%

Trang 15

DESCRIPTION REFERENCE DES BOM OPTION QTY

0.010

1%

1/4W MF 0603

2

402Place on bottom side of U1000

10V1UFX5R 10%

2

1C1711CRITICAL

6.3V 20%

0402-1

3 2

1C1723

2.0V 20%

470UF-4MOHM

D2T-SM1 POLY-TANT

2

CRITICAL

0402-1 20%

6.3V CERM-X5R

Place close to U1000 on bottom side

2

1C1717OMIT

X5R-CERM-16036.3V

2

10UF

CERM-X5R 6.3V 20%

0402-1

2

0402-1 20%

6.3V CERM-X5R

10UF

3 2

1C1724

POLY-TANT 20%

22UF

2

10V1UF402Place on bottom side of U1000

2

1UFX5R 10%

2

10V 402

1UF10%

X5R 2

X5R1UF10%

22UF

2

1UF402 10V

2

10%

X5R1UF402

2

1UF10%

X5R

2

1C1700CRITICAL

Place on bottom side of U1000

402 10V1UF

2

1C1701CRITICAL

4021UF10VPlace on bottom side of U100

X5R 10%

2

CRITICAL

X5R 10%

1UFPlace on bottom side of U1000

2

CRITICAL

1UF402 10%

X5R 2

CRITICAL

1UF10%

X5R 2

CRITICAL

1UF402 10V

2

CRITICAL

1UF10%

X5R

2

402 10V1UFPlace on bottom side of U1000

2

10V 402 10%

2

Place on bottom side of U1000

402 10V1UFX5R 2

10V 402 10%

X5R 2

402

1UF10%

2

CRITICAL

10V 4021UFX5RPlace on bottom side of U1000

2

1UF10VPlace on bottom side of U1000

10%

X5R 2

1UF402Place on bottom side of U100

Trang 16

ININ

OUTOUT

OUTBI

ININOUTOUT

OUTBI

OUT

SATA3COMPISATA3RCOMPO

SATA0GP/GPIO21SATA1GP/GPIO19SATALED*

SATA3RBIASSATAICOMPO

SATA1RXNSATA0TXPSATA0TXN

SATA2RXNSATA2RXP

HDA_RST*

SPKR

HDA_SDIN0HDA_SDIN1HDA_SDIN3HDA_SDIN2HDA_SDOHDA_DOCK_EN*/GPIO33HDA_DOCK_RST*/GPIO13JTAG_TCK

JTAG_TMSJTAG_TDIJTAG_TDO

SPI_CS0*

SPI_CLKSPI_CS1*

SPI_MOSISPI_MISO

FWH0/LAD0RTCX1

RTCX2

SATA1TXP

SATA0RXNSERIRQLDRQ1*/GPIO23

FWH1/LAD1FWH2/LAD2FWH3/LAD3FWH4/LFRAME*

SATA1RXPSATA1TXN

SATA2TXNSATA2TXPSATA3RXNSATA3RXPSATA3TXNSATA3TXPSATA4RXNSATA4RXPSATA4TXNSATA4TXPSATA5RXNSATA5TXNSATA5TXPSATAICOMPI

PCIECLKRQ3*/GPIO25CLKOUT_PCIE4PCLKOUT_PCIE4N

CLKOUT_PCIE3PCLKOUT_PCIE3N

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73CLKOUT_PCIE1NCLKOUT_PCIE1P

CLKOUT_PCIE0NCLKOUT_PCIE0P

PERN3PETP2PETN2

PERP1PETN1PERN1

SMBCLKSMBALERT*/GPIO11

PETP8

PERP8PETN8

PETP7PERN8PETN7PERP7PERN7

PETN6PETP6PERP6PERN6PETP5PETN5PERP5

PETP4PERN5PETN4PERP4

PETP3PERN4PETN3PERP3

PERN2PERP2PETP1 SMBDATA

CLKOUT_PEG_B_P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE6NCLKOUT_PCIE6P

CLKOUT_PCIE7NCLKOUT_PCIE7PPCIECLKRQ7*/GPIO46CLKOUT_ITPXDP_PCLKOUT_ITPXDP_N

CLKOUTFLEX0/GPIO64CLKOUTFLEX1/GPIO65CLKOUTFLEX2/GPIO66CLKOUTFLEX3/GPIO67

CLKOUT_DMI_NCLKOUT_DMI_P

CLKOUT_DP_PCLKOUT_DP_N

CLKIN_DMI_NCLKIN_DMI_P

CLKIN_GND1_NCLKIN_GND1_P

CLKIN_DOT_96NCLKIN_DOT_96P

CLKIN_SATA_PCLKIN_SATA_N

REFCLK14INCLKIN_PCILOOPBACK

XTAL25_OUTXTAL25_IN

XCLK_RCOMP

CLKOUT_PEG_A_NPEG_A_CLKRQ*/GPIO47CLKOUT_PEG_A_P

SML0ALERT*/GPIO60SML0CLKSML0DATA

SML1CLK/GPIO58SML1ALERT*/PCHHOT*/GPIO74SML1DATA/GPIO75

CL_CLK1CL_DATA1CL_RST1*

OUTOUT

OUTIN

IN

OUT

OUTBI

OUTOUT

ININ

IN

ININOUTOUT

IN

OUTOUT

OUTOUTIN

OUT

OUTOUTOUTOUT

BIBIOUTBIBI

OUTOUT

(IPD-BOOT)

(IPD)(IPD)(IPD)

(IPU)(IPU)

(IPD-PWROK)(IPU/IPD)

(IPD-PWROK)(IPD-PWROK)

(IPU)(IPU)

Unused clock terminations for FCIM Mode

(IPU)

(IPD)

(IPD-BOOT)

VSel strap not functional (VCCVRM = 1.8V)

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

1/20W 2

1

R1803

20KMF 201 5%

1/20W

2

1UFX5R 2

1

C1802

1UFX5R

2

1

R1830

PLACE_NEAR=U1800.Y11:2.54mm37.4

MF 201 1%

V5

P3

Y11 Y10 AB1 AB3 Y1 Y3 AD1 AD3 Y5 Y7 AF1 AF3 AB10 AB8

AB12 AH1 AB13

AH4 AH5 AD5 AD7 AP10 AP11 AM8 AM10

P1

AP5 AP7 AM1 AM3

V14

C20 A20

D20

K36 E36

H7 H1 K5 J3

C17 K22

L34

A36 A34 C34 G34 E34 K34

N32 C36

N34

D36 C37 B37 A38 C38

U1800

PANTHERPOINTMOBILE FCBGAOMIT_TABLE

V49 V47

Y47

M16 E14 C13 G12 C8 A12

C9 H14 E12

K45

AY38 BB40 AV36 BB36 BB34 AU34 AY32 AU32

AW38 AY40 AU36 AY36 AY34 AV34 BB32 AV32

BC38 BJ40 BG38 BH37 BE36 BJ36 BF34 BJ34

BE38 BG40 BJ38 BG37 BF36 BG36 BE34 BG34

E6

M10

K12 T13

L14 L12 A8 V10 M1 J2

K49 H47 F47 K43

AB40 AB42

AB38 AB37

V37 V38

V42 V40

V46 V45

Y45 Y43

Y36 Y37

AA47 AA48

AB47 AB49

Y39 Y40

AK13 AK14

AM13 AM12

AU22 AV22

AK5 AK7

H45

BG30 BJ30

E24 G24

BE18 BF18

P10 T11 M7

U1800

OMIT_TABLEPANTHERPOINTMOBILE FCBGA

R1840

0MF 201 5%

1/20W

NO STUFF

2 1

R1841

1/20W

NO STUFF5%

201 MF0

2 1

R1872

604MF-LF 402 1%

1/16W

2

1R1873

1KMF 201 1%

MF 201 1/20W 1%

2

1

R1831

PLACE_NEAR=U1800.AB12:2.54mm201

1%

1/20W49.9MF

MF 201 5% 1/20W 2 1

R1878

1/20W 5% MF 20110K

2 1

MF 201 5% 1/20W 2 1

MF 201 5% 1/20W

12

MF 201 5% 1/20W 2 1

MF 201 5% 1/20W

2 1

MF 201 5% 1/20W

2 1

MF 201 5% 1/20W

2 1

MF 201 5% 1/20W 2 1

MF 201 5% 1/20W

16 25

16

2 1

MF 201 5% 1/20W 2 1

MF 201 5% 1/20W

2 1

MF 201 1/20WPLACE_NEAR=U1800.K34:1.27mm 5%

2 1

MF 201 5% 1/20WPLACE_NEAR=U1800.A36:1.27mm

2 1

MF 201 5% 1/20WPLACE_NEAR=U1800.N34:1.27mm

2 1

MF 201 5% 1/20WPLACE_NEAR=U1800.L34:1.27mm

MF 201 5% 1/20W 2 1

MF 201 5% 1/20W

6 45 47 81

2 1

MF 201 5% 1/20W

2 1

MF 201 5% 1/20W 2 1

201 5% 1/20W MF 2

1

MF 201 5% 1/20W 2 1

MF 201 5% 1/20W

PCIE_CLK100M_ENET_P

ITPXDP_CLK100M_NPCIE_CLK100M_ENET_N

PCH_CLK96M_DOT_PPCH_CLK96M_DOT_NPCH_CLK100M_SATA_PPCH_CLK100M_SATA_NPCIE_CLK100M_PCH_PPCH_CLK14P3M_REFCLKPCH_CLKIN_GNDP1PCH_CLKIN_GNDN1

SYSCLK_CLK25M_SB_R

JTAG_DPMUXUC_TRST_LTP_PCIE_CLK100M_PE5N

ENET_MEDIA_SENSE_RDIVUSB_EXTD_SEL_XHCIUSB_EXTB_SEL_XHCIPCH_GPIO11

PEGCLKRQA_L_GPIO47PEGCLKRQB_L_GPIO56PCIECLKRQ0_L_GPIO73PEG_CLKREQ_LENET_CLKREQ_LJTAG_DPMUXUC_TRST_LEXCARD_CLKREQ_LAP_CLKREQ_LFW_CLKREQ_LSATARDRVR_ENDP_AUXCH_ISOLPCH_SATALED_LPCH_SPKRJTAG_TBT_TMS

ITPCPU_CLK100M_P

ENET_CLKREQ_LTP_PCIE_CLK100M_PEBP

PCIE_ENET_D2R_NPCIE_ENET_R2D_C_P

PCH_INTVRMEN_L

LPC_FRAME_R_LLPC_AD_R<3>

NC_PCIE_7_R2D_CNNC_PCIE_7_D2RPNC_PCIE_7_D2RN

NC_PCIE_6_R2D_CNNC_PCIE_6_R2D_CPNC_PCIE_6_D2RPNC_PCIE_6_D2RNNC_PCIE_5_R2D_CPNC_PCIE_5_R2D_CNNC_PCIE_5_D2RPNC_PCIE_5_D2RN

TP_PCH_GPIO64_CLKOUTFLEX0TP_PCH_GPIO65_CLKOUTFLEX1TP_PCH_GPIO66_CLKOUTFLEX2TP_PCH_GPIO67_CLKOUTFLEX3

PCH_CLKIN_GNDN1PCH_CLKIN_GNDP1

TP_PCIE_CLK100M_PEGANPEGCLKRQA_L_GPIO47TP_PCIE_CLK100M_PEGAP

TP_CLINK_CLKTP_CLINK_DATATP_CLINK_RESET_L

SMBUS_PCH_CLKSMBUS_PCH_DATAUSB_EXTB_SEL_XHCISML_PCH_0_CLKSML_PCH_0_DATAUSB_EXTD_SEL_XHCI

DMI_CLK100M_CPU_NDMI_CLK100M_CPU_PTP_PCH_CLKOUT_DPNTP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_NPCIE_CLK100M_PCH_P

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_PPCH_CLK14P3M_REFCLKPCH_CLK33M_PCIIN

PCIE_ENET_D2R_P

PCIE_AP_D2R_NPCIE_AP_D2R_PPCIE_AP_R2D_C_NPCIE_AP_R2D_C_PPCIE_FW_D2R_NPCIE_FW_D2R_PPCIE_FW_R2D_C_NPCIE_FW_R2D_C_PPCIE_EXCARD_D2R_NPCIE_EXCARD_D2R_PPCIE_EXCARD_R2D_C_NPCIE_EXCARD_R2D_C_P

PCIE_CLK100M_FW_PPCIE_CLK100M_FW_N

AP_CLKREQ_LPCIE_CLK100M_EXCARD_NPCIE_CLK100M_EXCARD_P

PEG_CLK100M_NPEG_CLK100M_PPEG_CLKREQ_LPCIE_CLK100M_T29_PTBT_CLKREQ_L

LPC_AD<0>

LPC_AD_R<3> LPC_AD<3>

LPC_FRAME_R_L LPC_FRAME_LHDA_BIT_CLK_R

HDA_SYNCHDA_RST_R_L HDA_RST_L

LPC_AD_R<0>

TP_SATA_E_D2RPTP_SATA_D_R2D_CPTP_SATA_D_D2RNTP_SATA_C_R2D_CP

PCH_SATALED_L

TBT_PWR_EN_PCH

SATA_HDD_D2R_NSATA_HDD_D2R_PSATA_HDD_R2D_C_NSATA_HDD_R2D_C_PSATA_ODD_D2R_NSATA_ODD_D2R_PSATA_ODD_R2D_C_N

ITPXDP_CLK100M_P

PCIE_CLK100M_AP_PPCH_SATAICOMP

PCH_XCLK_RCOMP

TP_PCIE_CLK100M_PE4NEXCARD_CLKREQ_L

TP_SATA_F_D2RPTP_SATA_F_R2D_CP

XDP_PCH_TCK

SATA_ODD_R2D_C_P

LPC_SERIRQTP_LPC_DREQ0_LSYSCLK_CLK32K_RTC

HDA_SYNC_R

ITPCPU_CLK100M_N

HDA_SDOUT

051-9058 6.0.0

Trang 17

OUTOUTOUTOUTOUT

FDI_RXP1FDI_RXP2FDI_RXP5FDI_RXP4FDI_RXP7FDI_INTFDI_FSYNC0FDI_LSYNC0FDI_FSYNC1FDI_LSYNC1

DMI2TXNDMI1TXNDMI3TXN

DMI3TXP

FDI_RXN0FDI_RXN1FDI_RXN3FDI_RXN2FDI_RXN4FDI_RXN5DMI0RXN

FDI_RXP6DMI1RXN

DMI0TXP

DMI3RXPDMI2RXPDMI1RXPDMI0RXPDMI3RXNDMI2RXN

DMI2TXP

DMI2RBIASDMI_IRCOMP

SUS_STAT*/GPIO61

SLP_S4*

SLP_S5*/GPIO63SUSCLK/GPIO62

SLP_SUS*

SLP_A*

SLP_S3*

PMSYNCHSLP_LAN*/GPIO29

SYS_RESET*

SYS_PWROKPWROKAPWROKDRAMPWROKRSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30PWRBTN*

ACPRESENT/GPIO31BATLOW*/GPIO72RI*

DSWVRMENDPWROKWAKE*

DDPD_AUXNDDPD_AUXPDDPD_CTRLDATADDPD_CTRLCLKDDPC_3PDDPC_3NDDPC_2PDDPC_2N

DDPC_0PDDPC_1PDDPC_1NDDPC_0NDDPC_HPD

DDPC_AUXNDDPC_AUXPDDPC_CTRLDATADDPC_CTRLCLKDDPB_3PDDPB_3N

DDPB_1PDDPB_2PDDPB_2NDDPB_1NDDPB_0P

DDPB_HPDDDPB_0N

DDPB_AUXNDDPB_AUXP

SDVO_CTRLCLKSDVO_CTRLDATASDVO_INTPSDVO_INTNSDVO_STALLPSDVO_STALLNSDVO_TVCLKINPSDVO_TVCLKINN

L_CTRL_CLK

DAC_IREFCRT_IRTNCRT_VSYNCCRT_HSYNCCRT_DDC_DATACRT_DDC_CLKCRT_REDCRT_GREENCRT_BLUE

L_VDD_EN

L_DDC_DATAL_CTRL_DATALVD_IBGLVD_VREFHLVD_VREFLLVDSA_CLKLVDSA_CLK*

LVDSB_CLKLVDSB_DATA0*

LVDSB_DATA1*

LVDSB_DATA2*

LVDSB_DATA0LVDSB_DATA3*

LVDSB_DATA3

LVDSB_DATA1LVDSB_DATA2

L_DDC_CLKL_BKLTCTLL_BKLTEN

OUT

ININ

IN

INININ

INBIOUTOUTOUTOUTOUT

OUT

IN

OUTOUT

OUT

OUTOUTOUT

OUT

OUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUTOUTOUT

OUTIN

INININININININ

INININININ

INININ

(IPD)(IPD)(IPD)(IPD)(IPD)(IPD)

(IPD-PLTRST#)(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)(IPU)

(IPU)

(IPU)(IPD-DeepS4/S5)

201 MF1KPLACE_NEAR=U1800.T43:2.54mm

K14 G10 C21

BB10 AV14

AW16 BC10 AV12

A18

B13

E22

BJ24 BG25 AU18 AV18 BJ20 BG20

AY18 BB18 BJ18 BG18

BH21

AY20 AW20 BC20 BE20

AY24 AW24 BE24 BC24

AP45 AP43 AM40 AM42 AP40 AP39

M39 P38

AF45

AF43 AF49

AF47 AH47

AH49 AH45

AH43

AF40 AF39

AJ48

AJ47 AK47

AK49 AM47

AM49 AN48

AN47

AK39 AK40

AE47 AE48 AF36 AF37

M45

K47 T40 P39 T45

J47 P45

BH41

M36 M43 AT43 AT45

BG42 BJ42 BE42 BF42 BE44 BF44 BB45 BB43

AT38

P42 P46 AP49 AP47

BB49 BB47 BA48 BA47 AY45 AY43 AY49 AY47

AT40 AT47 AT49

AV49 AV47 AU47 AU48 AV46 AV45 AV40 AV42

T43 M49 T49

T42 M47

P49

M40 T39 N48

U1800

FCBGA MOBILEPANTHERPOINTOMIT_TABLE

2

1

R1915

1/20W 5%

201 MF390K

201 MF0

201 MF100K

201 MF2.37KPLACE_NEAR=U1800.AF37:2.54mm

R1923

1/20W 5% MF 201100K

2 1

R1925

1/20W 5% MF 2011K

2 1

R1991

1/20W 5% MF 2018.2K

2 1

R1985

1/20W 5% MF 2011K

12

R1922

1/20W 5% MF 201100K

12

R1921

1/20W 5% MF100K

201

12

R1924

1/20W 5% MF 201100K

2

1

R1983

1/20W 5%

201 MF10K

75

2 1

R1982

1/20W 5% MF 20110K

17

12

R1984

1/20W 5% 201100K

MF

12

R1981

1/20W 5% MF 201100K

PCH_SUSACK_L

LPC_PWRDWN_L

TP_PM_SLP_A_LPM_SLP_S3_LPM_SLP_S4_L

PCIE_WAKE_L

PM_SLP_S5_LPCH_DMI_COMP

DPA_IG_AUX_CH_NDPA_IG_AUX_CH_P

DPA_IG_DDC_CLKDPA_IG_DDC_DATATP_SDVO_INTPTP_SDVO_INTNTP_SDVO_STALLNTP_SDVO_TVCLKINPTP_SDVO_TVCLKINN

TP_LVDS_IG_CTRL_CLK

PCH_DAC_IREFTP_CRT_IG_VSYNCTP_CRT_IG_HSYNCTP_CRT_IG_DDC_DATATP_CRT_IG_DDC_CLKTP_CRT_IG_REDTP_CRT_IG_GREENTP_CRT_IG_BLUE

LVDS_IG_PANEL_PWR

LVDS_IG_DDC_DATATP_LVDS_IG_CTRL_DATA

LVDS_IG_DDC_CLKLVDS_IG_BKL_PWMLVDS_IG_BKL_ON

LVDS_IG_A_CLK_NLVDS_IG_A_CLK_PLVDS_IG_A_DATA_N<0>

LVDS_IG_B_CLK_PLVDS_IG_B_DATA_N<1>

PM_PCH_PWROKPM_PCH_SYS_PWROK

FDI_LSYNC<0>

PM_DSW_PWRGD

=PP3V3_S5_PCH

=TBT_WAKE_LGPIO29

PM_CLKRUN_L

PM_SLP_S3_LPM_SLP_S4_LPM_SLP_SUS_LPM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LVDS_IG_PANEL_PWRLVDS_IG_BKL_ON

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO

MAKE_BASE=TRUEPCIE_WAKE_L

Trang 18

RSVD8RSVD9RSVD10RSVD12

USBP0NUSBP0PUSBP1NUSBP2NUSBP1PUSBP2PUSBP3NUSBP4NUSBP3PUSBP4PUSBP5NUSBP5PUSBP6PUSBP6NUSBP7NUSBP7PUSBP8PUSBP8NUSBP9NUSBP9PUSBP10PUSBP10NUSBP11NUSBP11PUSBP12PUSBP12NUSBP13NUSBP13P

OC0*/GPIO59

USBRBIAS*

USBRBIAS

OC1*/GPIO40OC2*/GPIO41OC3*/GPIO42OC4*/GPIO43OC5*/GPIO9OC6*/GPIO10OC7*/GPIO14

PIRQA*

PIRQB*

PIRQC*

REQ1*/GPIO50PIRQD*

REQ3*/GPIO54REQ2*/GPIO52

GNT1*/GPIO51GNT2*/GPIO53GNT3*/GPIO55PIRQE*/GPIO2PIRQF*/GPIO3PIRQG*/GPIO4PME*

PIRQH*/GPIO5PLTRST*

CLKOUT_PCI0CLKOUT_PCI2CLKOUT_PCI1CLKOUT_PCI4CLKOUT_PCI3

RSVD1TP1

RSVD3TP3

RSVD5TP5

TP6

RSVD6RSVD7TP7

TP8TP9TP10

RSVD11TP11

RSVD13TP14

RSVD14RSVD15TP15

TP16

RSVD16RSVD17TP17

TP18

RSVD18RSVD19TP19

TP20

RSVD20RSVD21RSVD22RSVD23RSVD24RSVD25RSVD27RSVD26RSVD28RSVD29

TP13TP12

TP23TP22TP21

USB3RN4USB3RN3USB3RN2

USB3TN2USB3TN1USB3TN3USB3TN4USB3TP1USB3TP2USB3TP3USB3TP4TP24

NCNCNC

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NC

NCNCNC

NCNCNCNCNC

BIBI

BIBIBIBIBIBI

BIBI

OUTOUTININ

OUTOUT

OUT

IN

OUTOUT

INININ

ININININ

INOUTINBI

IN

BI

BIBI

OUT

OUTOUT

(IPU-PCIERST#)

Unused RSVD: BT (HS)

Redundant to pull-up on audio page

C33 B33

E30 G30 K30 L30 M28 N28 B29 C29 A28 C28 D28 E28 H28 K28 A26 C26 B25 C25

A32 C32 E32 G32 K32 L32 A30 C30

A24 C24

AW30 AV28 AY26 AU26 AY30 AU28 BB26 AV26 BG32 BF32 BE30 BC28 BJ32 BE32 BC30 BE28

AK45 AK43 AH37 AH38 BG16 BJ16 BH25

BG46 AY16 M20 B21 AB45 BJ26

AB46 L24 K24 Y13 AM5 AM4 AH12 H3 N30 C18 BG26

AT3 AT4 AU2 BC8 AT10 BG4 AU3

BF3 AT12 BA2 AY5 AT8 AV10 AV5 BF6 BD4 BE8 AV7

BB7 BB3 BB5 BA3 BB1 AV1 AV3 AT5 AY3 AT1 AY7

E40 C44 C46

K10 C6

D44 C42 G40 G42

G38 H38 K38 K40

C14 D14 A16 L16 C16 B17 K20 A14

F46 E42 D47

H40 K42 J48 H43 H49

U1800

R2067

5% 1/20W MF 20110K

2 1

R2068

MF 201 5% 1/20W10K

2 1

R2061

MF 5% 1/20W 20110K

2 1

R2062

201 5% 1/20W MF10K

2 1

R2033

1/20W 5% MF 20110K NO STUFF

2 1

MF 201 5% 1/20W

2 1

R2030

1/20W 5% MF 20110K

2 1

R2018

1/20W 5% MF 20110K

2 1

R2016

1/20W 5% 20110K

MF 2

1

R2017

1/20W 5% MF10K

201

2 1

R2014

1/20W 5% MF 20110K NO STUFF

2 1

R2031

1/20W MF 20110K

R2010

1/20W 5% MF 20110K

2 1

R2011

1/20W 5% MF 20110K

2 1

R2012

1/20W 5% MF 20110K

2 1

R2013

1/20W 5% MF 20110K

12

R2054

1/20W 5% 20110K

NO STUFF

MF

2 1

MF 201 5% 1/20W

USB_EXTB_XHCI_NUSB_EXTA_P

JTAG_GMUX_TMSBLC_I2C_MUX_SELUSE_HDD_OOB_LBLC_GPIOTBT_PWR_REQ_L

TP_PCH_STRP_ESI_L

PLT_RESET_L

USB_EXTA_NUSB_EXTB_XHCI_P

TP_USB_4NTP_USB_4PTP_USB_SDNTP_USB_SDPTP_USB_WLANPTP_USB_WLANNUSB_HUB_UP_NUSB_HUB_UP_PUSB_CAMERA_PUSB_CAMERA_NUSB_EXTB_EHCI_NUSB_EXTB_EHCI_PUSB_EXTD_EHCI_NTP_USB_BT_HSNTP_USB_12PTP_USB_12NTP_USB_13NTP_PCH_STRP_BBS1

TP_PCH_TP23

USB3_EXTB_RX_NUSB3_EXTC_RX_NUSB3_EXTD_RX_N

USB3_EXTB_TX_NUSB3_EXTC_TX_N

USB3_EXTD_TX_PUSB3_EXTC_TX_P

JTAG_GMUX_TMSBLC_I2C_MUX_SELUSE_HDD_OOB_L

PCI_INTA_LPCI_INTB_LPCI_INTC_LPCI_INTD_L

=PP3V3_S0_PCH_GPIO

USB3_EXTA_RX_N

USB3_EXTC_RX_PUSB3_EXTB_RX_P

USB3_EXTD_TX_NUSB3_EXTA_TX_P

USB_EXTC_N

USB3_EXTA_TX_N

LPC_CLK33M_LPCPLUS_RPCH_CLK33M_PCIOUT

PCH_STRP_TOPBLK_SWP_L

AUD_IP_PERIPHERAL_DETTBT_PWR_REQ_LAUD_I2C_INT_L

TP_USB_BT_HSP

PCH_USB_RBIASTP_USB_13P

TP_PCI_CLK33M_OUT2

TP_PCI_PME_L XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA3_PCH_GPIO42_USB_EXTD_OC_LXDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_LXDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_LXDP_DB2_PCH_GPIO10_AP_PWR_ENTP_PCI_CLK33M_OUT3

LPC_CLK33M_SMC_RUSB3_EXTD_RX_P

AUD_IP_PERIPHERAL_DET

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA1_PCH_GPIO40_USB_EXTB_OC_LXDP_DA0_PCH_GPIO59_USB_EXTA_OC_LXDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGEAUD_I2C_INT_L

Trang 19

OUTBIIN

BI

ININ

OUTOUTIN

OUT

SATA2GP/GPIO36SATA3GP/GPIO37

VSS_NCTF_30VSS_NCTF_31VSS_NCTF_29

VSS_NCTF_27VSS_NCTF_28

VSS_NCTF_15VSS_NCTF_16VSS_NCTF_14NC_1TS_VSS4TS_VSS3

TS_VSS1TS_VSS2DF_TVSINIT3_3V*

THRMTRIP*

PROCPWRGDRCIN*

PECIA20GATE

TACH7/GPIO71TACH6/GPIO70TACH5/GPIO69TACH4/GPIO68

VSS_NCTF_0VSS_NCTF_1SATA5GP/GPIO49/TEMP_ALERT*

SLOAD/GPIO38

GPIO27GPIO24

GPIO57SDATAOUT1/GPIO48

BMBUSY*/GPIO0TACH1/GPIO1

LAN_PHY_PWR_CTRL/GPIO12GPIO15

SATA4GP/GPIO16TACH2/GPIO6

SDATAOUT0/GPIO39GPIO35

SCLOCK/GPIO22TACH0/GPIO17

GPIO8TACH3/GPIO7

GPIO28STP_PCI*/GPIO34

GPIO CPU/MISC

(6 OF 10)

OUTOUT

OUT

BIIN

TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM

(IPD-PLTRST#)

(IPU)(IPD-PLTRST#?)

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPD)

Set to Vcc when HighSet to Vss when LowDF_TVS:DMI & FDI Term Voltage(IPU-RSMRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

201 MF1K

201 MF10KRAMCFG3:H

2

1

R2173

1/20W 5%

201 MF10KRAMCFG2:H

2

1

R2174

RAMCFG1:H1/20W 5%

201 MF10K2

1

R2175

1/20W 5%

201 MF10KRAMCFG0:H

F49 F1 E49 A45

E1 D49 D1 C48 C2 BJ6 BJ5 BJ46 BJ45 BJ44 A44

BJ4 BH47 BH3 BG48 BG2

BF49 BF1 BE49 BE1 BD49 A4

AK10 AH10 AK11 AH8 AY10

A40 C41 B41 C40

E38 H36 A42

D40

K1

N2 V13 M3 T5

V3

U2

M5 V8

P5 AY11 AU16

P37

C4

T14 C10

D6

K4 P8 E16 E8 G2

2 1

R2178

1/20W 5%

201 MF1K2

1

R2179

1/20W 5%

201 MF2.2K

12

R2111

1/20W 5% MF 20120K

12

R2195

1/20W 5% MF 201100K

2 1

R2191

1/20W 5% MF 20110K

2 1

R2192

1/20W 5% MF 20110K

2 1

R2193

1/20W 5% MF 201100K

2 1

R2194

1/20W 5% MF 20110K

2 1

R2184

1/20W 5% MF 20110K

2 1

R2197

1/20W 5% MF 20110K

NO STUFF2 1

R2190

1/20W 5% MF 201100K

2 1

R2196

1/20W 5% MF 20110K

2 1

R2185

1/20W 5% MF 20110K

2 1

R2160

1/20W 5% MF 20110K

2 1

R2186

1/20W 5% MF 20110K

12

R2112

1/20W 5% MF 20110K

23

2 1

R2180

1/20W 5%

201 MF0

35

19

12

R2198

1/20W 5% MF 20110K

12

R2113

1/20W 5% MF 20110K

2 1

R2199

1/20W 5% MF 20110K

12

R2116

1/20W 5% MF 20110K

2 1

R2150

1/20W 5% MF 20110K

2 1

R2155

1/20W 5% MF 20110K

2 1

R2170

1/20W 5%

201 MF43

NO STUFF

2 1

R2140

1/20W 5%

201 MF0

2 1

R2156

1/20W 5%

201 MF390

10 46 78

23

19

SYNC_DATE=06/13/2011SYNC_MASTER=J31_MLB

PCH GPIO/MISC/NCTF

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H RAMCFG_SLOT

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCHLPCPLUS_GPIO

ODD_PWR_EN_L

=PP3V3_S5_PCH_GPIO

TBT_SW_RESET_R_LPCH_A20GATE

SMC_SCI_L

JTAG_ISP_TCK

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCKXDP_DC1_PCH_GPIO35_MXM_GOOD

SPIROM_USE_MLB

JTAG_ISP_TDOJTAG_ISP_TDITBT_SW_RESET_R_L

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L PCH_A20GATE

PCH_RCIN_L

PM_THRMTRIP_L_R

PCH_DF_TVSPCH_INIT3V3_L

CPU_PWRGDPM_THRMTRIP_L

PCH_RCIN_LWOL_ENSPIROM_USE_MLBDPMUX_UC_IRQODD_PWR_EN_LXDP_DD0_PCH_GPIO36_DP_GPU_TBT_SELENET_LOW_PWR_PCH

=PP3V3_T29_PCH_GPIO

DPMUX_UC_IRQXDP_FC1_PCH_GPIO0

=PP3V3_SUS_PCH_GPIO

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S0_PCH_GPIO

MLB_RAMCFG2MLB_RAMCFG1

CPU_PECI

PCH_PROCPWRGDPCH_PECI

JTAG_ISP_TDO

WOL_ENTP_PCH_GPIO8FW_PME_L

PCH_GPIO24FW_PWR_EN_PCH

=PP3V3_S0_PCH_GPIO

TBT_SW_RESET_L

051-9058 6.0.0

Trang 20

NC

NCNC

NC

VCCTX_LVDSVCCTX_LVDSVCCTX_LVDSVCCTX_LVDS

VSSALVDSVCCALVDS

VCC3_3_7_HVCMOSVCC3_3_6_HVCMOS

VCCCOREVCCCORE

VSSADACVCCADAC

VCCDMI_2_FDIVCCIO_27_PLLFDIVCCAFDIPLLVCCVRM_2_FDI

VCCIO_26_DPVCC3_3_3_PCIE

VCCIO_24_PCIEVCCIO_25_DP

VCCIO_21_PCIEVCCIO_22_PCIEVCCIO_23_PCIE

VCCIO_19_PCIEVCCIO_20_PCIEVCCIO_18_PCIEVCCIO_17_PCIEVCCIO_16_FDIVCCIO_15_FDIVCCAPLLEXPVCCIO_28_PLLPCIE

VCCSPIVCCDFTERMVCCDFTERMVCCDFTERMVCCDFTERM

VCCCORE

VCCCOREVCCCORE

VCCCOREVCCCOREVCCCOREVCCCOREVCCCOREVCCCOREVCCCORE

VCCCOREVCCCOREVCCCOREVCCCOREVCCCORE

VCCVRM_3_DMIVCCDMI_1_DMIVCCCLKDMI

DCPSUSBYPVCCACLK

DCPRTC

VCCADPLLAVCCADPLLB

DCPSSTDCPSUS_2_CLKDCPSUS_1_CLK

VCCDIFFCLKNVCCDIFFCLKNVCCDIFFCLKN

VCCDSW3_3

VCCIO_7_CLK

VCC3_3_5_CLK

VCCASW_2_CLKVCCASW_3_CLKVCCASW_4_CLKVCCASW_5_CLKVCCASW_6_CLKVCCAPLLDMI2

VCCASW_18_CLK

VCCASW_8_CLKVCCASW_9_CLKVCCASW_10_CLKVCCASW_11_CLKVCCASW_12_CLKVCCASW_13_CLKVCCASW_14_CLKVCCASW_15_CLKVCCASW_16_CLKVCCASW_17_CLKVCCASW_7_CLK

VCCVRM_4_CLK

VCCASW_20_CLKVCCASW_19_CLK

VCCSSC

VCCASW_1_CLKDCPSUS_3_CLKVCCIO_14_PLLCLK

VCCIO_30_USBVCCIO_29_USBVCCIO_31_USBVCCIO_32_USBVCCIO_33_USBVCCSUS3_3_7_USBVCCSUS3_3_8_USBVCCSUS3_3_6_USBVCCSUS3_3_10_USBVCCSUS3_3_9_USB

DCPSUS_4_USBV5REF_SUSVCCSUS3_3_1_USB

VCC3_3_2_SATAVCCIO_5_PLLSATAVCCIO_13_SATA3VCCIO_12_SATA3

VCCAPLLSATAVCCIO_6_PLLSATA3

VCCIO_2_SATAVCCVRM_1_SATAVCCIO_4_SATAVCCIO_3_SATA

VCCASW_22_MISCVCCASW_23_MISCVCCASW_21_MISC

V5REFVCCSUS3_3_2_GPIOVCCSUS3_3_4_GPIOVCCSUS3_3_3_GPIOVCCSUS3_3_5_GPIOVCC3_3_1_GPIOVCC3_3_8_GPIOVCC3_3_4_GPIO

PCH output, for decoupling only

10 mA Max, 1mA Idle

NC-ed per DG AL24 left as NC per DG

55mA Max, 5mA Idle

NC-ed per DG

VCCACLK pin left as NC per DG

VCCAPLLDMI2 pin left as NC per DG

1.44 A Max, 474mA Idle

VCCAFDIPLL pin left as NC per DG VCCAPLLSATA pin left as NC per DG

2

PLACE_NEAR=U1800.A22:2.54mm

0.1UFCERM 402 20%

AK37 U47

AT16

AP16

AP37 AP36 AM38 AM37

V1

AN19

AP17

AN34 AN33 AT24 AP26 AP24 AP23 AP21 AN27 AN26 AN21 AN17 AN16

AU20

AT20

AJ17 AJ16 AG17 AG16

AG24 AG23 AG21 AF23 AF21 AD23 AD21 AC23

AJ31 AJ29 AJ27 AJ26 AJ23 AG29 AG27 AG26 AA23

AB36 BJ22

AK36

BG6

U48

V34 V33

BH29

U1800

Y49

AF11

P32

V23 T24 T23

P24

P22 P20 N22 N20

AD17

T26

T29 T27 P28 P26

AC17 N26

AC16

AL29

AH14 AH13 T16

AG34 AF34 AF33

AC27 AC26 AA31 AA29 AA27 AA26 AA24

V21 T21 T19 W33

AA21

W31 W29 W26 W24 W23 W21 AD31 AD29 AC31 AC29 AA19

AK1 BH23

BF47 BD47

AD49

W16 T38

T34 AJ2 AA16

V19 T17 V16 N16

U1800

PCH POWER

PPVOUT_G3_PCH_DCPRTCVOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSSTVOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 mm

PP1V8_S0_PCH_VCCTX_LVDS_F

=PP3V3_S0_PCH_VCCA_LVDS

=PP3V3_S0_PCH_VCC3_3_HVCMOSPP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PPVRTC_G3_PCH

TP_PPVOUT_PCH_DCPSUSBYP

PP1V05_S0_PCH_VCCADPLLA_FPP1V05_S0_PCH_VCCADPLLB_F

Trang 21

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSS(9 OF 10)

VSS

VSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

VSSVSSVSS

VSSVSS

VSSVSSVSSVSSVSS

VSSVSS

VSS

VSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

(10 OF 10)VSS

AM36 AM14 AM11 AL48 AL34 AL33 AL31 AL27 AL26 AL23 AB4 AL21

AL2 AL19 AL17 AL16 AK8 AK46 AK42 AK4 AK38

AB39

AK3 AK12 AJ34 AJ33 AJ24 AJ21 AJ19 AH7 AH46 AH42 AB14

AH40 AH39 AH36 AH3 AH11 AG48 AG31 AG2 AG19 AF8 AB11

AF7 AF5 AF46 AF42 AF4 AF38 AF31 AF29 AF27 AF26 AA34

AF24 AF19 AF16 AD16 AD14 AF12 AF10 AE3 AE2 AD8 AA33

AD46 AD45 AD43 AD42 AD40 AD4 AD39 AD38 AD37 AD36 AA3

AD34 AD33 AD27 AD26 AD24 AD19 AD13 AD12 AD11 AD10 AA2

AC48 AC34 AC33 AC24

AY28 AY22 AY12 AV11

AW48 AW40 AW36 AW34 AW32 AC21

AW28 AW26 AW22 AW2 AW18 AW14 AV8 AV43 AV4 AV38 AC2

AV30 AV24 AV20 AV16 AU30 AU24 AT7 AT46 AT42 AT39 AC19

AT34 AT32 AT30 AT28 AT26 AT22 AT18 AT13 AT11 AR48 AB7

AR2 AP8 AP46 AP42 AP4 AP38 AP32 AP30 AP28 AP19 AB5

AP12 AN31 AN3 AN29 AN2 AM7 AM46 AM45 AM43 AM39 AB43

AA17

BJ28 BG28 BC16 BE16 AP1 AP3 M14 AP13 C22 BG24 BG22 T36 H16 G14 BG41 BE10 B43 AD47 AJ3 N24 BG29

Y8 Y46 Y42 Y4 Y38 Y12 W48 W27 W2 W19 W17 V7 V43 V39 V36 V31 V29 V27 V26 V17 V11 T8 T47 T46 W34 T4 T37 T31 T12 R48 R2 P7 P47 P43 P40 T33 P18 P11 N47 P30 N18 M8 M46 M42 M4 M38 M34 M32 M30 M24 M22 M18 P16 M12 L48 L36 L28 L26 L20 L2 L18 K7 K46 K39 K26 K18 H46

F3 H34 H32 H30 H26 H24 H22 H18 H12 G48 G36 G28 G26 G20 G18 E26 E18 D8 D42 D38 D34 D32 D30 D26 D24 D22 D18 D16 D12 D3 BH7 BH43 BH39 BH35 BH33 BH31 BH27 H10 BH19 BH17 BH15 BH11 BG8 BG44 BG33 BG21 BG17 BF8 BF40 BF38 BF30 BD3 BF28 BF26 BF24 BF22 BF20 BF16 BF12 BF10 BE40 BE26 BE22 BD5 BD46 BC48 BC42 BC40 BC36 BC34 BC32 BC26 BC22 BC2 BC18 BC14 BB46 BB4 BB38 BB30 BB28 BB24 BB22 BB20 BB16 BB12 F45 B7 B39 B35 B31 B27 B23 B19 B15 B11 AY8 AY46 AY42

PCH GROUNDS

051-9058 6.0.0

23 OF 109

Trang 22

NCNC

(PCH Reference for 5V Tolerance on USB)

PCH VCC3_3 BYPASS (PCH PCI 3.3V PWR)

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCADPLLA Filter(PCH DPLLA PWR)

(PCH DPLLB PWR)PCH VCCADPLLB Filter

69 mA

68 mA

PCH VCCCORE BYPASS (PCH 1.05V CORE PWR)

(PCH USB 1.05V PWR) PCH VCCIO BYPASS

0.1UF

CERM40220%

2

1C2441

10VPLACE_NEAR=U1800.P32:2.54mm 0.1UF

CERM40220%

2

1C2421

PLACE_NEAR=U1800.BH29:2.54mm

X7R-CERM0402

2

1C2484

PLACE_NEAR=U1800.P24:2.54mm

X7R-CERM0402

2

1

C2401

6.3V603

10UF

PLACE_NEAR=U1800.AN27:2.54mm

X5R20%

2

1

C2499

10VPLACE_NEAR=U1800.T16:2.54mm 0.1UF

CERM40220%

2

1C2486

25VPLACE_NEAR=U1800.T34:2.54mm

2

1C2424

PLACE_NEAR=U1800.V33:2.54mm

X7R-CERM0402

10UF

PLACE_NEAR=U1800.AG26:2.54mm

X5R20%

2

1

C2420

6.3V805

22UF

PLACE_NEAR=U1800.AC27:2.54mm

CERM20%

21

R2415

0

MF-LF5%

1/16W4022

1C2411

PLACE_NEAR=U1800.AB36:2.54mm

6.3V0402-1

10UF

CERM-X5R20%

2

1C2430

PLACE_NEAR=U1800.BJ8:2.54mm

X7R-CERM0402

22UF

PLACE_NEAR=U1800.AC27:2.54mm

CERM20%

22UF

PLACE_NEAR=U1800.AM37:2.54mmCERM

0.01UF

21

L2407

0805

0.1UH

21

0.1UF

10%

21

402

21

10UF

PLACE_NEAR=U1800.U48:2.54mmX5R

10UF

PLACE_NEAR=U1800.T38:2.54mmCERM-X5R

CERM402

21

PCH DECOUPLING

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMVOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MMMAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMMAKE_BASE=TRUEVOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F PP5V_SUS_PCH_V5REFSUS

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.3MMMAKE_BASE=TRUEVOLTAGE=5V

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.3MMVOLTAGE=5V

PP1V05_S0_PCH_VCCCLKDMI_R

051-9058 6.0.0

Trang 23

IN

INININ

IN

OUT

ININ

IN

INOUTOUT

OUT

INOUTIN

OUT

IN

OUTOUT

IN

OUTOUTOUTOUTOUT

ININININ

OUTOUT

IN

OUT

OUTOUT

ININ

NC

ININOUTOUT

OUTOUT

BIIN

ININ

BIINOUT

IN

ININ

NOTE: This is not the standard XDP pinout.

R252x, R253x, R257x and R259x should be placed where signal path

and path to non-XDP signal destination.

XDP SIGNALS

(R2564-R2567)

PCH/XDP Signal Isolation Notes:

- ’Output’ non-XDP signals require pulls.

OBSDATA_D1 OBSDATA_D2 OBSDATA_D3

VCC_OBS_CD DBR#/HOOK7

OBSDATA_D0

ITPCLK/HOOK4 ITPCLK#/HOOK5

support chipset debug.

RESET#/HOOK6

OBSFN_B0 OBSDATA_A2

VCC_OBS_AB HOOK2 PWRGD/HOOK0 OBSDATA_B2 OBSFN_B1

998-2516

VCC_OBS_CD OBSDATA_B3

OBSDATA_B1

OBSDATA_A1 OBSFN_A1

(R2560-R2563)

OBSFN_C0

OBSDATA_C0 OBSFN_C1

OBSFN_B1 OBSDATA_B0

support chipset debug.

TRSTn TDO

OBSDATA_A3 OBSFN_B0

OBSDATA_A1

OBSFN_A1 OBSFN_A0

OBSFN_D0 OBSFN_D1

OBSDATA_C1 OBSDATA_C2 OBSDATA_C3

998-2516

ITPCLK/HOOK4

HOOK3

TCK0 SDA HOOK1

TDI TMS

TDO TRSTn DBR#/HOOK7 ITPCLK#/HOOK5

OBSFN_C1

OBSDATA_C3 OBSDATA_C0

OBSDATA_D2 OBSDATA_D1

1K series R on PCH Support Page

XDP_PRESENT#

TCK0 OBSDATA_A0

OBSDATA_D3

TCK1 SCL

Use with 921-0133 Adapter Flex to

PCH SIGNALS

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_B2

VCC_OBS_AB HOOK2 HOOK3 HOOK1 PWRGD/HOOK0 OBSDATA_B3

XDP_PRESENT#

OBSFN_D0

OBSDATA_D0 OBSDATA_C2

needs to split between route from PCH to J2550

- ’Output’ PCH/XDP signals require pulls.

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

it is functional in that state, else add BOM options

Initially, stuffing both 33 and 0 ohms and validate whether

R2515

1/20W5% MF 201

0 XDP PLACE_NEAR=R1841.1:2.54mm

21

R2516

1/20W5% MF 201

0 XDP PLACE_NEAR=R1840.1:2.54mm

21

R2505

5% MF 201

1K XDP PLACE_NEAR=U1000.G3:2.54mm

1/20W

12

R2550

1/20W5% MF 201

51 XDP PLACE_NEAR=J2550.52:2.54mm

12

R2551

1/20W5% MF 201

51 XDP PLACE_NEAR=U1800.K5:2.54mm

12

R2552

1/20W5% MF 201

51 XDP PLACE_NEAR=U1800.H7:2.54mm

12

R2556

1/20W5% MF 201

51 XDP PLACE_NEAR=U1800.J3:2.54mm

12

R2510

1/20W5% MF 201

51 XDP PLACE_NEAR=J2500.52:2.54mm

12

R2511

1/20W5% MF 201

51 XDP PLACE_NEAR=U1000.K61:2.54mm

12

R2512

1/20W5% MF 201

12

R2513

1/20W5% MF 201

51 XDP PLACE_NEAR=U1000.J58:2.54mm

12

R2514

1/20W5% MF 201

21

R2504

1/20W5% MF 201

330 XDP

21

R2501

201MF

1K XDP

PLACE_NEAR=U1000.B57:2.54mm 5% 1/20W

21

R2502

1/20W5% 201

XDP 0

PLACE_NEAR=U4900.P17:2.54mm MF

21

R2560

1/20W5% MF 201

0 XDP_CPU:BPM

10

21

R2561

1/20W5% MF 201

0 XDP_CPU:BPM

21

R2562

1/20W5% MF 201

0 XDP_CPU:BPM

21

R2563

1/20W5% MF 201

0 XDP_CPU:BPM

21

R2566

5%

0 XDP_CPU:CFG

201MF1/20W21

R2565

5% MF 201

0 XDP_CPU:CFG

1/20W21

R2564

1/20W5% MF 201

0 XDP_CPU:CFG

21

R2567

1/20W5% MF

0 XDP_CPU:CFG

R2525

1/20W5% MF 201

33 XDP

21

R2526

201MF

33 XDP

1/20W5%

21

R2527

1/20W5% MF 201

33 XDP

21

R2530

1/20W5% MF 201

33 XDP

21

R2532

1/20W5% MF 201

33 XDP

21

R2533

1/20W5% MF 201

33 XDP

21

R2534

1/20W5% MF 201

33 XDP

21

R2535

201MF

33 XDP

1/20W5%

21

R2536

1/20W MF 201

33 XDP

5%

21

R2537

5% MF 201

33 XDP

R2584

1/20W5% MF 201

1K XDP

PLACE_NEAR=J2550.39:2.54mm

21

R2585

1/20W5% MF 201

0 XDP

J2500

M-ST-SM

DF40RC-60DP-0.4V

CRITICAL XDP_CONN

J2550

DF40RC-60DP-0.4V

CRITICAL XDP_CONN

M-ST-SM

21

R2521

5% MF

33 XDP

R2597

1/20W5% MF 201

0

21

R2596

1/20W5% MF 201

0

21

R2572 0

MF 2015% 1/20W

21

R2570

1/20W5% MF 201

0

21

R2576

1/20W5% MF 201

0

19 24

21

R2577

1/20W5% MF 201

R2528

1/20W5% MF 201

33 XDP

21

R2529

1/20W5% MF 201

33

XDP

21

R2520

1/20W5% MF 201

33 XDP

21

R2522

1/20W5% MF 201

33 XDP

21

R2523

1/20W5% MF 201

33 XDP

21

R2531

1/20W5% MF 201

R2575

1/20W5% MF 201

0

21

R2573

1/20W5% MF 201

R2591

1/20W5% MF 201

0

21

R2590 0

MF 2015% 1/20W

R2580

1K

2011/20W

MF

21

R2574

1/20W5% MF 201

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DA2_USB_EXTC_OC_L XDP_DA3_USB_EXTD_OC_L

XDP_DA1_USB_EXTB_OC_L XDP_DA0_USB_EXTA_OC_L TP_XDP_PCH_OBSFN_A<1>

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_OBSDATA_B<0>

CPU_CFG<0>

AUD_IPHS_SWITCH_EN_PCH ENET_LOW_PWR_PCH

XDP_FC1

XDP_DD2_AUD_IPHS_SWITCH_EN

TP_XDP_PCH_HOOK5 ALL_SYS_PWRGD

CPU_CFG<9>

CPU_CFG<5>

XDP_CPURST_L

SATARDRVR_EN SDCONN_STATE_CHANGE

ISOLATE_CPU_MEM_L XDP_CPU_CLK100M_N

XDP_DB3_SDCONN_STATE_CHANGE XDP_DB0_USB_EXTB_OC_EHCI_L TP_XDP_PCH_OBSFN_B<1>

CPU_RESET_L ITPXDP_CLK100M_N ITPXDP_CLK100M_P

XDP_PCH_TDO

XDP_PCH_TMS XDP_PCH_TDI

XDP_PCH_TCK XDP_DC2_DP_AUXCH_ISOL

CPU_CFG<7>

CPU_CFG<6>

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_CPU_TRST_L PM_PWRBTN_L

=PP3V3_S0_XDP

XDP_PCH_TMS TP_XDP_PCH_TRST_L XDP_PCH_TDO XDP_DBRESET_L XDPPCH_PLTRST_L TP_XDP_PCH_OBSFN_A<0>

TP_XDPPCH_HOOK2 XDP_PCH_PWRBTN_L XDP_PCH_S5_PWRGD XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_FC1_PCH_GPIO0 XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_CPU_TCK XDP_CPU_PWRGD

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DBRESET_L

XDP_CPU_TDI

=SMBUS_XDP_SCL XDP_CPU_CFG<0>

XDP_CPU_PWRBTN_L

=SMBUS_XDP_SDA XDP_VR_READY

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_FC0

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD1_JTAG_ISP_TCK TP_XDP_PCH_OBSFN_D<1>

=PP3V3_S5_XDP

051-9058 6.0.0

Trang 24

OUT

OUTIN

IN

OUT

ININ

OUTOUT

IN

OUTOUT

OUTIN

OUT

OUTBI

OUT

OUTOUT

OUT

OUTOUTOUTOUT

25MHZ_C25MHZ_B25MHZ_AX1

X2VDD_RTC_OUTTHRMGND32KHZ_A

OUT

D

SG

IN

D

SG

NCNC

OUTOUT08

Y1 Y2 GND B2

VCC

A1 B1 A2

IN

OUTOUT08

Y1 Y2 GND B2

VCC

A1 B1 A2

IN

Y B A

D

SG

NOTE: 30 PPM crystal required

SMC controls strap enable to allow in-field control of strap setting.

Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH ME Disable Strap

IPD = 9-50k

If high, ME is disabled This allows for full re-flashing of SPI ROM.

PCH uses HDA_SDO as a power-up strap If low, ME functions normally.

VBAT and +V3.3A are

SDCONN_STATE_CHANGE ISOLATION

ENET_MEDIA_SENSE ISOLATION CIRCUIT

to reduce VBAT draw

+V3.3A should be first

internally ORed tocreate VDD_RTC_OUT

GPIO Glitch Prevention

10

23

78

21

R2696

1/16W

0 XDP

5%

402

21

23

R2689

1/16W

1K XDP

5%

402

21

5%

4022

23

2

1C2602

10V402-1X5R

0.1UF

16V

21

R2605

1/20WMF

14611

U2600

TQFN

SLG3NB148A CRITICAL

2

1

C2622

0201X5R-CERM

0.1UF

16V

16

45

3

Q2610

SOT563

SSM6N37FEAPE CRITICAL

21

R2610

1/16WMF-LF

100K

5%

201

12

46

251

46

251

45

312

ENET_MEDIA_SENSE_EN ENET_MEDIA_SENSE_EN_L

PM_PCH_APWROK

=PP3V3_S5_PCHPWRGD

SYSCLK_CLK25M_SB SYSCLK_CLK25M_ENET SYSCLK_CLK25M_T29

PM_PCH_PWROK

FW_PWR_EN ENET_LOW_PWR

AUD_IPHS_SWITCH_EN

ENET_LOW_PWR_PCH FW_PWR_EN_PCH

TBT_PWR_EN_PCH AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S0_RSTBUF

CPU_RESET_L

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC LPC_CLK33M_SMC_R

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIIN

PM_PCH_SYS_PWROK SYS_PWROK_R

MAKE_BASE=TRUE

MAKE_BASE=TRUEPLT_RST_BUF_L SYSCLK_CLK25M_X2_R

PCIE_WAKE_L

MAKE_BASE=TRUEENET_WAKE_L

=PP3V3_ENET_PHY

SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X2

XDP_DBRESET_L

051-9058 6.0.0

Trang 25

BIBI

VDD33

SUSP_IND/LOCAL_PWR/NON_REM0SDA/SMBDATA/NON_REM1SCL/SMBCLK/CFG_SEL0HS_IND/CFG_SEL1

XTALIN/CLKINXTALOUT

TESTRESET*

THRM_PAD

USBDP_UP

NCOSC3*

OCS1*

OCS2*

USBDM_UP

RBIASVBUS_DETNC

NCNCUSBDP_DN3/PRT_DIS_P3USBDM_DN3/PRT_DIS_M3USBDP_DN2/PRT_DIS_P2USBDM_DN2/PRT_DIS_M2USBDP_DN1/PRT_DIS_P1USBDM_DN1/PRT_DIS_M1

BIBI

IN

VCC

GNDSELOE*

D+

D-Y+

M+

Y-

M-BIBI

BIBI

TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEMCRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

USB XHCI/EHCI2 PORT MUX FOR EXT B

J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION

SMC DEBUG PORT FOR J5, TP/KB FOR J3X

J3X USE 197S0284 FOR Y2700 TO SAVE COST

NON_REM 1 : NON_REM 0 STRAP PIN CFG

0 : 1 PORT 1 IS NON REMOVABLE CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

PCH PORT 1 (XHCI) PCH PORT 9 (EHCI2)

J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

IPUIPU

0 : 0 ALL PORTS ARE REMOVABLE

BOM TABLE

IPU

TO CONNECTOR

1 : 0 PORT 1&2 ARE NON REMOVABLE

1 : 1 PORT 1&2&3 ARE NON REMOVABLE

J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B

NC FOR J5, SMC DEBUG PORT FOR J3X

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

USB MUX FOR LS/FS INTERNAL DEVICES

TP/KB FOR J5, IR FOR J3XBLUETOOTH FOR J5 & J3X

2

1

R2712

402 5%

10K

MF-LF

2 1R2700

402 5%

1UF

2

1C271310%

1UF

X5R 2

402 5%

18 80

2

1C270110%

402

100

5%

MF-LF 2

50V

CRITICAL

C0G-CERM 0402 5%

18PF

2

1C270950V 5%

18PF

0402 C0G-CERM

CRITICAL

2

1R2707

402 5%

1/16W

10K

2

1R2706

402 5%

1/16W

10K

2

1R2703

402 5%

HUB_NONREM0_1

10K

1/16W 2

1R2702

HUB_NONREM0_0

10K

1/16W 2

1R2704

7 4 2

30

6 3 1

11

28 22 24 26

35

18 16 12

19 17 13 21 20

9 8 25

BYPASS=U27000.5::5MM

4.7UF

6.3V X5R

2

1C270420%

BYPASS=U2700.23::5MM

4.7UF

6.3V X5R

402 5%

0.1UF10V

12

108

54

76

U2760

TQFNCRITICAL

5X3.2X1.4-SM24.000M-60PPM-16PF

2

1R2710

402 5%

1 U2700 CRITICAL 338S0983 USB HUB 2512B USBHUB2512B

CRITICAL U2700

338S0923 USB HUB 2513B

USBHUB2514B

USB HUB 2514B 338S0824 1 U2700 CRITICAL

HUB_NONREM1_0,HUB_NONREM0_0 HUB_ALLREM

HUB_NONREM1_1,HUB_NONREM0_1 HUB_3NONREM

=PP3V3_S3_USB_HUB

USB_HUB_TEST

USB_HUB_NONREM1

USB_HUB_XTAL2_RUSB_HUB_NONREM0

USBHUB_DN2_NUSBHUB_DN2_PUSB_HUB_XTAL2

USB_HUB_XTAL1

MIN_LINE_WIDTH=0.4MMPPUSB_HUB2_VDD1V8MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V VOLTAGE=1.8V MIN_LINE_WIDTH=0.4MMPPUSB_HUB2_VDD1V8PLL

USB_HUB_RBIASUSB_HUB_VBUS_DET

USB_EXTB_MUX_NUSB_EXTB_EHCI_P

USB_EXTB_EHCI_NUSB_EXTB_XHCI_P

USBHUB_DN1_N

USBHUB_DN3_PUSB_HUB_CFG_SEL0

=PP3V3_S3_USB_RESET

USB_HUB_RESET_L

NC_USB_HUB_OCS2NC_USB_HUB_OCS3

=PP3V3_S3_USBMUX

NC_USB_HUB_OCS4

TP_USB_HUB_PRTPWR1NC_USB_HUB_PRTPWR2NC_USB_HUB_PRTPWR3NC_USB_HUB_PRTPWR4TP_USB_HUB_OCS1

USBHUB_DN4_P

=PP3V3_S3_USB_HUB

USBHUB_DN4_PUSBHUB_DN4_NUSBHUB_DN4_N

USB_EXTB_XHCI_N

USB_HUB_UP_PUSB_HUB_UP_N

USB_EXTB_MUX_P

USB_EXTB_SEL_XHCIUSBHUB_DN3_N

051-9058 6.0.0

Trang 26

IN IN

INOUT

OUT

D

SG

D

S G

D

SG

D

S GD

SG

OUTIN

IN

D

SG

D

SG

IN

GD

1 0 1 1 1 1 1 1 1

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

1V5 S0 "PGOOD" for CPU

MEMVTT Clamp

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

75mA max load @ 0.75V

Ensures CKE signals are held low in S3

transition Rails will power-up as if from S3, but MEM_RESET_L will not properly assert Software

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

2 0 0 1 1 1 1 0 1

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

MF-LF100KCPUMEM_S0

MF-LF

CPUMEM_S01K

4 5

3Q2800

6Q2810

6Q2800

6Q2805

MF-LFCPUMEM_S01/16W

8

67

4 5

3Q2850

SSM6N37FEAPE

CPUMEM_S0

SOT563 2

1R2851

402 1/16W 5%

100K

CPUMEM_S0

2

1C2851

6Q2850

MF-LF

10

5%

603 1/10W

CPUMEM_S0

2 1R2817

402 1/16W 5%

402 MF-LF 1%

33.2K

1/16W

2

1R2820

402 MF-LF 5%

10K

1 2

6

Q2820SOT-563

0.1UF

0402 X7R-CERM

CPUMEM_S0

2

1C281710%

X5R 6.3V

=PP1V5_S3_MEMRESETPLT_RESET_L

Trang 27

A5

DQ33

VDDA10/AP

VDD

VSS

SA1VTT

VSS

DQS4*

DQS4VSSDQ35

VSSCK0*

SA0

VSSDQ58DQ59DM7

VSSDQ57DQ56

DQ50DQ51VSS

DQS6*

DQS6VSSDQ49DQ48

DQ43VSS

DM5VSSDQ42

SDASCLVTT

VSSEVENT*

DQ62VSSDQ63

DQS7*

DQS7

DQ60DQ61VSS

VSSDQ55DQ54

DM6VSS

DQ53VSSDQ52

DQ47VSS

DQS5VSSDQ46DQ41

VSSDQ40DQ34VSSDQ32TESTVDD

VDDS1*

A13CAS*

WE*

BA0VDD

VDDCK0A1A3VDD

VDDA8A9A12/BC*

VDDBA2NCVDDCKE0

VSSDQS5*

VSSDQ44DQ45

DQ39DQ38VSS

VSSDM4

VSSDQ37DQ36VREFCA

VDDODT1NC

S0*

ODT0

BA1RAS*

VDD

CK1*

VDD

VDDA0CK1

A2VDDA4VDD

VDDA14A15

CKE1VDD

BIIN

BIBIBIBIBIBIIN

BIIN

BIBIBIINBIBIBIBIBIBIBIBI

DQ16

DM3DQ26DQ27

DQ4

DQ31DQ30DQS3DQS3*

DQ29DQ28DQ23DQ22DM2DQ21DQ20DQ15DQ14RESET*

DM1DQ13DQ12DQ7DQ6DQS0DQS0*

DQ5

DQ24DQ25

DQ19DQ18DQS2DQS2*

DQ17DQ11DQ10DQS1DQS1*

DQ8DQ9

DM0

DQ0DQ1VREFDQ

DQ3DQ2VSSVSS

VSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSKEY

VSS

VSSVSS

VSSVSSVSSVSSVSS

INBIBIBIBIBI

BIBI

BIBIBI

BIBI

ININ

ININININ

ININ

BIBIBIBIINBIBI

IN

BIBI

INBIBI

BIBI

BI

BIBI

BIINBIBIBIBI

BIBI

OUTBIIN

IN

INININININININININININININININ

BIBIBIBIBIBIBI

INBI

BIBIBIBIBIBIBIBI

IN

BIBI

BOM options provided by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

(NONE)

"Factory" (top) slot113

204 203

196 195

190 189

185

184 179

178 173

172

168 167

162 161

156 155

151

150 145

144 139

138

134 133

128 127

126

199

100 99

94 93

88 87

82 81

124 123

118 117

112 111

106 105

76 75

125

200 202 201

197

121

114 110

120 116 122 77

198

186 188

169 171

152 154

135 137

194 192

182 180

193 191

183 181

176 174

166 164

177 175

165 163

160 158

148 146

159 157

149 147

142 140

132 130

143 141

131 129

187

170 153

136

74 73

104 102 103

101

115

79

108 109

85 89

86 90

78 80

2

1C2930

6.3V

402-LF 20%

20 19

14 13

9

72 71

66 65

48

44 43

38 37

32 31

3

2 1

30

62 64

45 47

27 29

10 12

23 21

18 16

6 4

70 68

17

58 56

69 67

59 57

52 50

42 40 15

53 51

41 39

36 34

24 22

35 33

7 5

63

46 28

0.1UF

2

1C2935

402-LF 20%

402 2

1C2940

2.2UF

20%

CERM 402-LF 6.3V

1C2901

6.3V

10UF

X5R 20%

2

CERM 402 10V

0.1UF

2

10V 402 CERM 20%

2

10%

1UFX5R 2

10%

1UFX5R 2

10%

1UFX5R 2

Trang 28

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

CPU CHANNEL B DQS 5 -> DIMM B DQS 5 CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL B DQS 6 -> DIMM B DQS 6 CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

CPU CHANNEL B DQS 1 -> DIMM B DQS 1 CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

CPU CHANNEL B DQS 7 -> DIMM B DQS 7 CPU CHANNEL A DQS 7 -> DIMM A DQS 7

NOTE: Ivybridge does not use DM signals per doc 460452 CR SFF DG Section 2.6.14

DDR3 Byte/Bit Swaps

MEM_A_DQS_P<0>

MAKE_BASE=TRUEMEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQS_P<3>

MEM_B_DQ<31>

MAKE_BASE=TRUEMEM_B_DQ<30>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQS_N<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_DQS_P<0>

MEM_B_DQS_P<1>

MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_B_DQS_N<1>

MEM_B_DQ<0>

MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_B_DQ<1>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<31>

MEM_B_DQ<22>

MAKE_BASE=TRUE

MEM_B_DQ<47>

MEM_A_DQ<47>

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MEM_A_DQ<43>

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQS_P<7>

MEM_A_DQ<40>

MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQS_P<4>

MAKE_BASE=TRUEMEM_A_DQ<37> MAKE_BASE=TRUE

MEM_A_DQ<38>

MEM_A_DQ<33>

MEM_A_DQS_N<5>

MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_A_DQS_P<5>

MEM_A_DQS_N<3>

MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_A_DQS_P<3>

MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_B_DQS_P<4>

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MEM_B_DQ<43>

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MEM_A_DQ<7>

MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<11>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MEM_A_DQ<49>

MAKE_BASE=TRUE

=MEM_A_DQ<62>

Trang 29

BIBIBIOUTBIIN

IN

ININININININ

ININININININININ

BIBIBIBIBIBIBI

INBIBIBIBIBIBIBIBI

IN

BIBI

VDDA12/BC*

VSS

DQ42DQ43DQ48DQ49VSS

VSSDQ41DQS4*

DM5

VDDCKE1A15A14VDDA11A7A6VDDA4A2CK1

A0VDDVDDCK1*

VDDRAS*

BA1

ODT0S0*

NCODT1VDD

VREFCAVDDDQ36DQ37VSS

DM4VSSVSSDQ38DQ39DQ45DQ44VSS

DQS5*

VSS

CKE0VDDNCBA2

CK0

VDDBA0WE*

A13S1*

VDDVDDTESTDQ33DQ32VSS

DQ34DQ40VSS

DQ46VSSDQS5

VSSDQ47DQ52VSSDQ53VSSDM6DQ54DQ55VSSVSSDQ61DQ60

DQS7DQS7*

DQ63

VSSDQ62EVENT*

VSS

VTTSCLSDA

VSS

DQS6DQS6*

VSSDQ51DQ50

A10/APVDDCK0*

DQ35VSSDQS4VSSCAS*

VDD

DM7VSSDQ56

MTG PIN

MTG PINMTG PIN MTG PINMTG PIN MTG PIN

MTG PIN

VSSDQ57

VTTSA1SA0

DQ58VSSDQ59VSSVDDSPD

MTG PINMTG PINS

KEY

BIBIBIBIBIBIIN

BIIN

BI

BIBIINBIBIBIBIBIBIBI

BI

DQ2DQ3

VREFDQDQ1DQ0DM0

DQ9DQ8DQS1*

DQS1DQ10DQ11DQ17DQS2*

DQS2DQ18DQ19DQ25DQ24

DQ5DQS0*

DQS0DQ6DQ7DQ12DQ13DM1RESET*

DQ14DQ15DQ20DQ21DM2DQ22DQ23DQ28DQ29DQS3*

DQS3DQ30DQ31DQ4

DQ27DQ26DM3

DQ16

VSS

VSSVSSVSSVSSVSS

VSSVSS

KEYVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSS

VSS

INBIBIBIBIBI

BI

BIBI

BIBIBIBIBI

INININ

BI

INININININININININININ

BIBIBIBIINBIBI

IN

BIBIIN

BIBIBIBIBIBIBIBIBI

BIIN

BIBIBIBI

Power aliases required by this page:

Signal aliases required by this page:

"Expansion" (bottom) slot

1C3140

20%

CERM 402-LF 6.3V

6.3V

10UF

X5R 20%

2

CERM 402 10V

2

10V CERM

28

2

1C3153

1UF402 10V 2

1C3152

1UF402 10V 2

1C3151

4021UF10V 2

1C3150

4021UF10V

11 79

113

204 203

212 211

210 209

208 207

206 205

196 195

190 189

185

184 179

178 173

172

168 167

162 161

156 155

151

150 145

144 139

138

134 133

128 127

126

199

100 99

94 93

88 87

82 81

124 123

118 117

112 111

106 105

76 75

125

200 202 201

197

121

114 110

120 116 122 77

198

186 188

169 171

152 154

135 137

194 192

182 180

193 191

183 181

176 174

166 164

177 175

165 163

160 158

148 146

159 157

149 147

142 140

132 130

143 141

131 129

187

170 153

136

74 73

104 102 103

101

115

79

108 109

85 89

86 90

78 80

20 19

14 13

9

72 71

66 65

48

44 43

38 37

32 31

3

2 1

30

62 64

45 47

27 29

10 12

23 21

18 16

6 4

70 68

17

58 56

69 67

59 57

52 50

42 40 15

53 51

41 39

36 34

24 22

35 33

7 5

63

46 28

1 C3135

402-LF 20%

MEM_B_ODT<1>

MEM_B_A<3>

=PP1V5_S3_MEM_B

=PP0V75_S0_MEM_VTT_B MEM_B_SA<1>

Trang 30

BIBI

OUTBI

BIBIIN

BIBIBI

OC*

OUT2OUT1OUT0

THRMGNDENIN1IN0

PAD

IN

VDDWRITE_PROTECT_SW

CARD_DETECT_SWCARD_DETECT_GND

DAT6DAT7

DAT1CD/DAT3DAT2DAT4

VSSVSSCLKCMDDAT0

SHLD_PINSHLD_PINSHLD_PINSHLD_PIN

OUTOUT

DET_LVL DET_IN RST_IN*

DET_CH_EN*

DLY

RST LOGIC

(IPU)

(OD) (OD)PAD

CAESAR-IV Card Detect is programmable,but a Silicon bug makes the activehigh case unusable

SD Not Inserted, CARD_DETECT is OPEN

TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF

-> To Isolation Circuit (then to PCH GPIOi) & SMC

deasserts for >80ms, then asserts forOtherwise RST_OUT# follows RST_IN#

10ms regardless ofmove RST_IN# state

to bypass reset logic

SD Detect & Reset Logic

Converts SDCONN from active-low level signal to active-high pulses

R3311 and R3310 mutually exclusive

on DET_CHANGED# logic

to control effect of =ENET_RESET_L

-> From PCH GPI0

-> From SD Conn (Low active)

353S3004

Place near attr for series resistors:

SD Card 3.3V Overcurrent Protection

DLY block is 20ms nominalWhen ENET_LOW_PWR deasserts, RST_OUT#

-> To ENET Chip

516-0225

SD Card Connector

SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit

R3314 and R3312 mutually exclusive

Must STUFF R3312 and NOSTUFF R3314when R3311 is NOT STUFFED

5

3 2

4

U3300

DGNTPS2065-1CRITICAL

2

1C3302

20%

6.3V 60310UFCRITICAL

2

1C3303

10%

X7R-CERM0.1UF

0402 2

1

R3300

402 5%

1/16W47KNOSTUFF

2

1C3300

20%

CRITICAL10UFX5R 6.3V 2

1C3301

10%

X7R-CERM0.1UF0402

2 1

R3302

402 5%

1/16W0

2

1

R3301

402 5%

1/16W10K

24

16

6 3

4

20 19 18 17

13 12 11 10 9 8 7 2 5

1

14 15

J3300

F-RT-THSD-CARD-K19-K24CRITICAL

2 1

R3311

402 5%

1/16W0

24

2 1

R3314

402 5%

1/16W

0

36 82

2 1R3379 33 5% 1/16W MF-LF402

PLACE_NEAR=U3900.21:5MM

2 1

L3300

040247NH-1.3OHMCRITICAL

2

1C3370

402 CERM 50V 5%

15PFNOSTUFF2

1C3371

CERM 50V 5%

22PF0402NOSTUFF

30

2

1C3373

50V 5%

0201 COG-CERM10PFNOSTUFF

30

2

1C3372

50V 5%

2

1C3375

50V 5%

2

1C3374

50V 5%

2

1C3377

50V 5%

2

1C3376

50V 5%

2

1C3379

50V 5%

2

1C3378

50V 5%

2

1C3381

50V 5%

2

1C3380

50V 5%

2 1R3361 33 5% 1/16W MF-LF402

2 1R3371 33 5% 1/16W MF-LF402

2 1R3372 33 5% 1/16W MF-LF402

2 1R3373 33 5% 1/16W MF-LF402

2 1R3374 33 5% 1/16W MF-LF402

2 1R3375 33 5% 1/16W MF-LF402

2 1R3376 33 5% 1/16W MF-LF402

2 1R3377 5% MF-LF402

1/16W33

2 1R3378 33 5% 1/16W MF-LF402

4 3

2

8 1

7

9 6

U3311

TDFNSLG4AP026VCRITICAL

2

1R3310

402 5%

MF-LF10KNOSTUFF

2

1R3316

402 5%

MF-LF10K

2

1R3317

402 5%

1/16W10KMF-LF

2

1R3312

402 5%

0MF-LFNOSTUFF

2

1

R3315

402 5%

MF-LF10K1/16W

SD Card Connector

SYNC_DATE=11/03/2011SYNC_MASTER=YONAS_J30

Trang 31

V+

SCLSDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPAD

NC

INBI

VDD

VOUTDVOUTCVOUTBVOUTASCL

SDAA0A1GND

INBI

QTY

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs

VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs

VREFDQ:LDO - LDO outputs sent to DQ inputs

DDRVREF_DAC - Stuffs Apple margining circuit

Addr=0x30(WR)/0x31(RD)

10mA max load

soft-resets and sleep/wake cycles.

D 6

0.000V - 3.000V (0x00 - 0x74) 1.000V - 2.000V (+/- 500mV) 1.5V (DAC: 0x3A)

+61uA - -61uA (- = sourced)

MEM VREG D 5 C

2 A

+6.0mA - -5.0mA (- = sourced) 1.056V - 1.442V (+/- 180mV) GPU Frame Buffer (1.8V, 70% VRef)

0.000V - 3.300V (0x00 - 0xFF) 1.267V (DAC: 0x8B)

NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.

C 3

MEM B VREF CA

NOTE: Margining will be disabled across all

DDR3L (1.35V) 6.99mV per step DDR3 (1.5V) 7.70mV per step NOTE: CPU DAC output step sizes:

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable both at the same time!

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs

watchdog will disable margining.

Required zero ohm resistors when no VREF margining circuit stuffedRST* on ’platform reset’ so that system

Addr=0x98(WR)/0x99(RD)

MEM A VREF DQ

PCA9557D Pin:

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs

VREFCA:LDO - LDO outputs sent to CA inputs

B MEM B VREF DQ

+3.4mA - -3.4mA (- = sourced) 0.000V - 1.501V (0x00 - 0x74) 0.300V - 1.200V (+/- 450mV) 0.75V (DAC: 0x3A) DAC Channel:

DDRVREF_DAC0.1UF402

2 1

R3414

PLACE_NEAR=R7320.2:1mm

DDRVREF_DAC

1/16W 1%

33.2K402

2

1

R3413

100KMF-LF 5%

1/16WDDRVREF_DAC

402

B4

B1 C4 C1 C2

C3

U3402

UCSPMAX4253

CRITICALDDRVREF_DAC

B4

B1 A4 A1 A2

A3

U3403

UCSPMAX4253DDRVREF_DACCRITICAL

B4

B1 A4 A1 A2

A3

U3402

UCSPMAX4253

CRITICALDDRVREF_DAC

B4

B1 C4 C1 C2

C3

U3403

UCSPCRITICALMAX4253DDRVREF_DAC

B4

B1 A4 A1 A2

A3

U3404

DDRVREF_DACMAX4253UCSPCRITICAL

B4

B1 C4 C1 C2

C3

U3404

MAX4253CRITICALUCSPDDRVREF_DAC

2 1

R3409

1%

1/16WPLACE_NEAR=J2900.126:2.54mmVREFCA:LDO_DAC

200402

2 1

R3411

1/16W2001%

MF-LFPLACE_NEAR=J3100.126:2.54mmVREFCA:LDO_DAC

402

2 1

R3418

OMIT

NONE NONESHORT402

2 1

R3419

SHORTOMIT

NONE NONE 402

24

2 1

R3403

PLACE_NEAR=J2900.1:2.54mm1%

2001/16WVREFDQ:LDO_DAC

402

2 1

R3404

PLACE_NEAR=R3403.2:1mmMF-LF

1%

1/16W133VREFDQ:LDO_DAC

402

2 1

R3405

200 PLACE_NEAR=J3100.1:2.54mmMF-LF

1%

1/16WVREFDQ:LDO_DAC

402

2 1

R3406

1%

1331/16W PLACE_NEAR=R3405.2:1mmVREFDQ:LDO_DAC

MF-LF0DDRVREF_DAC

402 2

1

R3416

0MF-LF 5%

1/16WDDRVREF_DAC

402 2

VREFDQ:M1_M3PLACE_NEAR=Q3420.3:2mm

X7R-CERM 04020.1UF16V

2

VREFDQ:M1_M3PLACE_NEAR=Q3420.6:2mm

X7R-CERM 04020.1UF16V

1KVREFDQ:M1_M3

MF-LF1KPLACE_NEAR=R3441.2:1mm

MF-LF

PLACE_NEAR=Q3420.3:1mm1K

1/16WDDRVREF_DAC

402

2 1

R3410

MF-LF 1% PLACE_NEAR=R3409.2:1mm133

1/16WVREFCA:LDO_DAC

100K1/16WDDRVREF_DAC

402

2 1

15 14 13 12 11 10 9 7 6

5 4 3

U3401

CRITICAL

QFNPCA9557DDRVREF_DAC

2 1

R3412

1/16W 1%

133PLACE_NEAR=R3411.2:1mmVREFCA:LDO_DAC

3 10 9

U3400

DDRVREF_DACCRITICAL

DDRVREF_DAC0.1UF402 2

1

C3400

6.3V 20%

2.2UFCERM 402-LFDDRVREF_DAC

2

1

C3405

10V CERM 20%

DDRVREF_DAC0.1UF402

2

1

C3403

CERM 10V

DDRVREF_DAC0.1UF402

4 R3421,R3422,R3441,R3442 VREFDQ:M1_DAC114S0218 RES,MTL FILM,1K,1%,0402,SM,LF

114S0171 2 RES,MTL FILM,332,1%,0402,SM,LF R3404,R3406 VREFDQ:M1_DAC

SYNC_DATE=06/13/2011

DDR3/FRAMEBUF VREF MARGINING

SYNC_MASTER=J31_MLB

RES,MTL FILM,0,5%,0402,SM,LF116S0004 2 R3403,R3405 VREFDQ:LDO

RES,MTL FILM,0,5%,0402,SM,LF116S0004 2 R3409,R3411 VREFCA:LDO

VREFMRGN_SODIMMS_CAVREFMRGN_SODIMMB_DQ

=PP3V3_S3_VREFMRGN

MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFCA_AMIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

VOLTAGE=0.75V MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFCA_BMIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFDQ_AMIN_NECK_WIDTH=0.2 mm

PP3V3_S3_VREFMRGN_DACVOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75VPP0V75_S3_MEM_VREFDQ_BPP3V3_S3_VREFMRGN_CTRL

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MEMRESET_ISOL_LS5V_L

PPCPU_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

=PPDDR_S3_MEMVREF

PP0V75_S3_MEM_VREFDQ_BPPCPU_MEM_VREFDQ_B

MEMRESET_ISOL_LS5V_L

051-9058 6.0.0

Trang 32

BI

INBI

SYM_VER-1

IN

ININOUT

RESET*

OUTENMR*

GNDTHRMIN

ININ

20-30 MOHM @2.5V 0.727 A (EDP)

TPCP8102 P-TYPE

3V S3 WLAN FET

CHANNEL RDS(ON)

L3507

DLP0NS

90-OHM CRITICAL

2

1R3554

1/16W1%

MF-LF

232K

4022

1R3553

1/16W1%

C3531

0201X5R-CERM

0.1UFPLACE_NEAR=J3501.15:2.54mm

10% 16V2

1

C3530

0201X5R-CERM

10UFPLACE_NEAR=Q3550.6:2.54mm

21

16 81

21

L3501

DLP11S

330-OHM-80MA CRITICAL

R3500

1/16W5% MF-LF

0

40221

R3501

1/16W5% MF-LF

0

40221

R3502

1/16W5% MF-LF

34 33

32 31

303

J3501

F-ST-SM

500913-0302 CRITICAL

16 81

21

R3510

1/20W5% MF201

0

21

R3511

1/20W5% MF201

0

21

201MF

NOSTUFF

21

R3519

1/20W5%

201MF

BTPWR:S4 0

15K

1/20W

NOSTUFF

12

54

76

U3510

TQFN

PI3USB102ZLE CRITICAL

201MF

15K NOSTUFF

2

1R3513

1/20W1%

201MF

15K NOSTUFF

2

1R3512

1/20W1%

201MF

0.1UF

10%

46

21

3

Q3510

VESM

SSM3K15AMFVAPE CRITICAL

BTPWR:S4

X19/ALS/CAMERA CONNECTOR

PM_SLP_S4_L

USB_BT_WAKEN

AP_CLKREQ_Q_L

USB_BT_CONN_P USB_BT_CONN_N

PP3V3_WLAN

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=1 mm

PP3V3_S3RS4_BT_F

MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

=PP3V3_S4_BT

USB_BT_P USB_BT_N

PCIE_WAKE_L

P3V3WLAN_VMON

AP_RESET_L AP_PWR_EN

AP_CLKREQ_L

=PP5V_S3_ALSCAMERA

=I2C_ALS_SCL USB_CAMERA_CONN_P

P3V3WLAN_SS

=PP3V3_S3_WLAN

PCIE_AP_D2R_P PCIE_AP_D2R_N

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

=I2C_ALS_SDA

USB_CAMERA_N USB_CAMERA_P

PM_WLAN_EN_L

WIFI_EVENT_L

=AP_TEMP_SMB_SCL AP_TEMP_SMB_SDA_R

051-9058 6.0.0

Trang 33

OUT

INININ

OUT

OUTOUT

OUT

INOUT

IN

OUT

OUTOUT

INININ

OUT

ININOUT

BI

DPSNK0_ML_LANE_3PDPSNK0_ML_LANE_3NDPSNK0_ML_LANE_2P

DPSRC0_HOT_PLUG_DET

TEST_POINT_2TEST_POINT_3

DPSNK0_HOT_PLUG_DETDPSNK0_AUX_CHNDPSNK0_AUX_CHPDPSNK0_ML_LANE_0NDPSNK0_ML_LANE_0PDPSNK0_ML_LANE_1NDPSNK0_ML_LANE_1PDPSNK0_ML_LANE_2N

TEST_POINT_0TEST_ENTHERM_DPEE_CLKEE_CS*

EE_DOEE_DIPCIE_CLKREQ_3*

PCIE_CLKREQ_2*

PCIE_CLKREQ_1*

PCIE_CLKREQ_0*

DPSNK1_ML_LANE_1PDPSNK1_ML_LANE_2NDPSNK1_ML_LANE_2PDPSNK1_ML_LANE_3NDPSNK1_ML_LANE_3P

DP_RES_1DP_RES_0DP_ATEST

DPSRC0_AUX_CHNDPSRC0_AUX_CHPDPSRC0_ML_LANE_0NDPSRC0_ML_LANE_0PDPSRC0_ML_LANE_1NDPSRC0_ML_LANE_1PDPSRC0_ML_LANE_2NDPSRC0_ML_LANE_2PDPSRC0_ML_LANE_3NDPSRC0_ML_LANE_3P

TMU_CLK_OUTTMU_CLK_IN

XTAL_25_INXTAL_25_OUT

REFCLK_100_IN_PREFCLK_100_IN_N

TDOTCKTMSTDIPCIE_RST_3*

PER_0_NPER_0_P

PET_3_PPET_3_N

PET_2_NPET_2_P

PET_1_PPET_1_N

PET_0_NPET_0_P

TEST_POINT_1

DPSNK1_ML_LANE_0N

PER_1_N

DPSNK1_ML_LANE_0PDPSNK1_ML_LANE_1N

DPSNK1_AUX_CHPDPSNK1_HOT_PLUG_DETDPSNK1_AUX_CHN

PRT0_T29T_NPRT0_T29R_PPRT0_T29R_NT29_0_LSEOT29_0_LSOEPRT1_T29T_PPRT1_T29T_NPRT1_T29R_PPRT1_T29R_NT29_1_LSEOT29_1_LSOET29_SDAT29_SCL

PRT2_T29T_PPRT2_T29T_NPRT2_T29R_PPRT2_T29R_NT29_2_LSEOT29_2_LSOEPRT3_T29T_PPRT3_T29T_NPRT3_T29R_PPRT3_T29R_NT29_3_LSEOT29_3_LSOE

IN

OUTIN

CVCC

THMVSS PAD

S_LW_LHOLD_L

OUT

INININ

ININ

OUTOUT

DEBUG: For monitoring clock DEBUG: For monitoring current/voltage

Use B1 GND ball for THERM_DN

Not used in host mode.

(T29_SPI_CLK) (T29_SPI_CS_L)

1/16W402

1C3686

BYPASS=U3600.Y19::5.08mm

0402X7R-CERM16V

5%

402

48

R16P17F1

U2E2

R4

A2

L6M5N6P5E4

T1

T3R2

F3F5

H1G2

H3G4

H5G6

K5J6

E14

H17E16

A18A16C16C14

A14A12C12C10

A10A8C8C6

A6A4C4C2

F21D21

K21H21

P21M21

V21T21

E6

F19D19

K19H19

P19M19

V19T19

J4K3J2K1

L4M3N4P3

K17M17

A20B21

M1P1N2L2

AA18Y17AA16Y15AA14Y13AA12Y11

V3

W16U16V9

U8V11U10V13U12V15U14

U4

V7U6

AA4Y3AA6Y5AA8Y7AA10Y9

V5

V1W2

AA20Y21Y19

U3600 CRITICAL

FCBGA T29 OMIT_TABLE

402 2

1R3622

10K

1/16W5%

8

83

21

C3621

0201X5R-CERM

21

C3622

0201X5R-CERM

21

C3623

0201X5R-CERM

21

C3624

0201X5R-CERM

21

C3625

0201X5R-CERM

21

C3626

0201X5R-CERM

21

C3627

0201X5R-CERM

21

C3628

0201X5R-CERM

21

C3629

0201X5R-CERM

21

C3630

0201X5R-CERM

21

C3631

0201X5R-CERM

21

C3632

0201X5R-CERM

21

C3633

0201X5R-CERM

21

C3634

0201X5R-CERM

21

C3635

X5R-CERM0201

21

C3636

0201X5R-CERM

21

C3637

0201X5R-CERM

21

C3638

0201X5R-CERM

21

C3639

21

C3641

X5R-CERM0201

21

C3642

X5R-CERM0201

21

C3643

X5R-CERM0201

21

C3644

0201X5R-CERM

21

C3645

0201X5R-CERM

21

C3646

0201X5R-CERM

21

C3647

0201X5R-CERM

21

C3601

X5R-CERM0201

21

C3602

X5R-CERM0201

21

C3603

X5R-CERM0201

21

C3604

X5R-CERM0201

21

C3605

X5R-CERM0201

21

C3606

X5R-CERM0201

21

U3690

M95320-RMC6XGMLP

CRITICAL OMIT_TABLE

35

16 81

2 1

T29_RSVD T29_GPIO<2>

TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET3_L

TP_T29_XTAL25OUT SYSCLK_CLK25M_T29_R

T29_TMU_CLK_IN T29_TMU_CLK_OUT

T29_DP_ATEST T29_DP_RES

DP_T29SRC_HPD DP_T29SNK0_ML_P<2>

PCIE_T29_R2D_C_N<0>

PCIE_T29_R2D_C_N<2>

T29_RBIAS T29_RSENSE

=PP3V3_T29_RTR

T29ROM_HOLD_L

T29_SPI_CS_L

051-9058 6.0.0

Trang 34

VDD3P3DP_PLL

VCC3P3_DP_TXRXBIAS

VSSDPVSSDPVSSDPVSSDPVSSDPVSSDPVSSDPVSSDP

VSSDPVSSDPVSSDP

VSSDPVSSDPVSSDPVSSDP_PLLVSSDP

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPE

VCC1P0VCC1P0

VCC1P0VCC1P0VCC1P0

VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVDD1P0_DP_TXRXVDD1P0_DP_RX1VDD1P0_DP_TXRX

VDD1P0_DP_PLL

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VCC1P0_PEVCC1P0_PE

VCC3P3VCC3P3VCC3P3VCC3P3_T29VCC3P3_T29

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

2

1C3713

1UF

6.3V10%

402CERM 2

1C3714

6.3V10%

402CERM

1UF

2

1C3730

CERM20%

402CERM

1UF

2

1C3721

6.3V10%

402CERM

1UF

2

1C3722

6.3V10%

402CERM

6.3V2

1

C3700

10UF

X5R20%

6.3V 2

1C3746

6036.3V20%

6.3V

B19B17B15B13B11

W20W18U20U18R20R18

B9

N20N18N16L20L18L16J20J18J16G20

B7

G18F17F15F13F11F9

F7E20E18D17

B5

D15D13D11D9D7D5D3D1C20C18

B3B1

T13

W8W6W4V17T17T15T11T9

AA2Y1W14W12W10

T7T5

N8L14L12L10L8J14J12J10

N14N12N10

J8G8

P13R12

R10R8

R14

G12G10

P15

P11P9R6P7

K7M7H7

G14E12E10E8M15K15H15M13M11M9K13K11K9H13H11H9

U3600 FCBGA OMIT_TABLE CRITICAL

402CERM 2

1C3706

CERM40210%

PP3V3_T29_DPBIAS

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm

37 OF 109

34 OF 86

7 33 35

7

Trang 35

GND THRM

IN

VDD

SENSE+

PAD

(OD)

0.7VDLY

SW

SGND GND

NC

SNS1SNS2

VOUTGNDONVIN

Vout = 1.6V * (1 + Ra / Rb)

UVLO = 4.55V (falling), 4.95 (rising) UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO(falling) = 1.22 * (R1 + R2) / R2

Pull-up provided by SB page.

Supervisor & CLKREQ# Isolation

TypePartR(on)Max Current = 2A (85C)

@ 2.5V

18.3 mOhm Typ

U3810

Load SwitchTPS22924C

Platform (PCIe) Reset

SGND shorted to

Rds(on): 46mOhm @ 4.5V Vgs Vgs(th): -1.4V

Vgs(max): +/-12V Vds(max): -30V SI8409DB:

- =PPVIN_SW_T29BST (8-13V Boost Input)

- =PP18V_T29_REG (18V Boost Output)

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PP3V3_T29_FET (3.3V FET Output)

- =PP3V3_S0_T29PWRCTL

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

- =PP1V05_T29_FET (1.05V FET Output)

- =T29_CLKREQ_L

- =T29_RESET_L

T29BST:Y - Stuffs 18V boost circuitry.

B1A1B2

A2C2

2

48

1/16W402

25V40210%

2

1R3892

T29BST:Y 73.2K

MF-LF1%

1/16W402

2

1

R3887

2015%

T29BST:Y 330K

MF1/20W

4 5

3 Q3888

T29BST:Y SSM6N37FEAPE

SOT563

1 2

6 Q3888

T29BST:Y SSM6N37FEAPE

MF-LF1%

1/16W

402 2

1C3894

T29BST:Y 0.33UF

CERM-X5R6.3V40210%

2

1R3888

2015%

330K

MF1/20W

2

1

R3896

15.8K T29BST:Y

MF-LF1%

1/16W4022

1C3887

5%

47PF

50VCERM4022

1

C3892

X5R

T29BST:Y 4.7UF

80510%

MF-LF1%

1/16W402

2

1

R3891

T29BST:Y 200K

MF-LF1%

1/16W402

80525V 2

1

C3891

X5R

T29BST:Y 10UF

80525V

21

L3895

10UH-4A-68-MOHM

PCMB063T-100MS

CRITICAL T29BST:Y

33

3635102128

XW3895

SMPLACE_NEAR=C3897.1:2 mm2

1

R3889

MF-LF5%

T29BST:Y 0

1206X7R-CERM50V 2

C1B1A1C2

B2A2

2

1

C3816

NO STUFF 1UF

6.3V40210%

R3890

T29BST:Y 49.9K

1/16W1%

402

21

3

Q3805

SSM3K15AMFVAPE T29BST:YVESM

T29 Power Support

GND_T29BST_SGND

VOLTAGE=0VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

T29BST_RT

T29BST_VSNS T29BST_SNS2

Trang 36

INOUTOUT

NC

BI

BIBI

OUT

ININ

IN

OUT

BIBIBIBIBI

NC

WAKE*

CR_DATA4CR_DATA5

CR_LED*/CR_BUS_PWR

MS_INS*

CR_DATA7CR_DATA6CR_DATA0

CR_WP*

CR_CLK

TRD3_NTRD3_PGPIO_0/CR_ACT_LED*

GPIO_1/LR_OUTGPIO_2/MEDIA_SENSESD_DETECTCR_CMD

PCIE_TXD_PPCIE_RXD_P

CR_DATA3CR_DATA2CR_DATA1

TRD0_PTRD1_PTRD0_NTRD1_NTRD2_NVMAIN_PRSNT

PCIE_RXD_NPCIE_REFCLK_P

CLKREQ*

THRM_PAD

XTALIXTALORDAC

SI

GNDVCC

NOTE: "IPx" == Programmable pull-up/down SD_DETECT can only be used active low due to errata.

(IPU)

(IPx)

ROM is used then the straps must change

Atmel AT45DB011D (1Mbit) ROM If a different other 3 SPI pins configures ENET for the

(OD)

o

(OD)

NOTE: ENETM requires SI pull-down instead of SO

PHY Non-Volatile Memory

(Required ROM size TBD)

=ENET_WAKE_L to PCIE_WAKE_L

If PHY is always powered then alias

is powered-down in S3/S5 Standard

ROM contains MAC address, PCIe config

???mA (1000base-T, Caesar V)

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor

Internal 1.2V Switching Regulator pins

Required for proper PHY operation

info as well as code for Bonjour proxy

WAKE#

N-channel FET isolation suggested

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

No MS (Memory Stick) Insert feature needed

SR_DISABLE must be pulled down to useinternal SR IPD has a race condition

Must isolate from PCIe WAKE# if PHY

the card reader on-chip I/O

Connect only to U3900 pin 20

BCM57765 supports both active-levels for WP

NOTE: Pull-down on SO plus internal pull-ups on

BCM57765 ENET SR pins are internal 1.2V switching regulator See note for SR_DISABLE below

If disabled: Okay to float VDD, VDDP & LX pin VFB must always connect to =PP1V2_S3_ENET_PHY

Special Star routing needed on these pins Decoupling on Pg 37

VDD for Card Reader I/O

(IPD)(See note)

(IPD)Resistor

281mA (1000base-T max power, Caesar IV)

2

1

C3921

16V0.1UF0402 X7R-CERM

2

1C3935

10%

CRITICAL6.3V 80510UFX5R

2

10%

6.3V4.7UF603 X5R-CERM

2 1

L3925

FERR-600-OHM-0.5ACRITICAL

SM 2

10%

4.7UFX5R-CERM 603 6.3V

2 1

L3920

FERR-600-OHM-0.5ACRITICAL

SM

2 1

L3900

CRITICALFERR-600-OHM-0.5ASM

2 1

L3905

FERR-600-OHM-0.5ASMCRITICAL

2

1R3942

402 1/16W 5%

16V

0.1UF

X7R-CERM 0402

2 1C3950

16V

0.1UF

X7R-CERM 0402

2 1C3956

16V

0.1UF

X7R-CERM 0402

2 1C3955

16V

0.1UF

X7R-CERM 0402

2

1

R3965

402 1/16W1.24K1%

4.7K

5%

MF-LF 2

1R3940

402

4.7K

1/16W 5%

1R3943

402 1/16W

1C3971

16V0.1UF0402 X7R-CERM 2

24

2

1R3910

402

4.7K

1/16W 5%

MF-LF

2 1

R3980

402 1/16W

1K

5% MF-LF

30

2 1

L3910

FERR-600-OHM-0.5ASMCRITICAL

30 82

2

1C3900

19 18 3

46 47

44 43

40 41

10 6 64

63

57 60 55 54 53 52 22 23 24 25

26 21 12

2

10%

4.7UF6.3V X5R-CERM 603 2

1

C3931

2 1

L3930

CRITICALFERR-600-OHM-0.5ASM

1C3916

5

8

1 2

2

1

R3997

402 MF-LF4.7K5%

2

1

C3926

ETHERNET PHY (CAESAR IV)

SYNC_MASTER=J31_MLB SYNC_DATE=06/15/2011

PP3V3R1V8_ENET_LR_OUT_REG

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MIN_LINE_WIDTH=0.3 mm MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmPP3V3_S3_ENET_PHY_BIASVDDHMIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V

PP3V3_S3_ENET_PHY_XTALVDDHMIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_ENET_PHY_AVDDHVOLTAGE=3.3V

PP1V2_ENET_PHY_AVDDLMIN_LINE_WIDTH=0.4 mm VOLTAGE=1.2V

PP1V2_ENET_PHY_PCIEPLLMIN_LINE_WIDTH=0.4 mm VOLTAGE=1.2V

PP1V2_ENET_PHY_GPHYPLLVOLTAGE=1.2V

PCIE_ENET_R2D_PPCIE_CLK100M_ENET_N

=PP1V2_ENET_PHY

ENET_SR_LXENET_SR_VFB

ENET_CLKREQ_L

SYSCLK_CLK25M_ENETBCM57765_RDAC

PCIE_ENET_R2D_C_PPCIE_ENET_R2D_C_N

=PP3V3_S0_ENETPHY

051-9058 6.0.0

Trang 37

RXTX

BI

RX

TX

BIBI

QTY

Place one of 0.1uf cap close to each centertap pin of transformer

Page Notes

sides of the board mirrored on opposite

5432

121110

75

5%

21

C4008

10%

1000PF CRITICAL

1C4004

10%

0.1UF

X5R-CERM02012

1C4002

10%

0.1UF

X5R-CERM0201

9876

5432

121110

1

T4001

OMIT_TABLE CRITICAL

36

9

8 7 6 5 4 3 2

12 11

Trang 38

ATBUSHATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMSTCKREFCLKNPCIE_TXD0P

TRST*

ATBUSB

TDI

DS1TPA0NTPA0P

AVREGCE

CLKREQN

FW_RESET*

FW620*

JASI_ENMODE_ANAND_TREE

OCR_CTL_V12

PCIE_RXD0NPCIE_RXD0PPCIE_TXD0N

SCLSDASE

SM

TDOTPA1N

TPA2NTPA2PTPB0NTPB0PTPB1NTPB1PTPB2NTPB2PTPBIAS0TPBIAS1TPBIAS2TPCPS

DS0

TPA1P

VDD33VDD10

VREG_VSSVSS

SERIAL EEPROMMISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLERPCI EXPRESS PHY

CHIP RESETSCIF

1394 PHY

NCNCNC

NC

ININ

OUTOUT

OUT

INININBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

IN

NCNC

(IPD)(IPD) NT-1(IPU)

(IPD)(IPD)

(IPD) NT-11

NT-15 (IPD)NT-14 (IPD)NT-16 (IPD)

(IPD) NT-4(IPD) NT-3

138 mA

7 mA I/O

25 mA PCIe SerDes

NT-7NT-6

NT-5NT-OUT

NT-10 (IPD)FIXME!!! - TYPO IN SYMBOL REGCTL

NT-20 (IPU)NT-21 (IPU)

NT-13

- TP (or NC) PME#

- Gate CLKREQ# based on PHY power

isolated for systems that useNOTE: FW_PME_L and FW_CLKREQ_L are

- Alias both signals to drop = prefix

NT-18 (IPU)

WITH PLUG DETECT:

WITHOUT PLUG DETECT:

110 mA Digital Core

2

1R4170

402 MF-LF 1%

191

2

1C4162

402 CERM-X5R 6.3V0.33UF10%

2

1

R4162

402 5%

470KMF-LF

F13 G13

B10 A2 C3 B7 A4 B4 A6 B6 A9 B9 A3 B3 A5 B5 A8 B8

M3 M1 N2 M4

N13 M13

M11 N12

F2 H1 G1 G2 L8

D13

N10 N9

B11

N4

N6 N5 N7 N8

J13 J12

K1

J2 D1 K13 D12

E13 E12 F12

L2

L13 A10

A11 A13 B13

U4100

FW643ECRITICAL

BGAOMIT

2 1

C4151

5%

22PF

0402 50V

2 1

C4150

5%

22PF

0402 50V

2

1

R4160

402 1/16W200K1%

2 1

R4150

402412MF-LF 1%

1/16W10K

2

1

R4164

402 5%

MF-LF10K1/16W

2

1

R4165

402 5%

10KMF-LFFW643_LDO

2

1

R4166

402 5%

1/16W10K

2

1

C4130

402 CERM1UF6.3V10%

2

1

C4131

402 CERM1UF6.3V10%

2

402 CERM1UF6.3V 10%

2

402 CERM1UF6.3V 10%

2

1

C4132

402 CERM1UF10%

2

1C4102

402 CERM1UF6.3V 10%

2

1C4103

402 CERM1UF6.3V 10%

2

1

C4135

402 CERM1UF6.3V 10%

2

1

C4136

402 CERM1UF6.3V 10%

2

1C4104

402 CERM1UF6.3V 10%

2

402 CERM1UF6.3V 10%

2

402 CERM1UF6.3V 10%

2

402 CERM1UF6.3V 10%

2

1

C4120

402 CERM1UF6.3V10%

2

1

C4121

402 CERM1UF6.3V10%

2

1

C4122

402 CERM1UF6.3V10%

2

1

C4123

402 CERM1UF6.3V10%

2

1

C4124

402 CERM1UF6.3V10%

2

1

C4141

4020.1UFCERM 10V

2

402 CERM1UF6.3V 10%

2

402 CERM1UF6.3V 10%

L4130

120-OHM-0.3A-EMI0402-LF

2 1

L4135

0402-LF120-OHM-0.3A-EMI

39

2 1

L4110

120-OHM-0.3A-EMI0402-LF

0.1UF X7R-CERM 0402

PLACEMENT_NOTE=Place C4170 close to U1400

16V 10%

2 1C4171

0.1UF X7R-CERM 0402

16V 10%

2 1C4175

0.1UF X7R-CERM 0402

16V 10%

2 1C4176

0.1UF X7R-CERM 0402

16V 10%

FireWire LLC/PHY (FW643E)

VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 MMPP3V3_FW_FWPHY_VDDA

VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 MMPP3V3_FW_FWPHY_VP25PP1V0_FW_FWPHY_AVDD

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.0V

=PP1V0_FW_FWPHY

=PP3V3_FW_FWPHY

FW_CLK24P576M_XI

PCIE_FW_D2R_PPCIE_FW_D2R_C_P

PCIE_FW_D2R_NPCIE_FW_D2R_C_N

PCIE_FW_R2D_C_NPCIE_FW_R2D_N

PCIE_FW_R2D_C_PPCIE_FW_R2D_P

TP_FW643_SCIFCLK

=FW_CLKREQ_L

TP_FW643_SCIFMCFW_CLK24P576M_XO

TP_FW643_OCR10_CTL

PCIE_CLK100M_FW_N

TP_FW643_AVREG

TP_FW643_CETP_FW643_FW620_LTP_FW643_MODE_ATP_FW643_NAND_TREE

PCIE_CLK100M_FW_P

TP_FW643_SCIFDOUT

TP_FW643_SDATP_FW643_SE

TP_FW643_SM

TP_FW643_TDOFW_P1_TPA_P

FW_P1_TPA_NFW_P2_TPA_NFW_P2_TPA_PFW_P0_TPB_NFW_P1_TPB_PFW_P2_TPB_NFW_P2_TPB_PFW_P0_TPBIASFW_P2_TPBIAS

FW_P0_TPA_PFW_P0_TPA_N

FW643_PU_RST_L

FW_RESET_LFW643_SCL

TP_FW643_VAUX_ENABLEFW643_VAUX_DETECTFW643_REGCTL

=FW_PME_L

FW643_TRST_LTP_FW643_TMS

TP_FW643_SCIFDAINFW643_REXT

TP_FW643_JASI_ENTP_FW643_VBUF

TP_FW643_TDITP_FW643_TCK

=PPVP_FW_PHY_CPS

FW_CLK24P576M_XO_R

FW643_TPCPSFW643_R0FW_P1_TPB_N

051-9058 6.0.0

Trang 39

S

ININ

GD

S

OUT

IN

SGD

GNDVOUTONVIN

IN

OUT

INOUTIN

IN

RESET*

OUTENMR*

GND THRM

IN

VDD

SENSE+

PAD

(OD)

0.7VDLY

FireWire Port 5K Pull-Down Detect

FireWire PHY WAKE# Support

DLY = 60 ms +/- 20%

3.3V FW Switch Supervisor & CLKREQ# Isolation

Max Output: 2APart

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

- =PP3V3_S0_FWPWRCTL

- =PP1V0_FW_FWPHY (PHY 1.0V)

- =PP1V05_FW_P1V0FWFET (1.0V FET Input)

- =PP3V3_FW_P3V3FWFET (3.3V FET Input)

- =PP3V3_FW_FET (3.3V FET Output)

- =PP3V3_FW_FWPHY (PHY 3.3V Power)

- =PPBUS_S5_FWPWRSW (FW VP FET Input)

Current source only active when FW_PWR_EN is low

All FireWire devices require 5K pull-down on TPB pair

Host can detect as load on TPBIAS signal

Dual-purpose output:

1) 5K Pull-down Detect when FW_PWR_EN is low

Pull-up provided on another page

- =FW_PME_L

- =FW_CLKREQ_L

2) FW643 WAKE# (PME#) when PHY is powered

FireWire Port Power Switch

50 mOhm MaxLoad Switch

1.05V is used with a series R

To avoid an extra power supply,LSI FireWire PHY requires 1.0V

- =PPBUS_FW_FET (FW VP FET Output)

Pull-up provided by another page

2

1

C4260

X5R0.1UF10%

402 2

1

R4260

300KMF-LF 5%

1/16W 402

2

1

R4261

470K5%

MF-LF 402

2 1F4260

CRITICAL

MINISMDC110H24

1.1A-24V

K AD4260SM

CRS08-1.5A-30VCRITICAL

1

6

BC847CDXV6TXG SOT563CRITICAL

4

3 5Q4270

BC847CDXV6TXGCRITICALSOT563 2

1

R4270

330K1/16W 5%

MF-LF 402

2

1

R4271

1/16W 5%

MF-LF56K402

2

1

R4273

12KMF-LF 5%

402 2

1

R4272

1/16W1K5%

MF-LF PLACE_NEAR=C4360.1:2 mm

402

1 2

6

Q4275SOT-563

0402 X7R-CERM

1K5%

MF-LF 402

6

Q4276SOT-563

402

2

1C4276

10K1/16W 5%

MF-LF 402

BSS8402DW

SOT-363

2

1R4262

10KMF-LF 5%

1/16W 402

1 2 6

X5R

NO STUFF25V0.1UF10%

402

2

1R4263

MF-LF 5%

10

402

B1 A1 B2

A2 C2

U4201

CSPCRITICAL

TPS22924

B1 A1 B2

A2 C2

U4202

CSPCRITICAL

TPS22924

40

2

1R4202

0.549

1%

1/16W MF 402

38 1

2R4283

10K

5%

MF-LF 402

1UF

6.3V 10%

CERM 402

2

1C4202

1UF

6.3V 10%

CERM 402

2

4 8

21

FWPORT_PWR_EN

FWPORT_PWREN_L

MAKE_BASE=TRUEFW_CLKREQ_PHY_L

MIN_LINE_WIDTH=0.5 mmPPBUS_FW_FWPWRSW_DMIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 mmPPBUS_FW_FWPWRSW_FMIN_NECK_WIDTH=0.25 mm

FW643_WAKE_LMAKE_BASE=TRUE

VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 mmPP1V05_FW_FET

MAKE_BASE=TRUEFW_5KPD_DET_L

FW_RESET_LFW_PWR_EN

FWPORT_PWREN_L_DIV

=FW_PME_L

FW_PME_LFW_P1_TPBIAS

051-9058 6.0.0

Trang 40

TPA+ TPA(R) VG

VP TPB+

TPB(R) TPB-

TPA-CHASSIS GND

D2-D1+

FWPWR_ENOUT

OUTOUTOUT

BIBIBIBI

IN

BIBIBIBIIN

AREF needs to be isolated from alllocal grounds per 1394b specWhen a bilingual device is connected to abeta-only device, there is no DC pathbetween them (to avoid ground offset issue)

- =FW_PHY_DS0

NOTE: This page is expected to contain

appropriate connectors and/or to

(PINS 5/6 AND 7/8 ARE SWAPPED FOR BETTER ROUTING)

"Snapback" & "Late VG" Protection

Note: Trace PPVP_FW_PORT1 must handle up to 5A

TPA-BILINGUAL

TPB+

VP NC

TPB<R>

TPB-INPUTOUTPUT

FireWire PHY Config Straps

properly terminate unused signals

the necessary aliases to map the

- =PPVP_FW_PHY_CPS_FET (From Port)

Page Notes

FireWire TPA/TPB pairs to their

FW643 has internal leakage path from TPCPS pin to VDD33

CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED

2

1

R4363

SIGNAL_MODEL=EMPTY56.2MF-LF 1%

1/16W 402

2

1

R4364

4.99KMF-LF 1%

1/16W 402

2

1

R4362

1/16W 1%

MF-LF56.2SIGNAL_MODEL=EMPTY

402

2

25V C0G-CERM 0402 5%

2

1C4360

6.3V0.33UFCERM-X5R 402 10%

2

1

R4360

1/16W SIGNAL_MODEL=EMPTY56.2MF-LF 1%

0.1uF50V

2

1R4319

1/16W1MMF-LF 5%

402

2

X7R0.01UF50V 402 10%

2 1

L4310

CRITICAL

SMFERR-250-OHM

9 8 7 6 5 4 3 2

13 12 11 10

1

J4310

CRITICAL1394B-M97F-RT-TH

2

1

R4381

1/16W 1%

MF-LF10K402

2

1

R4382

10KMF-LF 1%

MF-LF10K402

6

Q4300

BSS8402DWSOT-363

2

1

R4312

330KMF-LF 5%

8 7

U4350

TPD4S1394

LLPCRITICAL

2

1C4350

PLACE_NEAR=U4350.1:2 mm

0402

0.1UF

X7R-CERM 16V

2

1

R4350

1/16W100KMF-LF 5%

FW_PORT1_AREF

=PP3V3_S0_FWLATEVG

FWPORT_PWR_ENTP_FWLATEVG_VCLMPFW_P1_TPBIAS

FW_P1_TPA_NFW_P1_TPA_P

FW_P0_TPB_NFW_P2_TPA_PFW_P2_TPBIAS

FW_P0_TPA_PFW_P0_TPA_NFW_P0_TPB_PFW_P0_TPBIAS

FW_PORT1_TPA_NMAKE_BASE=TRUE

PPVP_FW_PORT1_FVOLTAGE=33V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=12.6V MAKE_BASE=TRUEPPVP_FW_CPS

NO_TEST=TRUENC_FW2_TPBN

MAKE_BASE=TRUE

NO_TEST=TRUENC_FW2_TPBP

MAKE_BASE=TRUE

NC_FW2_TPAP

NO_TEST=TRUENC_FW2_TPBIAS

MAKE_BASE=TRUE

NO_TEST=TRUENC_FW0_TPBN

MAKE_BASE=TRUE

NO_TEST=TRUENC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW0_TPAN

NC_FW0_TPAP

NC_FW0_TPBIAS

MAKE_BASE=TRUEFWPHY_DS1MAKE_BASE=TRUEFWPHY_DS2MAKE_BASE=TRUEFWPHY_DS0

FW_PORT1_TPA_PMAKE_BASE=TRUE MAKE_BASE=TRUEFW_PORT1_TPB_P

051-9058 6.0.0

Định dạng
Số trang	86
Dung lượng	1,49 MB