apple macbook pro fa255 m42c mlb

ININININININ IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO OUTOUTOUT IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO IOIOIOIOIOIOI

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

ANGLES

3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2 ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE APPD ENG

DATE

APPD CK ECN

ZONE REV

DO NOT SCALE DRAWING

X.XXXX.XXXXDIMENSIONS ARE IN MILLIMETERS

DSIZENOTED AS

MATERIAL/FINISH

NONESCALEDESIGNERMFG APPDDESIGN CK

RELEASE

QA APPDENG APPDDRAFTERMETRIC

DRAWING NUMBERTITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCEIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY ITAGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYApple Computer Inc.

1 2

3 4

5 6

7 8

B C D

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DRAWING

REFERENCE DESIGNATOR(S) BOM OPTION

TABLE_5_HEADQTY DESCRIPTION

DK RX

RX MK

RX

DK DK

RX RX

RX RX ES RX

LT LT LT DK DK ES ES ES ES ES ES ES ES ES MK

LD MK ES

RX

DK MK

MK MK MK ES DK

DK

ES-ERIC SMITH LD-LINDA DUNN

LT MK

MK-MARC KLINGELHOFER RC-RAY CHANG

CPU ITP700FLEX DEBUG

MASTER11

NB12

NB CPU Interface

ENET6

SIGNAL ALIAS /RESET

SATA CONNECTOR

ENET38

PATA CONNECTOR

CLOCK33

CLOCKS

(MASTER)31

Memory Vtt Supply

MEMORY30

Memory Active Termination

MEMORY29

DDR2 SO-DIMM Connector B

MEMORY28

DDR2 SO-DIMM Connector A

ENET27

M42 SMBUS CONNECTIONS

NB26

SB Misc

SB25

SB24

ENET23

NB19

NB (GM) Decoupling

ENET44

FIREWIRE CONTROLLER

ENET51

FIREWIRE PORT

ENET52

CPU MISC1-TEMP SENSOR

08/30/2005

NB60

LPC+ Debug Connector

SMC59

SMC SUPPORT

SMC58

SMC

ENET54

BLUETOOTH INTERFACE

ENET53

07/25/2005NB

NB Power 1

MASTER2

SYSTEM BLOCK DIAGRAM

N/A1

Table of Contents

ENET49

CONNECTOR MISC

SMC9

CPU DECAPS & VID<>

CONFIGURATION OPTIONS

SMC4

Cross Reference Page

NB Config Straps

SCHEM,MLB,MACBOOK

C 051-7173

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OFSHTDRAWING NUMBER

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY ITAGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

IR_RX_OUT

SATA

IR

HDD Connector P.35

USB

P.41 CONTROLLER

ODD

16BITS

P.54-57

P.40 AUDIO

P.64 SMBUS

P.68

P.42

P.69 P.67

P.67

LCD Panel

INVERTER CONNECTOR

MINI DVI &

CRT CONNECTOR

ETHERNET CONNECTOR

P.37

FW CONNECTOR

DMIX4 PCIEX1

SDVO

P.12-20

609 BGA CHIPSET-SB

FSB

479 BGA

PROCESSOR

CLOCKING THERMAL

LVDS

ENET CONTROLLER P.36

FAN CONNECTOR P.27

1466UFCBGA CHIPSET-NB

SMBUS

REGULATOR

P.31 Config

USB 2.0

SMS

DDR2 VTT

P.29 SO-DIMM Connector

J2900 J2800

CPU

P.32-33 AND SPECTRUM

CH.A TV+CRT

SB MISC.

P.21-26

SMC BOOTROM

SYNC_DATE=5/23/05 SYNC_MASTER=MASTER

SYSTEM BLOCK DIAGRAM

1082

Trang 3

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

VR_PWRGOOD_DELAY

PM_RSMRST_L IMVP_VR_ON

24

U7500 (PAGE 57)

16

Q8060

(S5) 5VS5_RUNSS Q8059

MAX8887

2.5V

VINPP3V3S3_EN_L_RC

PP5VS3_EN_L_RC

12 12

SLP_S4_LSLP_S5_L

VIN

(4A MAXVOUT2

U8375 U8370

SOFT

(S0)

CPUPWRGD(GPIO49)VRMPWRGD

CPU

ENAVIN

7ms 200ms

(PAGE 62)

PWRGOODCK410_PD_VTT_PRGD_L

MCH

PWRGD

SMC_RST_L SMC PWRGD

H(S5 ON) H(S5 ON)

01-04 STEP

NO AC/BATTERY

U5800 (PAGE 44)

SLP_S4_L(P94)SLP_S3_L(P93)

P60

P25

PWRGD(P12)IMVP_VR_ON(P16)99ms DLYRSMRST_OUT(P15)

1.05V

VOUT1VIN

(S0) (S3)

POWER ON SEQUENCE LIST

VR_PWRGOOD_DELAY S0PWRGD_OK

(S3)

c=0.01uf

P1V2S0_ENDELAY

1V5S0_RUNSS

(S0)

DELAY

Q8030 Q8030

R=10kc=0.1uf

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TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM

PART#

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

PART#

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

SIGNAL(High Speed)

L4 SIGNAL L2 GROUND

(MM) 0.018

L1-L2 L1 SIGNAL(TOP) CONFORMAL_COAT

BETTER-ST BEST-KIONIX

5V3V3S3_CONT 1V51V05S0_SKIP 1V51V05S0_CONT

GROUND SIGNAL

SIGNAL(High Speed)

GROUND 3

FANCY NORMAL

STANDOFF

ONEWIRE_PU_ACOK ONEWIRE_PU_PROT

ONEWIRE_PWRCTL

BETTER GOOD

BEST

USB_C_OC_PU USB_D_OC_PU USB_E_OC_PU

630-7799

M42A BEST KIONIX

630-7798 EVT KIONIX

630-7736 EVT

KIONIX M42A BETTER M42A GOOD

0.014 0.156

0.076 0.014 0.014

(MM)

0.07

0.1 L5 GND

0.076

0.1 0.1

L9-L10

L11-L12 L8-L9 L4-L5

CONFORMAL_COAT

L11 GROUND

L12 SIGNAL(BOTTOM)

0.014 0.156

0.018

0.076

0.031

0.014 0.07

0.07 0.047 0.1

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

ONEWIRE_PULLUP M42A_PGM

1

EEE:WEULBL,P/N LABEL,PCB,28MMX6MM

EEE:WEW826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM CRITICAL BEST-KIONIX

108SYNC_DATE=07/18/2005

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OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

Other Func Test Points

I156

I157I158I159I16

I160I161I162I163I164I165I166I167I168I169I17

I170I171I172I173I174

I175I176

I177

I178I179

I29I3

I31I32I33I36I38I4

I44I45

I46I47I48

I57

I58

I59I60I61I63

I71I72I73I74I75I76I77I78I79I80I81I82I83I84I85I86I87I88I89

I9

I90I91

TRUE SMC_MANUAL_RST_L

SMC_LID TRUE

LVDS_B_DATA_N0_SPN TRUE

FW_C_TPB_P_SPN TRUE

LVDS_B_DATA_P1_SPN TRUE

TRUE =PP5V_S0_FAN_RT TRUE FAN_RT_PWM TRUE FAN_RT_TACH TRUE =PP3V3_S0_FAN_RT

SMC_FAN_1_CTL TRUE

SMC_FAN_1_TACH TRUE

SMBUS_BATT_SDA_F TRUE

TRUE =PP3V42_G3H_LPCPLUS

LPC_AD<0>

TRUE TRUE LPC_FRAME_L TRUE BOOT_LPC_SPI_L TRUE SMC_TMS

TRUE SMC_TDO

TRUE LPC_AD<2>

TRUE LPC_AD<3>

TRUE INT_SERIRQ TRUE SMC_TDI

TRUE SV_SET_UP TRUE SMC_RX_L

TRUE SMBUS_SMC_MLB_SCL TRUE SMBUS_SMC_MLB_SDA

PPFW_SWITCH TRUE

SYS_LED_ANODE TRUE

FW_C_TPB_N_SPN TRUE

LVDS_B_CLK_N_SPN TRUE

TRUE LVDS_B_DATA_N1_SPN

FW_C_TPA_N_SPN TRUE

FW_B_TPB_P_SPN TRUE

TRUE SMC_TX_L TRUE FWH_INIT_L TRUE PCI_CLK_PORT80_LPC

TRUE PM_SUS_STAT_L

FW_C_TPA_P_SPN TRUE

FW_C_TPBIAS_SPN TRUE

TRUE SMC_TCK

LVDS_B_CLK_P_SPN TRUE

FW_B_TPB_N_SPN TRUE

CK410_SRC5_N TRUE

TRUE CK410_SRC4_P TRUE CK410_SRC4_N TRUE CK410_SRC3_P_SPN TRUE CK410_SRC3_N_SPN TRUE CK410_SRC2_P TRUE CK410_SRC2_N

CK410_PCIF1_CLK TRUE

TRUE CK410_SRC1_N_SPN

PP3V3_S3 TRUE

PP5V_S3 TRUE

PP3V3_S5 TRUE

PP5V_S5 TRUE

PP3V42_G3H TRUE

PPBUSA_G3H TRUE

PPBUSB_G3H TRUE

PP18V5_G3H TRUE

PP0V9_S0 TRUE

PP1V8_S0 TRUE

PP2V5_S0 TRUE

PP3V3_S0 TRUE

PP5V_S0 TRUE

TRUE =PP1V05_S0_REG

PP1V5_S0 TRUE

PP1V2_S3 TRUE

PP1V8_S3 TRUE

PP2V5_S3 TRUE

CK410_PCI4_CLK_SPN TRUE

CK410_SRC8_P TRUE

CK410_SRC7_P_SPN TRUE

FW_B_TPBIAS_SPN TRUE

FW_B_TPA_P_SPN TRUE

FW_B_TPA_N_SPN TRUE

CK410_SRC7_N_SPN TRUE

CK410_SRC1_P_SPN TRUE

CK410_LVDS_N TRUE

CK410_CPU2_ITP_SRC10_N TRUE

CK410_CPU1_P TRUE

CK410_CPU0_P TRUE

CK410_CPU0_N TRUE

BATT_IN TRUE

BATT_POS TRUE

BATT_NEG TRUE

TRUE PP5V_S0_AUDIO

GND_AUDIO_PWR TRUE

GND_AUDIO_CODEC TRUE

TRUE LPC_AD<1>

SMC_BATT_TRICKLE_EN_L TRUE

=PP5V_S0_LPCPLUS TRUE

TRUE P3V42G3H_FB

TRUE DEBUG_RST_L TRUE SMC_TRST_L

SMBUS_BATT_SCL_F TRUE

ACZ_SDATAIN<0>

TRUE

ACZ_SYNC TRUE

SYS_ONEWIRE TRUE

TRUE PM_CLKRUN_L

TRUE SMC_MD1

TRUE SMC_RST_L TRUE SMC_NMI

SMC_PS_ON TRUE

SMC_BC_ACOK TRUE

SMC_BATT_ISET TRUE

ACZ_RST_L TRUE

ACZ_BITCLK TRUE

ACZ_SDATAOUT TRUE

TRUE PP5V_S0_AUDIO_PWR

SMC_BS_ALRT_L TRUE

TP_USBP_E TRUE

TP_USBP_F TRUE

TP_USBN_E TRUE

TP_USBN_F TRUE

ACIN_ENABLE_GATE TRUE

PPVBAT_G3H_CHGR_OUT TRUE

PP5V_INV_F TRUE

INV_GND TRUE

PPBUS_ALL_INV_CONN TRUE

INV_BKLIGHT_PWM_L TRUE

1V5S0_RUNSS 1V8S3_COMP 5VS5_RUNSS

ALL_SYS_PWRGD TRUE

PPVCORE_CPU_S0 TRUE

PP1V05_S0 TRUE

TRUE 3V3S5_COMP

1V8S3_FSET

IMVP6_COMP IMVP6_RBIAS

SMC_BATT_CHG_EN TRUE

CK410_SRC6_P TRUE

CK410_SRC_CLKREQ1_L_SPN TRUE

CK410_SRC_CLKREQ3_L_SPN TRUE

CK410_SRC_CLKREQ8_L TRUE

CK410_SRC6_N TRUE

TRUE 3V3S5_FSET

1V05S0_COMP TRUE

1V05S0_FSET TRUE

CK410_CPU1_N TRUE

CK410_CPU2_ITP_SRC10_P TRUE

CK410_DOT96_27M_N TRUE

CK410_DOT96_27M_P TRUE

CK410_LVDS_P TRUE

CK410_SRC5_P TRUE

CK410_SRC8_N TRUE

LVDS_B_DATA_N2_SPN TRUE

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DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

PART#

DIGITAL GND SCREW HOLE

Ethernet ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

(EMI PAD FOR INVERTER GONNECTOR)

I/O CONNECTOR CHASSIS GND

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND

NC

CHASSIS GND

NO-CONNECT UNUSED SDVO INTERFACE PORTS

PCI_EXPRESS GRAPHICS ALIASES

LVDS ALIASES

NO-CONNECT UNUSED LVDS INTERFACE PORTS

USB PORT "H" = PCI-E Mini Card USB PORT "F" = IR CONTROLLER

USB PORT D = CAMERA

USB PORT "E" = Unused USB PORT C = External USB2.0 Port B

ANALOG SWITCH GPIO

USB PORT B = Trackpad(Geyser) USB PORT A = External USB2.0 Port

USB PORT "G" = BLUETOOTH

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS

NO-CONNECT UNUSED SATA INTERFACE PORTS

PCI_EXP ALIASES SATA ALIASES

DIP DIMM CONNECTOR CHASSIS GND

SATA,LVDS CONNECTOR CHASSIS GND

DCIN CONNECTOR CHASSIS GND

1

OMIT 5R2P3-7SQB Z0606

1

OMIT 5R2P3-7SQB Z0602

402

2

10.01uF

C0608

10%

CERM

402210%

0.1UF

C06071

X5R

OMIT

15R2P3-7SQB Z0601

C0611

0.01uF21

16VCERM402

21

402

C0610

0.1UF10%

X5R

1

Z0609

5R2P3-7SQB OMIT

2

0.01uF402CERM16V

1

5R2P3-7B

C061921

10%

0.01uF402CERM16V

X5R

R0610

21

MF-LF4021/16W5%

0

0.01uFCERM402

C0614

0.1UF40221

16V

21

CERM40216V0.01uF

2

1R0621

05%

MF-LF

1

Z0608

5P0R2P3-7BLB OMIT

1

240216V

C0630

0.1UF10%

1

CLIP-SM-M42

ZS0620EMI-SPRING

SPKR-MIC-CLIP-M42

SM

ZS06211

OMIT STDOFF-4.5OD3.95H-1.1-3.7-TH1 Z0604

1

SYNC_DATE=08/19/2005SYNC_MASTER=ENET

VOLTAGE=0VGND_CHASSIS_SATAMAKE_BASE=TRUE

MAKE_BASE=TRUEVOLTAGE=0VGND_CHASSIS_DCIN

VOLTAGE=0VMAKE_BASE=TRUEGND_CHASSIS_IO

GND_CHASSIS_CENTERMAKE_BASE=TRUEVOLTAGE=0V

=GND_CHASSIS_USB

=GND_CHASSIS_FW_DOWN

=GND_CHASSIS_TMDS_DOWN

GND_CHASSIS_IO1VOLTAGE=0VMAKE_BASE=TRUE

ENET_CTRL12

MEM_B_A<14>

MAKE_BASE=TRUE

MEM_B_A14_SPNMEM_B_A<15>

MEM_A_A<14>

MAKE_BASE=TRUE

MEM_A_A14_SPNMEM_A_A<15>

MAKE_BASE=TRUE

CK410_SRC3_N_SPN

MAKE_BASE=TRUE

CK410_SRC3_P_SPNCK410_SRC1_N

NB_CFG<11>

MAKE_BASE=TRUE

TP_NB_CFG11NB_CFG<12>

MAKE_BASE=TRUE

FW_C_TPA_N_SPNFW_C_TPA_P FW_C_TPA_P_SPN

MAKE_BASE=TRUE

FW_B_TPB_N

MAKE_BASE=TRUE

FW_B_TPB_N_SPNFW_C_TPBIAS

MAKE_BASE=TRUE

FW_B_TPA_N_SPNFW_B_TPA_P

MAKE_BASE=TRUE

FW_B_TPA_P_SPNFW_B_TPBIAS

MAKE_BASE=TRUE

FW_B_TPBIAS_SPN

MAKE_BASE=TRUEUSB2_EXTA_P USB_A_PMAKE_BASE=TRUE

EXTAUSB_OC_L USB_A_OC_LUSB2_EXTA_N

MAKE_BASE=TRUE

USB_A_N

USB2_GEYSER_PMAKE_BASE=TRUE

USB_B_P

USB2_EXTB_PMAKE_BASE=TRUE

USB_C_P

USB2_GEYSER_NMAKE_BASE=TRUE

USB_B_N

MAKE_BASE=TRUEEXTBUSB_OC_L USB_C_OC_LUSB2_EXTB_N

MAKE_BASE=TRUE USB_C_N

MAKE_BASE=TRUEUSB2_CAMERA_P USB_D_PMAKE_BASE=TRUE

USB2_CAMERA_N USB_D_N

MAKE_BASE=TRUETP_USBP_E USB_E_PMAKE_BASE=TRUE

TP_USBN_E USB_E_N

MAKE_BASE=TRUEUSB_IR_P USB_F_PMAKE_BASE=TRUE

USB_IR_N USB_F_N

MAKE_BASE=TRUEUSB_BT_P USB_G_PUSB_BT_N

MAKE_BASE=TRUE

USB_G_N

MAKE_BASE=TRUEUSB2_AIRPORT_P USB_H_PUSB2_AIRPORT_N

MAKE_BASE=TRUE

USB_H_N

MAKE_BASE=TRUESB_GPIO22 TP_SB_GPIO22

MAKE_BASE=TRUE MAKE_BASE=TRUE

PEG_D2R_N14_SPN

MAKE_BASE=TRUE

PEG_D2R_N12_SPN

LVDS_B_CLK_PLVDS_B_DATA_N<0>

PEG_R2D_C_N14_SPNPEG_R2D_C_N13_SPN

PEG_R2D_C_P15_SPNPEG_R2D_C_P<13>

LVDS_B_DATA_N1_SPN MAKE_BASE=TRUE

LVDS_B_DATA_N0_SPN MAKE_BASE=TRUELVDS_B_CLK_P_SPN

PEG_R2D_C_P<14>

PEG_R2D_C_P7_SPN

MAKE_BASE=TRUE MAKE_BASE=TRUE

Trang 7

ININININININ

IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

OUTOUTOUT

IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

IOIOIOIOIOIOIO

IO

IOIOIOIOIOIOIO

IO

OUT

OUTOUT

OUT

IN

INININININ

ININININ

OUT

ININ

INININ

INOUT

A7*

RSVD14RSVD15

BCLK1BCLK0

RSVD20

RSVD17RSVD18RSVD19RSVD16RSVD13RSVD12

THERMTRIP*

THERMDCTHERMDAPROCHOT*

DBR*

TRST*

TMSTDOTDITCKPREQ*

RSVD1RSVD2RSVD3RSVD4RSVD5

RSVD9RSVD10

SMI*

LINT0LINT1STPCLK*

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

WITHOUT T-ING (NO

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD ECM*50

SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

PLACE GND VIA W/IN 1000 MILS

FSB_IERR_L WITH A GNDPLACE TESTPOINT ON

LAYOUT NOTE: 0.5" MAX LENGTH

ICH7-M AND GMCH

TRACE LENGTH SHORTER THAN 0.5"

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKELAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

CPU_PROCHOT_L TO SMC

SHOULD CONNECT TOPM_THRMTRIP#

54.91%

R0702

1

2

MF-LF402

5%

1/16W68

R0704

1

2

1/16W1%

402MF-LF1K

R0705

1

2

1/16W1%

402MF-LF2.0K

R0717

40227.4

R0716

0402

NOSTUFF

R0730

NOSTUFF 1KMF-LF402

5%

1/16W51

R0712

1

2

54.91%

1/16W402

R07031

OMIT

U0700

N3P5P2L1P4P1R1

Y2U5R3W6

A6

U4Y5U2R4T5T3W3W5Y4J4

W2Y1

L4M3K5M1N2J1

H1

L2

V4

A22A21

E2

AD4AD3AD1AC4

G5

F1

C20

E1H5F21

A5

G6E4D20

C4

B3

C6B4

H4

AC2AC1

D21

K3H2K2J3L5

B1F3F4G3

AA1

C3B25

T22

D2F6D3C1AF1D22C23AA4

C24

AB2AA3M4N5T2V3B2

A3D5

AC5AA6AB3

A24A25C7AB5G2

AB6

CPU YONAH

BGA

OMIT

U0700

B22B23C21

R26U26U1V1

E22F24

J24J23H26F26K22H25

N22K25P26R23E26

L25L22L23M23P25P22P23T24R24L26H22

T25N24

AA23AB24V24V26W25U23U25U22F23

AB25W22Y23AA26Y26Y22AC26AA24

AC22AC23G25

AB22AA21AB21AC25AD20AE22AF23AD24AE21AD21E25

AE25AF25AF22AF26

E23K24G24

H23

M24

W24

AD23G22

N25

Y25

AE24

AD26A2

AE6D6D7

C26D25

CPU_PSI_L FSB_SLPCPU_L CPU_PWRGD

CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L

FSB_CLK_CPU_N FSB_CLK_CPU_P

TP_CPU_SPARE7

TP_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6 TP_CPU_SPARE3 TP_CPU_SPARE0 TP_CPU_EXTBREF

PM_THRMTRIP_L CPU_THERMD_N CPU_THERMD_P CPU_PROCHOT_L XDP_DBRESET_L XDP_TRST_L XDP_TMS XDP_TDO XDP_TDI XDP_TCK XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<0>

FSB_CPURST_L FSB_LOCK_L CPU_INIT_L FSB_IERR_L FSB_BREQ0_L FSB_DRDY_L FSB_DEFER_L

TP_CPU_HFPLL

TP_CPU_A37_L TP_CPU_A38_L TP_CPU_A39_L

TP_CPU_A32_L TP_CPU_A33_L TP_CPU_A34_L TP_CPU_A35_L TP_CPU_A36_L

TP_CPU_APM0_L TP_CPU_APM1_L

CPU_SMI_L

CPU_INTR CPU_NMI CPU_STPCLK_L CPU_IGNNE_L CPU_FERR_L CPU_A20M_L FSB_ADSTB_L<1>

FSB_RS_L<2>

FSB_HIT_L FSB_HITM_L

Trang 8

OUTOUT

VSS_82VSS_83VSS_84VSS_85

VSS_87VSS_86

VSS_88VSS_89VSS_90

VSS_92VSS_91

VSS_93VSS_94VSS_95

VSS_97VSS_96

VSS_100VSS_98VSS_99

VSS_102VSS_101

VSS_105

VSS_103VSS_104

VSS_106VSS_107

VSS_110VSS_109VSS_108

VSS_111VSS_112

VSS_120VSS_119

VSS_124VSS_125

VSS_129VSS_130

VSS_133

VSS_131VSS_132

VSS_134VSS_135

VSS_143VSS_142

VSS_147VSS_148

VSS_152VSS_153

VSS_161VSS_160

VSS_162

VSS_1VSS_2VSS_3

VSS_5VSS_4

VSS_6VSS_7VSS_8

VSS_10VSS_9

VSS_11VSS_12

VSS_15VSS_13VSS_14

VSS_16VSS_17VSS_18VSS_19VSS_20

VSS_23VSS_22VSS_21

VSS_24VSS_25

VSS_28VSS_27VSS_26

VSS_29VSS_30

VSS_33VSS_32VSS_31

VSS_34VSS_35

VSS_38VSS_37VSS_36

VSS_46

VSS_44VSS_45

VSS_47VSS_48

VSS_51VSS_49VSS_50

VSS_52VSS_53

VSS_56VSS_54VSS_55

VSS_63VSS_62

VSS_64VSS_65VSS_66

VSS_69VSS_68VSS_67

VSS_70VSS_71

VSS_74VSS_73VSS_72

VSS_75VSS_76

VSS_79VSS_78VSS_77

VSS_80VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66VCC_65VCC_63VCC_62VCC_61VCC_59VCC_60VCC_58VCC_57VCC_56VCC_54VCC_55VCC_53

VCC_51VCC_52

VCC_49VCC_50VCC_48VCC_47VCC_46VCC_44VCC_45VCC_43

VCC_41VCC_42VCC_40VCC_39VCC_38VCC_36VCC_37

VCC_33

VCC_35VCC_34

VCC_31VCC_32

VCC_29VCC_30VCC_28

VCC_26VCC_27

VCC_23

VCC_25VCC_24VCC_22VCC_21VCC_20VCC_18VCC_19VCC_17VCC_16VCC_15

VCC_13VCC_14VCC_12

VCC_10VCC_11

VCC_8VCC_9VCC_7VCC_6VCC_5

VCC_3VCC_4VCC_2

VCC_69

VCC_71VCC_70

VCC_72

VCC_74

VCC_76VCC_75

VCC_78VCC_77

VCC_79

VCC_81VCC_80

VCC_84VCC_82VCC_83

VCC_86VCC_85

VCC_87

VCC_89VCC_88

VCC_90VCC_91VCC_92

VCC_94VCC_93

VCC_95VCC_96VCC_97

VCC_99VCC_98

VCC_100

VCCP_1VCCP_2VCCP_3VCCP_4VCCP_5VCCP_6VCCP_7

VCCP_9VCCP_8

VCCP_11VCCP_10

VCCP_12VCCP_13VCCP_14

VCCP_16VCCP_15

VCCA

VID0VID1VID2VID3VID4VID5VID6

VSSSENSEVCCSENSE

VCC_73

(3 OF 4)

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

(CPU CORE POWER)

(CPU IO POWER 1.05V)

STUB

LAYOUT NOTE:

VCCSENSE AND VSSSENSE LINES

SHOULD BE OF EQUAL LENGTH

LOCATION WHERE THE TWO 54.9 OHMBETWEEN VCCSENSE AND VSSSENSE AT THE

TO CONNECT A DIFFERENCTIAL PROBEPROVIDE A TEST POINT (WITH NO STUB)LAYOUT NOTE:

TO TP_VSSSENSE WITH NO

(CPU INTERNAL PLL POWER 1.5V)

ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING

402MF-LF100

R08021

2

CPU YONAH

AA5AA8AA11AA14AA16AA19AA22AA25AB1AB4B13

AB8AB11AB13AB16AB19AB23AB26AC3AC6AC8B16

AC11AC14AC16AC19AC21AC24AD2AD5AD8AD11B19

AD13AD16AD19AD22AD25AE1AE4AE8AE11AE14B21

AE16AE19AE23AE26AF3AF6AF8AF11AF13AF16B24

AF19AF21AF24

C5C8C11A8

C14C16C19C2C22C25D1D4D8D11A11

D13D16D19D23D26E3E6E8E11E14A14

E16E19E21E24F5F8F11F13F16F19A16

F2F22F25G4G1G23G26H3H6H21A19

H24J2J5J22J25K1K4K23K26L3A23

L6L21L24M2M5M22M25N1N4N23A26

N26P3

P6P21P24R2R5R22R25T1

T23T26U3U6U21U24V2V5V22

CPU YONAH

C10C12C13C15C17C18D9D10D12D14A10

D15D17D18E7E9E10E12E13E15E17A12

E18E20F7F9F10F12F14F15F17F18A13

F20AA7AA9AA10AA12AA13AA15AA17AA18AA20A15

AB9AC10AB10AB12AB14AB15AB17AB18

AB20AB7

A17

AC7AC9AC12AC13AC15AC17AC18AD7AD9AD10A18

AD12AD14AD15AD17AD18AE9AE10AE12AE13AE15A20

AE17AE18AE20AF9AF10AF12AF14AF15AF17AF18

B26

V6

N6R21R6T21T6V21W21

G21J6K6M6J21K21M21N21

AF7

AD6AF5AE5AF4AE3AF2AE2

AE7

SYNC_DATE=05/03/2005

1088

C051-7173

SYNC_MASTER=MASTER

CPU 2 OF 2-PWR/GND

=PPVCORE_S0_CPU

CPU_VCCSENSE_P CPU_VCCSENSE_N

Trang 9

INININININININ

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

# VCCLFM: VCORE AT LOWEST FREQUENCY MODE

(CPU INTERNAL PLL POWER 1.5V)

PLACE NEAR THE NORTH BRIDGE

TBD

# REFER TO YONAH PROCESSOR EMTS REV 1.0 WITH THE VID RANGE(VCORE VOLTAGE)!

1.1625

# ALL PROCESSOR DEFAULT VCORE FOR INITIAL POWER UP IS 1.2V

# VCCHFM: VCORE AT HIGHEST FREQUENCY MODE

VCCLFM

TBD

1.1625

VCCHFM VCCLFM TBD

VCCHFM VCCLFM

TBD VCCLFM

ON BOTTOM SIDE

CPU CORE VID<> SETTINGS

ON BOTTOM SIDE PLACE NEAR THE CPU

R0922

1/16W 5%

2 1

R0923

1/16W

2 1

R0924

5%

2 1

R0925

5%

2 1

MF-LF402 1/16W

5%

2 1

2

1

C0950

16VCERM

0.01uF10%

402

470UFCRITICAL

20%

2.5VD2T

C09401

23

470UF-8MOHMPOLY

CRITICAL

20%

2.5VD2T

C09411

23

NOSTUFF

470UF-8MOHMPOLY

23

470UF-8MOHMPOLY

20%

CRITICAL

D2T

C09431

23

470UF-8MOHMPOLY

CRITICAL

2.5V20%

D2T

C09441

23

470UF-8MOHMPOLY20%

2.5V

CRITICAL

D2T

C09461

23

C0911

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICALC0910

CRITICAL

CERM-X5R 1 2 805 6.3V 20%

22UF

C0908 C0901

CRITICAL

CERM-X5R 1 2 805 6.3V 20%

22UF

CRITICAL

CERM-X5R 1 2 805 6.3V 20%

CERM-X5R

CRITICALC0900

CRITICAL

CERM-X5R 1 2 805 6.3V 20%

CERM-X5R

CRITICALC0907

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICALC0929

C0924

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICAL

C0918CRITICAL

CERM-X5R 1 2 805 6.3V 20%

22UF C0913

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICAL

C0912CRITICAL

CERM-X5R 1 2 805 6.3V 20%

22UF C0904

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICAL

C0930CRITICAL

CERM-X5R 1 2 805 6.3V 20%

22UF C0902

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICAL

C0931CRITICAL

CERM-X5R 1 2 805 6.3V 20%

22UF C0939

22UF

20%

6.3V 805 2 1

CERM-X5R

CRITICAL

CERM-X5R 1 2 805 6.3V 20%

402 10V

CERM 20%

402 10V

0.1UF

20%

CERM 402

C0938

1 2

2 1

Trang 10

THM2*

IOIO

INOUT

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

CPU ZONE THERMAL SENSOR

ROUTE CPU_THERMD_P AND

10 MIL TRACELAYER

5

32

6

U1001ADT7461

MSOP

CRITICAL

21

R1001

1%

4021/16W

402

2

1C1002

40210%

0.1UF

X5R

21

R1002

1/16W402MF-LF1%

10K

CPU MISC1-TEMP SENSOR

SYNC_DATE=08/19/2005SYNC_MASTER=ENET

10810

C051-7173

THRM_CPU_DX_PTHRM_CPU_DX_NCPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_THRM_SNR

THRM_ALERT_LTHRM_ALERT

SMB_THRM_CLKSMB_THRM_DATA

Trang 11

OUTIOIOIO

IOIOIO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

ITP TCK SIGNAL LAYOUT NOTE:

CONNECTOR’S FBO PIN.

(AND WITH RESET BUTTON)

NCNC

516S0416

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM

(DBA#)(DEBUG PORT ACTIVE)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC(DBR#)

(DEBUG PORT RESET)(TCK)

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

(FBO)(FROM CK410M HOST 133/167MHZ)

CPU ITP700FLEX DEBUG SUPPORT

21R1100

ITP

4021/16W1%

MF-LF22.6

ITP

4021%

1/16W

122.62R11022

1R1103MF-LF4021%

1/16W54.9

40216V0.1UF1

2

ITP

C11001/16W

240402MF-LF5%

1

2R1104

2

1R1101MF-LF1%

4021/16W54.9

2

MF-LF5%

402680

SM1

CRITICALF-ST-5047

SYNC_MASTER=MASTER

10811

C051-7173

SYNC_DATE=5/23/05

CPU ITP700FLEX DEBUG

XDP_DBRESET_L

CPU_XDP_CLK_N CPU_XDP_CLK_P XDP_BPM_L<3>

=PP1V05_S0_CPU

XDP_TDI XDP_TCK

XDP_BPM_L<1>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK XDP_TMS

Trang 12

IOIO

OUTOUT

OUTIOIOIOIOIOIO

IOIOIOIOIOIOIO

IOIOIOIOIOIOIOIO

OUTIO

OUTOUTOUTOUT

IOIOIOIOIO

HYRCOMPHYSCOMP

HXSWINGHXSCOMPHXRCOMP

IO

IOIOIOIOIO

IOIOIO

IOIOIOIO

IOIOIOIOIOIOIOIO

IO

IOIOIOIOIOIOIOIO

IOIO

IO

IOIOIOIOIOIO

IOIOIOIO

IO

IOIOIOIO

IOIOIOIOIOIO

IO

IOIO

IOIOIOIOIOIOIO

IO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

0.1uF

10%

X5R

C12111 2 402 MF-LF 1%

200R1211

1 2

402 MF-LF 1%

100R1210

1 2

402 MF-LF 1%

54.9R12201 2

24.9

1%

1/16W 402

R12211 2

402 MF-LF 1%

221R1225

1 2

100

402 MF-LF 1%

R1226

1 2

10%

X5R

0.1uFC1226

1 2

402 MF-LF 1%

221R1235

1

2 402 MF-LF 1%

54.9R12301 2

100

402 MF-LF 1%

R1236

1 2

24.9

1%

1/16W 402

R12311 2

945GM NB

LEMENU

BGA

U1200

H11J12G14D9J14H13J15F14D12A11C11A12A13E13G13F12B12B14C12A14H9

C14D14

C9E11G11F11G12F9

E8B9C13J13C6F6C7

AG2AG1

B7

F1J1

K7J8H4J3K11G4T10W11T3U7H1

U9U11T11W9T1T8T4W7U5T9J6

W6T5AB7AA9W4W3Y3Y7W5Y10H3

AB8W2AA4AA7AA2AA6AA10Y8AA1AB4K2

AC9AB11AC11AB3AC2AD1AD9AC1AD7AC6G1

AB5AD10AD4AC8

G2K9K1

A7C3

J7W8U3AB10

J9H8

K4T7Y5AC4K3T6AA5AC5K13

D3D4B3D8G8B8F8A8B4E6D6E3E7

E1E2E4Y1U1W1

051-7173

10812

C

NB CPU Interface

SYNC_DATE=07/25/2005SYNC_MASTER=NB

NB_FSB_XSCOMPNB_FSB_XSWING

NB_FSB_YSCOMPNB_FSB_YRCOMP

NB_FSB_YSWINGFSB_CLK_NB_PFSB_CLK_NB_N

FSB_BNR_LFSB_BPRI_LFSB_BREQ0_LFSB_CPURST_LFSB_DBSY_LFSB_DEFER_LFSB_DPWR_LFSB_DRDY_L

FSB_RS_L<0>

FSB_RS_L<1>

FSB_SLPCPU_LFSB_TRDY_L

Trang 13

CRT_VSYNCCRT_IREF

TV_IRTNCTV_IRTNBTV_IREFTV_IRTNA

TV_DACB_OUTTV_DACC_OUTTV_DACA_OUTLB_DATA2LB_DATA1LB_DATA0LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2LA_DATA1LA_DATA0LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLKLB_CLK*

LA_CLKLA_CLK*

L_VDDEN

L_VREFLL_VREFHL_VBGL_IBGL_DDC_CLKL_DDC_DATA

EXP_A_COMPIEXP_A_COMPOEXP_A_RXN0EXP_A_RXN1EXP_A_RXN2EXP_A_RXN3EXP_A_RXN4EXP_A_RXN5EXP_A_RXN6EXP_A_RXN7EXP_A_RXN8EXP_A_RXN9EXP_A_RXN10EXP_A_RXN11EXP_A_RXN12EXP_A_RXN13

EXP_A_RXN15EXP_A_RXN14

EXP_A_RXP0EXP_A_RXP1EXP_A_RXP2

EXP_A_RXP4EXP_A_RXP3

EXP_A_RXP15

EXP_A_TXN1EXP_A_TXN0

EXP_A_TXN6EXP_A_TXN5EXP_A_TXN4

EXP_A_TXN7EXP_A_TXN8EXP_A_TXN9EXP_A_TXN10EXP_A_TXN11EXP_A_TXN12

EXP_A_TXN15EXP_A_TXP0

EXP_A_TXP2EXP_A_TXP1

EXP_A_TXP3EXP_A_TXP4EXP_A_TXP5

L_CLKCTLBL_BKLTENL_CLKCTLAL_BKLTCTL

IN

OUTOUTOUTOUT

ININ

OUTOUTOUTOUT

IN

OUTOUT

IO

ININININ

INININ

INININININININININININ

IN

INININ

OUT

OUTOUT

OUT

IN

OUT

OUTOUT

OUT

IN

OUT

OUTOUT

OUT

IN

OUT

OUTOUT

OUT

OUTOUTOUTOUT

IN

IOIO

OUTOUTOUTOUTOUTOUT

IN

OUT

OUTOUTOUTOUTOUTOUT

OUTOUTOUT

IN

OUTOUTOUT

IOIO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

SDVOB_GREENSDVOB_RED

SDVOC_CLKNSDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKNSDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKPSDVOB_BLUE

SDVOC_REDSDVOC_GREENSDVOC_BLUESDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail

VCCA_TVBG to 1.5V power rail Tie VSSA_TVBG to GND

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, andconnect to GND through 75-ohm resistors

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:

Composite: DACA only

C26C25

C22B22

J22

A21B21

H23

D40D38F34G38

V34W38Y34AA38AB34AC38

H34J38L34M38N34P38R34T38

D34F38

T34V38W34Y38AA34AB38

G34H38J34L38M34N38P34R38

F36G40

V36W40Y36AA40AB36AC40

H36J40L36M40N36P40R36T40

D36F40

T36V40W36Y40AA36AB40

G36H40J36L40M36N40P36R40G23

D32J30H30H29G26G25B38C35F32C33C32

A32A33

B37C37

B34B35

A36A37

E26E27

F30G30

D29D30

F28F29

A16C18A19J20B16B18B19

BGA

NB 945GM

U1200

24.9

1%

1/16W 402

R1310

1 2

NB PEG / Video Interfaces

C051-7173

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<15>

CRT_BLUE_LCRT_BLUE

CRT_GREEN_LCRT_GREEN

CRT_RED

CRT_DDC_CLKCRT_RED_L

LVDS_VDDEN

LVDS_VREFLLVDS_VREFHTP_LVDS_VBGLVDS_IBG

LVDS_DDC_CLKLVDS_DDC_DATA

Trang 14

RSVD15RSVD14

SM_CKE2

RSVD2RSVD3

RSVD6RSVD4RSVD5

RSVD8RSVD7

RSVD9RSVD1

RSVD10RSVD11RSVD12RSVD13

CFG1CFG0

CFG2CFG3CFG4

CFG6CFG5

CFG7CFG8CFG9CFG10CFG11CFG12CFG13CFG14

CFG17CFG16CFG15

CFG18CFG19CFG20PM_BM_BUSY*

PM_EXTTS0*

PM_EXTTS1*

PW_THRMTRIP*

PWROKRSTIN*

SDVO_CTRLCLKSDVO_CTRLDATAICH_SYNC*

CLK_REQ*

NC2NC3NC4NC5NC6NC7NC8NC9

NC0NC1

NC13NC12NC11NC10

NC18NC17NC16NC15NC14

SM_CK0SM_CK1SM_CK2

SM_ODT1SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMPSMVREF0SMVREF1G_CLKIN*

G_CLKIND_REFCLKIN*

D_REFCLKIND_REFSSCLKIN*

D_REFSSCLKINDMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3DMI_TXP0

DMI_TXP2DMI_TXP1

IN

IOIOOUTOUT

OUT

OUTOUTOUT

OUT

OUTOUTOUT

OUTOUT

OUTOUTOUT

OUTOUTOUTOUT

IN

ININININININININININININININ

OUT

OUTOUTOUT

OUTOUTOUTOUT

INININ

INININININININININININININININ

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

(LA_DATAP3)(LB_DATAN3)(LB_DATAP3)(LA_DATAN3)

(H_EDRDY#)(D_PLLMON1)

(H_PROCHOT#)(TESTIN#)(TV_DCONSEL0)(TV_DCONSEL1)

(H_PLLMON1)(H_PLLMON1#)(H_PCREQ#)

(VSS_MCHDETECT)

NCNC

NC

NCNC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

IPU

IPDIPDIPDIPU

IPU

IPUIPUIPUIPUIPUIPUIPUIPUIPUIPU

NCNC

IPUIPU

NC

LEMENU

945GM NB

BGA

U1200

K16K18

E16D15G15K15C15H16G18H15J25K27J18

J26

F18E15F15E18D19D16G16

H32

A26A27

D41C40

AE35AF39AG35AH39AC35AE39AF35AG39AE37AF41AG37AH41AC37AE41AF37AG41

AG33AF33

K28

D1C41

B2AY41AY1AW41AW1A40A4A39A3

C1BA41BA40BA39BA3BA2BA1B41

G28F25H26G6AH33AH34

T32

J29A41A35A34D28D27

R32F3F7AG11AF11H7J19K30

H28H27

AY35

AW35AR1

AT1AW7

AY7AW40

AY40AU20AT20BA29AY29AW13AW12AY21AW21

BA13BA12AY20AU21

AL20AF10

AT9AV9

AK1AK41

100

402 MF-LF 5%

R1430

1 2

1/16W 5%

402

10KR1441

1 2 MF-LF 5%

402

10KR14401 2

20%

CERM 402

0.1uFC1416

1 2 20%

CERM 402

0.1uFC14151 2

MF-LF5%

SYNC_MASTER=NB SYNC_DATE=08/15/2005

NB Misc Interfaces

TP_NB_XOR_FSB2_H7

TP_NB_XOR_LVDS_D27TP_NB_XOR_LVDS_D28TP_NB_XOR_LVDS_A34

MEM_VREF_NB_1MEM_VREF_NB_0MEM_RCOMP

SDVO_CTRLCLKSDVO_CTRLDATANB_SB_SYNC_L

CLK_NB_OE_L

TP_NB_TESTIN_L

TP_NB_XOR_LVDS_A35NB_TV_DCONSEL0

=PP3V3_S0_NB

NB_RST_IN_L

PM_DPRSLPVR_RPM_EXTTS_L<0>

Trang 15

SA_DQ2SA_DQ3SA_DQ4SA_DQ5SA_DQ6SA_DQ7SA_DQ8SA_DQ9SA_DQ10

SA_DQ12SA_DQ11

SA_DQ13SA_DQ14SA_DQ15SA_DQ16SA_DQ17SA_DQ18SA_DQ19SA_DQ20SA_DQ21SA_DQ22SA_DQ23SA_DQ24SA_DQ25SA_DQ26SA_DQ27

SA_DQ29SA_DQ28

SA_DQ30SA_DQ31SA_DQ32SA_DQ33

SA_DQ35SA_DQ34

SA_DQ36SA_DQ37SA_DQ38SA_DQ39SA_DQ40SA_DQ41SA_DQ42SA_DQ43SA_DQ44

SA_DQ46SA_DQ45

SA_DQ47SA_DQ48SA_DQ49SA_DQ50SA_DQ51SA_DQ52SA_DQ53SA_DQ54SA_DQ55SA_DQ56SA_DQ57SA_DQ58SA_DQ59SA_DQ60SA_DQ61SA_DQ62SA_DQ63

SA_BS1SA_BS0

SA_BS2SA_CAS*

SA_DM0SA_DM1SA_DM2SA_DM3

SA_DM5SA_DM4

SA_DM7SA_DM6

SA_DQS0

SA_DQS2SA_DQS1

SA_DQS3

SA_DQS5SA_DQS4

SA_DQS6SA_DQS7

SA_MA2SA_MA3

SA_MA5SA_MA4

SA_MA6SA_MA7

SA_MA9SA_MA8

SA_MA10SA_MA11SA_MA12SA_MA13

OUTOUTOUTOUTOUT

IO

OUTOUT

IOIOIOIO

IOIOIOIOIO

IOIOIOIO

IO

IOIOIOIOIOIOIOIOIOIO

IO

IOIOIOIOIO

IOIOIOIO

IO

IOIO

SB_DQ1SB_DQ0

SB_DQ2SB_DQ3SB_DQ4SB_DQ5SB_DQ6SB_DQ7SB_DQ8SB_DQ9SB_DQ10

SB_DQ12SB_DQ11

SB_DQ13SB_DQ14SB_DQ15SB_DQ16SB_DQ17SB_DQ18SB_DQ19SB_DQ20SB_DQ21SB_DQ22SB_DQ23SB_DQ24SB_DQ25SB_DQ26SB_DQ27

SB_DQ29SB_DQ28

SB_DQ30SB_DQ31SB_DQ32SB_DQ33

SB_DQ35SB_DQ34

SB_DQ36SB_DQ37SB_DQ38SB_DQ39SB_DQ40SB_DQ41SB_DQ42SB_DQ43SB_DQ44

SB_DQ46SB_DQ45

SB_DQ47SB_DQ48SB_DQ49SB_DQ50SB_DQ51SB_DQ52SB_DQ53SB_DQ54SB_DQ55SB_DQ56SB_DQ57SB_DQ58SB_DQ59SB_DQ60SB_DQ61SB_DQ62SB_DQ63

SB_BS1SB_BS0

SB_BS2SB_CAS*

SB_DM0SB_DM1SB_DM2SB_DM3

SB_DM5SB_DM4

SB_DM7SB_DM6

SB_DQS0

SB_DQS2SB_DQS1

SB_DQS3

SB_DQS5SB_DQS4

SB_DQS6SB_DQS7

SB_MA2SB_MA3

SB_MA5SB_MA4

SB_MA6SB_MA7

SB_MA9SB_MA8

SB_MA10SB_MA11SB_MA12SB_MA13

IOIO

IO

IOIOIOIO

IOIOIO

OUTOUTOUT

IO

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

IO

OUTOUTOUTIOIO

IOIOIOIOIO

IO

IOIOIO

IOIOIOIOIO

OUTIO

IO

OUTOUT

OUTOUTOUTOUTOUTOUTOUTOUT

IO

OUT

IOIOIOIOIOIOIOIO

IO

IOIOIOIOIOIOIO

OUTOUTOUT

IO

OUTOUT

OUT

OUTOUTOUTOUT

IO

OUTOUTOUTOUTOUTOUTOUTOUT

OUTIO

IO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

NC

AY14AK24AK23AW14

AT16AW17AU17AV17AU16BA17BA16AW16

AV12AV20AT17AU13

AU14AY16AH5AG5

AN3AP3

AL8AN8

AM12AN12

AM21AM22

AN27AN28

AU33AT33

AK32

AK33

AP33AN35AH31

AF8AF4AH6AG9AJ32

AF6AG4AF9AG7AL2AN1AT3AV2AN2AP1AK35

AW2AY2AL5AT5AN9AP9AK7AK8AN7AK9AJ36

AL12AL14AT12AT13AP12AP13AR14AR12AT21AP20AM33

AP24AL23AN20AP21AL22AP23AP26AM24AL28AK28AM31

AN24AM26AL27AK26AN33AM34AM36AN38AP31AR31

AJ34AJ35

AH4AR3AL9AM14AN22AL26AM35AJ33AY13BA20AV14AU12U1200

AK39AJ37

AU38AV38AP38AR40AW38AY38BA38AV36AR36AP36AP39

BA36AU36AP35AP34AY33BA33AT31AU29AU31AW31AR41

AV29AW29AM19AL19AP14AN14AN17AM16AP15AL15AJ38

AJ11AH10AJ9AN10AK13AH11AK10AJ8BA10AW10AK38

BA4AW4AY10AY9AW5AY5AV4AR5AK4AK3AN41

AT4AK5AJ5AJ3

AP41AT40AV41

AM39

AM40AT39

AU39AU35

AT35AR29

AP29AR16

AP16AR10

AT10AR7

AT7AN5

AP5AY23AW24

AV24BA27AY27AR23

AY24AR28AT27AT28AU27AV28AV27AW27

AU23AK16AR27AK18

NB DDR2 Interfaces

10815

Trang 16

VCC_50 VCC_51

VCC_46 VCC_47 VCC_48VCC_44 VCC_45

VCCAUX_NCTF46

VCCAUX_NCTF40VCCAUX_NCTF39VCCAUX_NCTF37VCCAUX_NCTF38VCCAUX_NCTF36VCCAUX_NCTF34VCCAUX_NCTF35

VCCAUX_NCTF32VCCAUX_NCTF33VCCAUX_NCTF31VCCAUX_NCTF30VCCAUX_NCTF29VCCAUX_NCTF27VCCAUX_NCTF28VCCAUX_NCTF26VCCAUX_NCTF24VCCAUX_NCTF25VCCAUX_NCTF22VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42VCCAUX_NCTF43VCCAUX_NCTF41

VCCAUX_NCTF19VCCAUX_NCTF20VCCAUX_NCTF18VCCAUX_NCTF17VCCAUX_NCTF16VCCAUX_NCTF14VCCAUX_NCTF15VCCAUX_NCTF13VCCAUX_NCTF12VCCAUX_NCTF11VCCAUX_NCTF9VCCAUX_NCTF10VCCAUX_NCTF8VCCAUX_NCTF7VCCAUX_NCTF6VCCAUX_NCTF5VCCAUX_NCTF4VCCAUX_NCTF3VCCAUX_NCTF1VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12VSS_NCTF11VSS_NCTF10VSS_NCTF9VSS_NCTF7VSS_NCTF8

VSS_NCTF5VSS_NCTF6VSS_NCTF4VSS_NCTF2VSS_NCTF3

VSS_NCTF0VSS_NCTF1

VCC_NCTF72VCC_NCTF71VCC_NCTF70VCC_NCTF69VCC_NCTF68VCC_NCTF67VCC_NCTF66VCC_NCTF65VCC_NCTF64

VCC_NCTF61VCC_NCTF62VCC_NCTF63VCC_NCTF60

VCC_NCTF57VCC_NCTF58VCC_NCTF59

VCC_NCTF56VCC_NCTF55VCC_NCTF53VCC_NCTF54VCC_NCTF52VCC_NCTF50VCC_NCTF51VCC_NCTF49VCC_NCTF48

VCC_NCTF46VCC_NCTF47VCC_NCTF45VCC_NCTF44VCC_NCTF43VCC_NCTF41VCC_NCTF40

VCC_NCTF42

VCC_NCTF38VCC_NCTF39

VCC_NCTF36VCC_NCTF37

VCC_NCTF34VCC_NCTF35VCC_NCTF33VCC_NCTF31VCC_NCTF32VCC_NCTF30VCC_NCTF29VCC_NCTF28VCC_NCTF27VCC_NCTF26VCC_NCTF25VCC_NCTF24VCC_NCTF23VCC_NCTF22VCC_NCTF21VCC_NCTF20VCC_NCTF18VCC_NCTF19VCC_NCTF17VCC_NCTF16VCC_NCTF15VCC_NCTF13VCC_NCTF14

VCC_NCTF11VCC_NCTF12VCC_NCTF10

VCC_NCTF8VCC_NCTF9VCC_NCTF7VCC_NCTF6VCC_NCTF5VCC_NCTF4VCC_NCTF3VCC_NCTF2VCC_NCTF0VCC_NCTF1

(7 OF 10)

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

NCTF balls are Not Critical To FunctionThese connections can break withoutimpacting part performance

Layout Note:

Place near pin BA23

Place near pin BA15Layout Note:

AU40 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27

AM41 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1

C1610

1 2

0.47UF

10%

603 20%

X5R 6.3V

10uFC1621

1 2 2

1

C1620

603 20%

X5R 6.3V

10uF

AE18AE19AE20AE21AE22AE23AE24AE25

U17Y17AC17

AE26AE27

AF23AG23AF24AG24

R15T15U15V15W15Y15AA15AB15AF25

AC15AD15AE15AF15AG15R16T16U16V16W16AG25

Y16AA16AB16AC16AD16AE16AF16AG16R17T17AF26

V17W17AA17AB17AD17AE17AF17AG17R18AF18AG26

AG18R19AF19AG19AF20AG20AF21AG21AF22AG22

AF27AG27

R27T27

T18U18V18U27

W18Y18AA18AB18AC18AD18T19U19V19AD19V27

R20T20U20V20AD20R21T21U21V21AD21W27

R22T22U22V22AD22R23T23U23V23AD23Y27

R24T24U24V24W24Y24AA24AB24AC24AD24AA27

R25T25U25V25W25Y25AA25AB25AC25AD25AB27

R26T26U26V26W26Y26AA26AB26AC26AD26

AC27AD27

U1200

BGA

NB 945GM

LEMENU

402 6.3V CERM-X5R

C1611

1 2

0.47UF

10%

402 6.3V CERM-X5R

C16121 2

0.47UF

10%

402 6.3V CERM-X5R

C1613

1 2

0.47UF

10%

402 6.3V CERM-X5R

C16141 2

0.47UF

10%

402 6.3V CERM-X5R

C1615

1 2

0.47UF

10%

C051-7173

Trang 17

VTT15VTT14

VTT16

VTT18VTT17

VTT19VTT20VTT21VTT22VTT23VTT24VTT25

VTT27VTT26

VTT28VTT29

VTT31VTT30

VTT32

VTT34VTT33

VTT35VTT36VTT37

VTT39VTT38

VTT40VTT41VTT42VTT43VTT44VTT45

VTT48VTT46VTT47

VTT49VTT50

VTT52VTT51

VTT53

VTT55VTT54

VTT57VTT56

VTT58VTT59VTT60VTT61VTT62

VTT64VTT63

VTT65VTT66VTT67

VTT69VTT68

VTT70VTT71

VTT73VTT72

VTT74

VTT76VTT75

VCCSYNCVCC_TXLVDS0VCC_TXLVDS1VCC_TXLVDS2VCC3G0VCC3G1

VCC3G3VCC3G2

VCC3G4

VCC3G6VCC3G5

VCCA_3GPLLVCCA_3GBGVSSA_3GBGVCCA_CRTDAC0VCCA_CRTDAC1VSSA_CRTDAC

VCCA_DPLLBVCCA_DPLLA

VCCA_HPLL

VSSA_LVDSVCCA_LVDS

VCCA_MPLLVCCA_TVBGVSSA_TVBGVCCA_TVDACC0VCCA_TVDACC1VCCA_TVDACB0VCCA_TVDACB1VCCA_TVDACA0VCCA_TVDACA1VCCD_HMPLL0VCCD_HMPLL1

VCCD_LVDS2VCCD_LVDS0VCCD_LVDS1

VCCD_TVDAC

VCC_HV1VCC_HV2VCC_HV0

VCCD_QTVDAC

VCCAUX19VCCAUX18VCCAUX17VCCAUX16VCCAUX14VCCAUX15VCCAUX13VCCAUX12VCCAUX11VCCAUX10

VCCAUX0VCCAUX1VCCAUX2VCCAUX3VCCAUX4

VCCAUX6VCCAUX5

VCCAUX9VCCAUX8VCCAUX7

VCCAUX21VCCAUX20

VCCAUX25VCCAUX26

VCCAUX30VCCAUX31

VCCAUX33VCCAUX32

VCCAUX38VCCAUX37

VCCAUX39VCCAUX40

(8 OF 10)

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

LEMENU

U1200

AJ41AB41Y41V41R41N41L41

A23B23B25

C30B30A30

G41AC33

F21E21

B26C39AF1A38

AF2H20

E19F19

C20D20

E20F20

AK31AF31

AE30AD30AC30AG29AF29AE29AD29AC29AG28AF28AE31

AE28AH22AJ21AH21AJ20AH20AH19P19P16AH15AC31

P15AH14AG14AF14AE14Y14AF13AE13AF12AE12AL30

AD12

AK30AJ30AH30AG30AF30

AH1AH2A28B28C28

H19D21

AD13AC13AB13AA13Y13W13V13U13T13R13W14

N13M13L13AB12AA12Y12W12V12U12T12V14

R12P12N12M12L12R11P11N11M11R10T14

P10N10M10P9N9M9R8P8N8M8R14

P7N7M7R6P6M6A6P5N5P14

M5P4N4M4R3P3N3M3R2P2N14

M2D2AB1R1P1N1M1

M14L14

6.3V 20%

0.22UF

402

C1712

1 2

NB Power 2

10817

GND_NB_VSSA_CRTDAC

PP1V5_S0_NB_VCCA_DPLLBPP1V5_S0_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_HPLL

GND_NB_VSSA_LVDS

=PP2V5_S0_NB_VCCA_LVDS

PP3V3_S0_NB_VCCA_TVBGGND_NB_VSSA_TVBGPP3V3_S0_NB_VCCA_TVDACC

Trang 18

VSS_2VSS_3VSS_4VSS_5VSS_6VSS_7

VSS_9VSS_8

VSS_10VSS_11VSS_12VSS_13VSS_14VSS_15VSS_16VSS_17

VSS_19VSS_18

VSS_20VSS_21VSS_22VSS_23VSS_24VSS_25VSS_26

VSS_28VSS_27

VSS_37VSS_36

VSS_39VSS_38

VSS_49VSS_48

VSS_57VSS_56

VSS_59VSS_58

VSS_61VSS_60

VSS_64VSS_63VSS_62

VSS_73VSS_72

VSS_82VSS_80VSS_81

VSS_84VSS_83

VSS_85

VSS_87VSS_86

VSS_89VSS_88

VSS_91VSS_90

VSS_92VSS_93VSS_94

VSS_96VSS_95

VSS_97VSS_98VSS_99VSS_100VSS_101VSS_102VSS_103VSS_104VSS_105VSS_106VSS_107VSS_108VSS_109VSS_110VSS_111VSS_112

VSS_114VSS_113

VSS_115

VSS_117VSS_116

VSS_127VSS_126

VSS_137VSS_136

VSS_143VSS_142

VSS_144VSS_145VSS_146VSS_147VSS_148VSS_149VSS_150VSS_151VSS_152VSS_153VSS_154VSS_155VSS_156

VSS_158VSS_157

VSS_164VSS_163

VSS_172VSS_171

VSS

(9 OF 10)

VSS_272VSS_271VSS_269VSS_270VSS_268VSS_266VSS_267VSS_265VSS_264VSS_263VSS_261VSS_262VSS_260VSS_259VSS_258

VSS_256VSS_257VSS_255VSS_254VSS_253VSS_251VSS_252VSS_250VSS_248VSS_249VSS_247VSS_246VSS_245

VSS_243VSS_244VSS_242VSS_241VSS_240VSS_238VSS_239VSS_237VSS_236VSS_235VSS_233VSS_234VSS_232VSS_231VSS_230VSS_228VSS_229VSS_227VSS_225VSS_226VSS_224VSS_223VSS_222

VSS_220VSS_221VSS_219VSS_218VSS_217VSS_215VSS_216VSS_214VSS_213VSS_212

VSS_207VSS_208

VSS_205VSS_206VSS_204VSS_202VSS_203VSS_201VSS_200VSS_199VSS_197VSS_198VSS_196VSS_195VSS_194VSS_192VSS_193VSS_191VSS_190VSS_189VSS_187VSS_188VSS_186

VSS_273VSS_274

VSS_276VSS_275

VSS_277

VSS_279VSS_278

VSS_281VSS_280

VSS_286VSS_285

VSS_291VSS_290

VSS_293VSS_292

VSS_294

VSS_296VSS_295

VSS_297

VSS_299VSS_298

VSS_304VSS_303

VSS_309VSS_308

VSS_311VSS_310

VSS_317VSS_316

VSS_322VSS_321

VSS_327VSS_326

VSS_332VSS_331

VSS_334VSS_333

VSS_335

VSS_337VSS_336

VSS_345VSS_344

VSS_350VSS_349

VSS_352VSS_351

VSS

(10 OF 10)

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

NB 945GM

LEMENU

BGA

U1200AC41

AA41

AN40

AE34AC34C34AW33AV33AR33AE33AB33Y33V33AK40

T33R33M33H33G33F33D33B33AH32AG32AJ40

AF32AE32AC32AB32G32B32AY31AV31AN31AJ31AH40

AG31AB31Y31AB30E30AT29AN29AB29T29N29AG40

K29G29E29C29B29A29BA28AW28AU28AP28AF40

AM28AD28AC28W28J28E28AP27AM27AK27J27AE40

G27F27C27B27AN26M26K26F26D26AK25B40

P25K25H25E25D25A25BA24AU24AL24AW23

AY39AW39W41

AV39AR39AN39AJ39AC39AB39AA39Y39W39V39T41

T39R39P39N39M39L39J39H39G39F39P41

D39AT38AM38AH38AG38AF38AE38C38AK37AH37M41

AB37AA37Y37W37V37T37R37P37N37M37J41

L37J37H37G37F37D37AY36AW36AN36AH36F41

AG36AF36AE36AC36C36B36BA35AV35AR35AH35AV40

AB35AA35Y35W35V35T35R35P35N35M35AP40

L35J35H35G35F35D35AN34

AK34AG34AF34

NB 945GM

LEMENU

BGA

U1200AT23

AN23AM23AH23AC23W23K23J23F23C23AA22K22G22F22E22D22A22BA21AV21AR21AN21AL21AB21Y21P21K21J21H21C21AW20AR20AM20AA20K20B20A20AN19AC19W19K19G19C19AH18P18H18D18A18AY17AR17AP17AM17AK17AV16AN16AL16J16F16C16AN15AM15AK15N15M15L15B15A15BA14AT14AK14AD14AA14U14K14H14E14AV13AR13AN13AM13AL13AG13P13F13D13B13AY12AC12K12H12E12AD11AA11Y11

J11D11B11AV10AP10AL10AJ10AG10AC10W10U10BA9AW9AR9AH9AB9Y9R9G9E9A9AG8AD8AA8U8K8C8BA7AV7AP7AL7AJ7AH7AF7AC7R7G7D7AG6AD6AB6Y6U6N6K6H6B6AV5AF5AD5AY4AR4AP4AL4AJ4Y4U4R4J4F4C4AY3AW3AV3AL3AH3AG3AF3AD3AC3AA3G3AT2AR2AP2AK2AJ2AD2AB2Y2U2T2N2J2H2F2C2AL1

NB Grounds

10818

Trang 19

NC

NOISEGND

VOUTCONTVIN

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

within 6.35 mm of NB edge

(MCH CRTDAC ANALOG 2.5V PWR)MCH VCCA_CRTDAC BYPASS

THESE 4 0.1UF CAPS SHOULD

These 4 caps should bewithin 6.35 mm of NB edge

PLACE THOSE COMPONENT CLOSE TO GMCH

GMCH VCCA_MPLL FILTER

Place on the edge

(SHARE C0940 470UF)

(MCH TV OUT CHANNEL C 3.3V PWR) MCH VCCA_TVDACC FILTER

within 6.35 mm of NB edgeThese 8 caps should be

1uH, 20%

945 EDS: 1210?

on opposite side

be close to MCH10uF caps shouldLayout Note:

GMCH VCCD_QTVDAC FILTERMCH VCC_HV BYPASS

Layout Note:

(PCI-E/DMI ANALOG 1.5V PWR)

be within 5 mm of NB edgeThis 0.1uF cap should

Layout Note: Route to caps, then GND

0.1uF

C197210uF

20%

6.3V 2 1 X5R

CRITICALC1970

POLY 2 1 SMB2

220UF

20%

2.5V

2 1 402 20%

0.22uFC1967

6.3V X5R

C19662.2uF

603 2 1 6.3V CERM1 20%

603

4.7uFC1965

2 1 20%

CERM 2

1C191010uF

20%

6.3V X5R

2

1C1913

10V CERM 402 20%

0.1uF

402

2

1R1950 01/16W5%

MF-LF

402

2

1R1951 0MF-LF5%

1/16W

2

1C195210uF

X5R 6.3V 603

470UF

541

23

U1900SOT23-5

603

2 1 CERM 16V

402 10V

2 402 CERM 16V 1

0.01uFC1941

5

D1986SOT-363BAT54DW

2

1C1916

402 10V

1/16W2

1

R19861K

MF-LF4021%

2

1

R1987

1/16W1%

402MF-LF

1K

2

R1989

MF-LF1%

6.3V402

2

1UF10%

6.3V402

2

1UF10%

6.3V402

2

1C1940

CERM40210%

6.3V1UF

51

4

23SOT23-5-LFU1901 MM157

CRITICAL

L1970

91nH21

1210

CRITICAL

C1936CRITICAL

CERM-X5R 6.3V20%

805 2

0.1uF

2 1

L1922180-OHM-1.5A

0603

C1906

2 1 20%

6.3V X5R

0.22uF

3 1 2

C192322000pF-1000mA

16VNFM18

3 1 2

C1921

NFM1816V

22000pF-1000mA

2

1

C19220.1uF

10V 402 20%

CERM

2

1C19150.1uF

20%

402 10V CERM 2

402 2 1 6.3V X5R 20%

0.22uFC1905

2

1C1935

20%

CERM 402

0.1uF

2 1

L1934FERR-120-OHM-0.2A

0603

C1937

402 CERM 10V 2 1 20%

0.1uF

FERR-120-OHM-0.2AL1936

2 1

10uF

603

3 1 2

C199222000pF-1000mA

16VNFM18

2

1

C19910.1uF

10V CERM 402 20%

2 1

L1990180-OHM-1.5A

0603

2

1C1990

603 20%

6.3V

10uF

3 1 2

C1994

NFM1816V

0.1uF

402

3 1 2

C1996

NFM1816V

22000pF-1000mA

2

1C1902

X5R 6.3V 20%

0.1uF

3 1 2

10V 402 CERM

0.1uF

CERM 2

1C1918

20%

402 10V

3 1 2

C1986

NFM1816V

22000pF-1000mA

2

1

C19850.1uF

10V 402 CERM

2 1

L1985

0603

180-OHM-1.5A

2 1

R1985

1%

10

1/16W 402 MF-LF

2 1

R1990

402 1/16W 1%

10

MF-LF

2

1C19170.1uF

CERM 20%

402

2 1 10%

402 CERM

C19810.01uF

2

1C1980

10V CERM 402 20%

2 1

L19751.0UH-220MA-0.12-OHM

10uF

1/16W 2 1

R19750.51

603

SYNC_DATE=06/22/2005

10819

MIN_NECK_WIDTH=1.0 mmVOLTAGE=1.5V

PP1V5_S0_NB_VCCA_DPLLA

=PP5V_S0_NB_TVDAC

PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5VMIN_NECK_WIDTH=1.0 mm

PP1V5_S0_NB_3GPLL_F

MIN_LINE_WIDTH=1.0 mmVOLTAGE=1.5VMIN_NECK_WIDTH=1.0 mm

PP1V5_S0_NB_QTVDAC

MIN_LINE_WIDTH=1.0 mmVOLTAGE=2.5VMIN_NECK_WIDTH=1.0 mm

PP2V5_S0_NB_CRTDAC_FOLLOW

PP3V3_S0_NB_TVDAC_FOLLOW

VOLTAGE=3.3VMIN_LINE_WIDTH=1.0 mm

PP1V5_S0_DPLL

=PP1V5_S0_NB_3GPLL

MIN_LINE_WIDTH=1.0 mmVOLTAGE=2.5V

PP2V5_S0_NB_VCCA_CRTDACPP2V5_S0_NB_CRTDAC_F

=PP1V5_S0_NB_TVDAC

=PP1V8_S3_MEM

MEM_VREF_NB_1

MIN_LINE_WIDTH=0.25 mmVOLTAGE=0.9V

Trang 20

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

PCIe BackwardInterop Mode

VCC Select

ReversalDMI Lane

High = ReversedLow = Normal

High = 1.5VLow = 1.05V

Internal pull-down

945 External Design Spec says reserved

High = Both activeLow = Only SDVO

or PCIe x1

ODTFSB Dynamic

RESERVED

Low = DisabledHigh = Enabled

RESERVED

Internal pull-up

RESERVED

00 = Partial Clock Gating Disable

01 = XOR Mode Enabled

10 = All-Z Mode Enabled

11 = Normal Operation

Internal pull-up

Low = ReversedRESERVEDCPU Strap

RESERVED

PCIE Graphics

High = NormalLow = RESERVED

High = DMIx4Low = DMIx2

PROBABLY NOT NEEDED

DMI x2 Select

Internal pull-upRESERVED

NB_CFG<7> High = Mobile CPU

NB_CFG<10>

NB_CFG<11>

RESERVED

RESERVEDInternal pull-up

Internal pull-ups

2

1R2075

402 5%

5%

1/16W 402

402 MF-LF 5%

2.2K

NBCFG_PEG_REVERSE

C051-7173

Trang 21

INOUT

OUTOUTOUTOUTOUTOUTOUT

INOUT

OUT

OUTIN

ININ

IOIOIOIO

INIO

DDACK*

SATARBIASNSATARBIASP

SATA_CLKNSATA_CLKPSATA_2TXPSATA_2TXN

SATA_2RXNSATA_2RXPSATA_0TXPSATA_0TXNSATA_0RXPSATA_0RXNSATALED*

ACZ_SDOUT

ACZ_SDIN1ACZ_SDIN2ACZ_SDIN0ACZ_SYNCACZ_BIT_CLKLAN_TXD2

LAN_TXD0LAN_TXD1

LAN_RXD1LAN_RXD2

LAN_RSTSYNCLAN_RXD0LAN_CLK

EE_SHCLKEE_CSINTVRMENINTRUDER*

RTCRST*

RTCX2RTCX1

THRMTRIP*

STPCLK*

NMISMI*

RCIN*

INTRINIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGDFERR*

LDRQ1*/GPIO23LDRQ0*

LAD3LAD2

LAD0LAD1

EE_DOUTEE_DIN

ACZ_RST*

DIOR*

IDEIRQDIOW*

IORDYDDREQ

DD0DD1

DD3DD2

DD5DD4

DD6DD7DD8

DD11

DD9DD10

DD12DD13DD14DD15DA0DA1DA2

OUT

ININ

OUTOUT

OUTOUTININ

OUTOUTOUTININ

OUTOUTOUTOUTIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

INTEL HIGH DEFINITION AUDIO

INTERNAL 20K PD ONLY ENABLED IN S3COLD

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLEDINTERNAL 20K PD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

NOTE:

POR IS SMC WILL PUT LAN INT’FINTO RESET STATE TO SAVE PWR

INTEL CONFIRMS OK TO LEAVE PINS AS NC

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLEDINTERNAL 20K PD ENABLED DURING RESET AND WHEN

NONEINTERNAL 20K PD

SB: 1 OF 4

(INT PU)

NOTE: DD<7> HAS INTERNAL 11.5K PD

(HSTROBE)(STOP)

20K PD 20K PD 20K PD

(WEAK INT PU)(INT PU)

(DSTROBE)

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

< 2 IN OF R2107 W/O STUBLAYOUT NOTE: R2108 TO BECHANGED TO 54.9 FOR

NOTE: RISING-EDGE TRIGGERED AT CPUNOTE: KEYBOARD CONTROLLER RESET CPU

SPEC SAYS WEAK PU IS REQUIREDNOTE:

BUT CAPELL VALLEY USES 56-OHM PUCHECK WITH INTEL

(WEAK INT PD)

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

NOTE: PULLED UP PER INTEL

21R21004025%

0MF-LF

NOSTUFF

21R2101

MF-LF5%

2.2K

402

NOSTUFF

21

R2195

MF-LF5%

394021/16W

21

R2198 39

21

R2197 39

21

R2196 39

2

1R2199MF-LF5%

10K402

AH25AF24

AF26AH22AF23

AG10AH10

AF18

AE1AF1AH6AG6AE7AF7AH2AG2AE3AF3

AB2AB1

AA3

AG23AH24

AB3AA5AC3

V7V6U7T5V4U5U3V3

Y6AC4AB5AA6

AG16

W4Y5

AF25

AG21AF22AG22

AH16

AG24AG26

Y1Y2W3W1

AH15AF15

AE15AF16

AF12AE12AC12AD12AC13AD14AF13AG13

AC15AH14AH13AF14AC14AB13

AE14AB15

AD16AE16AF17AE17AH17

AG27

R6

T4T1T3T2R5U1

AH28AE22

U2100

BGA

LEMENU

SB ICH7-M

2

1R2194MF-LF5%

10K402

2

1

R2105MF-LF1/16W1%

402332K

21R21074021%

1/16W24.9

2

1

R2108

54.91%

1/16WMF-LF 402

R2110

54.91%

4021/16W

051-7173

10821

IDE_PDIOW_L

IDE_IRQ14IDE_PDIOR_LSB_ACZ_RST_L

SB_A20GATE

TP_CPU_CPUSLP_LCPU_A20M_L

CPU_DPSLP_LCPU_DPRSTP_L

CPU_FERR_LCPU_PWRGD

CPU_IGNNE_LFWH_INIT_LCPU_INIT_LCPU_INTRCPU_RCIN_L

CPU_SMI_LCPU_NMI

CPU_STPCLK_L

CPU_THERMTRIP_R

SB_RTC_X1SB_RTC_X2SB_RTC_RST_LSB_SM_INTRUDER_L

SB_INTVRMEN

TP_SB_XOR_W1TP_SB_XOR-Y1

SB_ACZ_SYNC

ACZ_SDATAIN<0>

TP_SB_ACZ_SDIN2TP_SB_ACZ_SDIN1

SB_ACZ_SDATAOUT

TP_SB_SATALED_LSATA_A_D2R_NSATA_A_D2R_PSATA_A_R2D_C_NSATA_A_R2D_C_P

SATA_C_D2R_PSATA_C_D2R_N

SATA_C_R2D_C_NSATA_C_R2D_C_P

SB_CLK100M_SATA_PSB_CLK100M_SATA_N

SATA_RBIAS_PSATA_RBIAS_N

IDE_PDDACK_L

TP_SB_XOR-Y2

TP_SB_XOR-U3

TP_SB_XOR-U7TP_SB_XOR-V6TP_SB_XOR-V7

SB_ACZ_BITCLKACZ_BITCLK

Trang 22

ININ

INININOUTOUTOUT

OUT

ININ

OUTOUT

OUTOUTIO

IO

IOIO

IN

IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO

INOUTIN

ININ

OUT

OUTOUT

OUTIO

DMI_ZCOMPDMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXNDMI0RXPDMI0TXNDMI0TXP

DMI2TXNDMI2TXPDMI3RXN

DMI3TXPDMI3TXNDMI3RXP

USBP0NUSBP0PUSBP1NUSBP1PUSBP2NUSBP2PUSBP3NUSBP3P

USBP4PUSBP5NUSBP5PUSBP6NUSBP6PUSBP7NUSBP7P

SPI_CLKSPI_CS*

SPI_MOSISPI_MISOSPI_ARB

DMI_CLKN

DMI2RXPDMI2RXNDMI1TXPDMI1TXN

DMI1RXNDMI1RXP

PERN1PERP1PETN1PETP1PERN2PERP2PETN2PETP2PERN3PERP3PETN3PETP3PERN4PERP4PETN4PETP4PERN5PERP5PETN5PETP5PERN6PERP6PETN6PETP6

MCH_SYNC*

RSVD8RSVD7RSVD6RSVD5

PLOCK*

SERR*

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

MISC INT I/F

IN

IOIOIOIO

OUTIOIOIOIOIOIO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

TRACKPAD (Geyser)

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

AIRPORTIRCAMERAEXTERNAL 1

LAYOUT NOTE:

EXTERNAL 0

NO STUFF - DEFAULT

NOTE: FWH_WP_L NOT USED

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

NOT PLANNED TO GO TO LPC+ CONNNOTE:

(INT PD) (INT PD)

(AKA TP3, INTERNAL 20K PU)

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

PLACE R2204 < 1/2 IN FROM SBLAYOUT NOTE:

PLACE R2203 < 1/2 IN FROM SB

NOTE:

LPC (DEFAULT)PCI

STUFFUNSTUFFUNSTUFFUNSTUFFSTUFF01

1011

R2210R2211

SB: 2 OF 4(INT 20K PU)

NOTE: CHANGE SYMBOL

TO RSVD[1-9]

GNT5# GNT4#

TARGETING FWH BIOS SPACE)

IE SB INVERTS A16 FOR ALL CYCLES

NOTE: TBL_L NET REMOVED

ENABLED ONLY WHEN PCIRST#=0GNT[0-3]# HAVE INT 20K PU

SB BOOT BIOS SELECT

STRAP

21R22031%

MF-LF24.94021/16W

21R2204

MF-LF1%

22.6

402

1

24021/16W5%

10KMF-LFR2223

2

1R2225MF-LF5%

10K402

1R22265%

10K1/16W4022

2

1R2299

402MF-LF5%

10K

D2D1N3N4M2M1L5L4K2K1J3J4H2H1G3G4F2F1

P5P2

P6R2

P1R27N27L27J27G27E27

R28N28L28J28G28E28

T24P25M25K25H25F25

T25P26M26K26H26F26

B3A2C3E5D4D5C4D3

C25D25AE27AE28AC27AC28AD24AD25AA27AA28AB25AB26W27W28Y25Y26U27U28V25V26

U2100

BGA

ICH7-M SB

LEMENU

F14F15B10

F21AH8AG8AE9

AD9AH4AG4AD5AE5

A13E13C17C16D7

B19C26E11

B5C5B4A3

C9

B18

A9E10

AH20

A7

G7F8F7G8

D8C8A14F13D17D16E7

F16

A12

C15D12C12B15

C14A15A17E17A18E16

D6E6

F18

B6C7A6A8B9D9E9F10F11A10

A16

A11D11C11E12G13G15C13B12D14E14

C18E18

U2100

BGA SB ICH7-M

LEMENU

2

1R2200

402

10K5%

1/16W

2

110K5%

1/16WR2250

USB_C_OC_PU

1

402MF-LF5%

10K1/16WR2251

USB_E_OC_PU

1

USB_D_OC_PU

4025%

2MF-LF10K

R2255

MF-LF

10K5%

1/16WR2208

40221

402

1K5%

MF-LF

051-7173

10822

TP_SB_GPIO22

PCI_REQ1_LTP_PCI_GNT0_L

TP_PCI_GNT1_LPCI_REQ2_LTP_PCI_GNT2_LPCI_REQ0_L

PCI_PME_FW_L

BOOT_LPC_SPI_L

TP_SB_XOR_AH8TP_SB_XOR_AG8TP_SB_XOR_AE9

TP_SB_RSVD9TP_SB_XOR-AD9

TP_SB_XOR-AH4TP_SB_XOR-AG4TP_SB_XOR-AD5TP_SB_XOR-AE5INT_PIRQD_L

USB_D_OC_LUSB_B_OC_L

USB_E_OC_LUSB_A_OC_LSPI_SCLK

NB_SB_SYNC_L

SB_GPIO5SB_GPIO4SB_GPIO3SB_GPIO2

PCI_C_BE_L<0>

PCI_C_BE_L<1>

PCI_DEVSEL_LPCI_PERR_L

PCI_STOP_L

PCI_RST_LTP_PCI_PME_LPLT_RST_LPCI_TRDY_L

PCI_FRAME_L

PCI_IRDY_L

PCI_CLK_SBPCI_PAR

PCI_LOCK_LPCI_SERR_L

USB_B_P

USB_D_N

USB_E_PUSB_F_N

USB_G_NUSB_G_PUSB_H_NUSB_H_PUSB_E_N

SB_GPIO30SB_GPIO29

SB_GPIO31

PP1V5_S0_SB_VCC1_5_B

USB_C_OC_L

USB_A_OC_LUSB_B_OC_L

USB_D_OC_L

SPI_CE_L

SPI_SISPI_SO

SB_CLK100M_DMI_NDMI_S2N_P<3>

DMI_S2N_N<3>

DMI_IRCOMP_R

USB_B_NSB_CLK100M_DMI_P

USB_D_P

USB_C_NUSB_C_P

Trang 23

IN

INOUT

OUTOUTOUT

OUT

ININ

IOIO

OUTOUT

OUTININ

IO

ININIO

IN

ININ

OUTIN

IN

OUT

GPIO19/SATA1GPGPIO21/SATA0GP

GPIO12

GPIO14GPIO13

GPIO24GPIO15

GPIO25GPIO35GPIO38GPIO39

SMBCLKSMBDATALINKALERT*

SMLINK1SMLINK0

RI*

SYS_RST*

SPKRSUS_STAT*

GPIO7GPIO6VRMPWRGD

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

STRAPPING @ PWROK RISING:

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

IN RESET STATE TO SAVE PWR

NOTE: PATA_DET IS ACTUALLY CABLE TYPE DETECT

DEF=GPI

NOTE FOR R2323 (DEF=NOSTUFF)

SB WILL DISABLE TCO TIMERSYSTEM REBOOT FEATURE

NOTE FOR GPIO25:

(INT 20K PU)

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

LAYOUT NOTE:

(INT WEAK PD)

NOTE: RESERVED FOR FUTURE

AZALIA DOCKING INT’FRESERVED FOR MOBILE

2

R230721/16W

10K

4025%

MF-LF1

4021/16WMF-LF5%

10K

R23081

21

4025%

MF-LF1/16W

10K

R23101

2

1/16WMF-LF5%

NOSTUFF

402

10K

R23111

2

10K

1/16WMF-LF5%

402R23131

2

402

NOSTUFF0

1/16WMF-LF5%

R23141

10K

4021

1/16WMF-LF5%

2

10K

4021/16WMF-LF5%

402R23191

2

4025%

MF-LF1/16W

10KSM-LF

1 2 3 4

8 7 6 5

5%

402 MF-LF1/16W100K

MF-LF1/16W

5%

MF-LF1/16W

AF20

SB

BGA

AC1B2

AB18

A20B23

F19E19R4E22

AC22AC20

AH18

AF21

AF19

R3D20

A21B21E23AG18AC19U2

AD21

AH19AE19

AD20AE20

AC21AC18E21

E20C19

A26

C23AA4A28

Y4

AH21

B24D23F22

C22B22

B25A25

R2390

2MF-LF4021/16W5%

10K1

402

10K5%

MF-LF

R23881

2

402

21R23125%

MF-LF0NOSTUFF

2R2315

MF-LF402

15%

1/16W0

15K

40221

MF-LF5%

R2389

NO_REBOOT_MODE

MF-LF4025%

NOSTUFF

5%

MF-LF1/16W402

2

051-7173

10823

=PP3V3_S5_SB

FWH_MFG_MODEBIOS_REC

TP_SB_GPIO6

TP_SB_GPIO38PATA_PWR_EN_L

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

VR_PWRGD_CK410TP_AZ_DOCK_RST_LBIOS_REC

PM_BMBUSY_L

PM_SUS_STAT_LPM_SYSRST_LSMLINK<0>

SV_SET_UPCRB_SV_DET

PM_DPRSLPVR

SB_GPIO37

SB_CLK48M_USBCTLR

SB_GPIO21SB_GPIO19

PM_RSMRST_L

SUS_CLK_SB

PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_LPM_SB_PWROK

PM_LAN_ENABLEPM_PWRBTN_L

PM_BATLOW_L

INT_SERIRQPM_THRM_LPM_CLKRUN_LPM_STPCPU_L

Trang 24

(6 OF 6)

VSS

V5REF_SUS

VCC3_3VCCDMIPLL

VCCSATAPLLVCC3_3

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDAVCCSUS3_3/VCCSUSHDAVCCLAN_3_3

VCC1_05V5REF

VCC1_5_B

(5 OF 6)

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

NOTE FOR VCCLAN_3_3:

S3 IF INTERNAL LAN IS USEDS0 OR S3 IF NOT

CHANGE SYMBOL TO 1.05

SO NO CONNECT HEREVOLTAGE GENERATED INTERNALLY

SB: 4 OF 4

NOTE:

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3VDEPENDING ON VIO OF AZALIA INTERFACECODEC IC’S CONSIDERED SO FAR ARE 3.3V

SB ICH7-M

LEMENU

BGA

U2100

A4A23

B1

B8B11B14B17B20B26B28C2C6C27D10

D13D18D21D24E1E2E4E8E15F3F4

F5F12F27F28G1G2G5G6G9G14G18

G21G24G25G26H3H4H5H24H27H28J1

J2J5J24J25J26K24K27K28L13L15L24

L25L26M3M4M5M12M13M14M15M16M17

M24M27M28N1N2N5N6N11N12N13N14

N15N16AE24

AE25AF2AF4AF8AF11AF27AF28N17

AG1AG3AG7

AG11AG14AG17AG20AG25AH1AH3N18

AH7AH12AH23AH27

N24

N25N26P3P4P12P13P14P15P16P17P24

P27P28R1R11R12R13R14R15R16R17R18

T6T12T13T14T15T16T17U4U12U13U14

U15U16U17U24U25U26V2V13V15V24V27

V28W6W24W25W26Y3Y24Y27Y28AA1AA24

AA25AA26AB4AB6AB11AB14AB16AB19AB21AB24AB27

AB28AC2AC5AC9AC11AD1

AD3AD4AD7AD8

AD11

AD15AD19AD23AE2AE4AE8AE11AE13AE18AE21

ICH7-M SB

LEMENU

BGA

U2100

G10AD17F6

AE23AE26AH26

L11

P18T11T18U11U18V11V12V14V16V17L12

V18

L14L16L17L18M11M18P11

AB7AC6

AB9AC10AD10AE10AF10AF9AG9AH9

AB17AC17AC7

T7F17G17AB8AC8

A1H6H7J6J7

AD6AE6AF5AF6AG5AH5

AB10

AA22AA23

AD28D26D27D28E24E25E26F23F24G22AB22

G23H22H23J22J23K22K23L22L23M22AB23

M23N22N23P22P23R22R23R24R25R26AC23

T22T23T26T27T28U22U23V22V23W22AC24

W23Y22Y23

AC25AC26AD26AD27

G16

AB12AB20AC16AD13AD18AG12AG15

AG28

AA2Y7

V5V1W2W7

W5

AD2

K7C28G20

R7

P7A24

L1L2L3L6L7M6M7N7

E3

C24D19D22G19K3K4K5K6

C1

051-7173

10824

Trang 25

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

ICH VCCA3GP(VCC1_5_B BYPASS(ICH IO,LOGIC 1.5V PWR)

PLACE C2520 NEAR PIN E3 OF SBPLACE < 2.54MM OF SB ON SECONDARY OR

ICH VCC3_3 BYPASS

3.56MM ON PRIMARY NEAR PIN U6

PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PIN AG5

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

PLACEMENT NOTE:

A24 G19 AND P7 OF SB

NEAR PINS A5 G16 PLACE C2509 NEAR PIN B27 OF SB

ICH VCCDMIPLL BYPASS(ICH USB PLL 1.5V PWR)

ICH VCC1_5_A/ATX BYPASS

(ICH IDE I/O 3.3V PWR)

PLACE < 2.54MM OF SB ON SECONDARY ORPLACEMENT NOTE:

(ICH USB CORE 1.5V PWR)ICH USB CORE/VCC1_5_A BYPASS

AB8 AND AC8 OF SBPLACE CAPS NEAR PINS(ICH LOGIC&IO 1.5V PWR)

K3 N7 OF SBPLACE CAPS NEAR PINSPLACEMENT NOTE:

PLACE < 2.54MM OF SB ON

PLACEMENT NOTE:

ICH VCC3_3/VCCHDA BYPASS

ICH VCCUSBPLL BYPASS

ICH PCI/VCC3_3 BYPASS

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PIN AH11

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PINS A1 J7

ICH VCC1_5A BYPASS

ICH VCCSUS3_3 BYPASS(ICH SUSPEND 3.3V PWR)

PLACE CAPS NEAR PIN W5 OF SB

PLACE CAPS NEAR PINS

3.56MM ON PRIMARY NEAR PIN AG9

DISTRIBUTE IN PCI SECTION OF SB

(ICH PCI I/O 3.3V PWR)ICH IDE/VCC3_3 BYPASS

ICH V_CPU_IO BYPASSPLACE < 2.54MM OF SB ON SECONDARY OR

ICH VCCSATAPLL BYPASS

(ICH IO BUFFER 3.3V PWR)

PLACEMENT NOTE:

NEAR PINS D28, T28, AD28

PLACE C2520 NEAR PIN C1 OF SB

(ICH SUSPEND USB 3.3V PWR)ICH USB/VCCSUS3_3 BYPASS

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AD2

3.56MM ON PRIMARY NEAR PINS AA7 AG19 V5, W2, OR W7

ICH VCCRTC BYPASS(ICH RTC 3.3V PWR)PLACEMENT NOTE:

ICH VCC1_5_A/ARX BYPASS(ICH LOGIC&IO[ARX] 1.5V PWR)

SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH CORE/VCC1_05 BYPASS(ICH CORE 1.05V PWR)PLACE CAPS AT EDGE OF SB

FOR 270UF

ICH VCC_PAUX/VCCLAN3_3 BYPASS

PLACEHOLDER

PLACE CAP UNDER SB NEAR PINS V1,

(ICH LAN I/F BUFFER 3.3V PWR)

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

1

2 2.5V220UFSMB220%

0.1UF402

X5R

0

21R2500

15%

1/10WMF-LF 603

C2524

4.7UF2120%

6.3V603

C25222

10.1UF10%

X5R

56

1D2502

BAT54DWSOT-363

23

4D2502

BAT54DWSOT-363

21

L2507

12060.28-OHM

2

0.1UF40210%

100-OHM-EMI L2500

21

SM-3

0

C250510%

2

10.1UFX5R

0.1UFX5R2

2

0.01UF10%

CERM402

2

603

10UF20%

6.3VX5R

0

C251121

X5R10%

0

0.1UF2

X5R

2

40216V0.1UF

2.5V330UF2

11UF10%

6.3V4020.1UF2

40210%

0.1UF402

0

0.1UF2

C25231

2X5R10%

0

2

0.1UFX5R10%

402

0

4022

X5R10%

0.1UF2

X5R10%

0.1UF402

C2528

0.1UF21

X5R10%

X5R

051-7173

10825

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MMVOLTAGE=5VMIN_LINE_WIDTH=0.3MM

PP1V5_S0_SB_VCCDMIPLL

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMVOLTAGE=1.5V

Trang 26

ININININ

IOIO

IOIOIOIOIOIOOUT

OUT

ININ

OUT

IOIOIOIO

IOIO

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

Initial resistor values are based on CRB, but may change after characterization.

to solder a reset button.

on the board to short or

it provides a set of pads This part is never stuffed, Silk: "SYS RST"

Platform Reset Connections

Linda Card represents 3 loads

1/16W4025%

20K

R2600

40210V0.1UFCERM20%

C26111

2

40210%

6.3V1UFCERM

C2605

1

2

100K1/16W4025%

OMIT

2

R2606MF-LF1M4025%

1/16W1

2

10K5%

MF-LF4021/16W

2

SC70MC74VHC1G08

U2601

32

14

5

1/16W402MF-LF5%

1K

R26071

2

15pF

402CERM50V5%

C2608

1 2

50V5%

CERM402

15pF

C2609

1 2

1/16W402

05%

R2610

5%

1/16W40210M

2

SC70MC74VHC1G08

U2680

32

1

45

0.1UF20%

CERM402

C26801

2

5%

402MF-LF100K

R26801

2

MF-LF402

R2681

01/16W5%

2100

R26831/16W4025%

MF-LF1

BSS138SOT23

R2682

402MF-LF5%

0

R26891

2

NOSTUFF 100K5%

1/16W402MF-LF

R26881

8 7 6 5

MF-LF402

R2687

SC70-5MC74VHC1G00

U2603

32

14

5

0

R2685

402MF-LF5%

1/16W

1K

402MF-LF5%

1/16W

R269612

CRITICAL

J2600

88460-0201F-RT-SM3

4

12

1/16W1.8K402MF-LF5%

R26111

2

0.1UFCERM20%

402

2

10K5%

1/16W402

5%

10K402

R26221

6.3V402

26SYNC_MASTER=NB

SMC_LRESET_L

TPM_LRESET_L

DEBUG_RST_L PLT_RST_BUF_L

SB_GPIO4 SB_GPIO5

PLT_RST_LMAKE_BASE=TRUE

PPVBATT_G3C_RTC_R

=PP3V42_G3H_SB_RTC

PCI_REQ3_L PCI_LOCK_L

PCI_TRDY_L

PCI_PERR_L PCI_DEVSEL_L PCI_SERR_L

SB_RTC_X2

MAKE_BASE=TRUEVR_PWRGD_CK410_L

=PP3V3_S0_RSTBUF SB_RTC_X1_R

PCI_REQ1_L PCI_REQ2_L

PLT_RST_GATED_L

PCI_REQ0_L

INT_PIRQC_L SB_GPIO2 INT_PIRQD_L SB_GPIO3

Trang 27

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

ICH7-M SMBus Connections

SMC "Battery B" SMBus Connections

Top-Case

(SEE TABLE)

(MASTER) U5800

402MF-LF2

1

R2750

2.0K5%

1/16W402MF-LF

2

1/16W4025%

5%

1/16W8.2K

2

1

R2760

2.0KMF-LF4025%

1/16W2

2.0K4025%

1/16W

2

MF-LF402

2.0K1/16W5%

2

1/16W5%

402MF-LF2.0K

2

100K1/16W4025%

2

100KMF-LF5%

2.0K

M42 SMBUS CONNECTIONS

051-7173SYNC_DATE=08/30/2005

10827

CSYNC_MASTER=ENET

=SMB_AIRPORT_DATA

=SMB_GEYSER_CLK

=SMB_GEYSER_DATA

SMB_BSB_CLK SMB_BSB_DATA

MAKE_BASE=TRUESMBUS_SMC_RMT_SDA

SMBUS_SMC_RMT_SCLMAKE_BASE=TRUE

=SMBUS_ATS_SCL

=SMBUS_ATS_SDA

MAKE_BASE=TRUESMBUS_SMC_BSA_SCLMAKE_BASE=TRUESMBUS_SMC_BSA_SDA

SMB_THRM_DATA SMB_THRM_CLK

THRM_DIMM1_SMB_DATATHRM_DIMM1_SMB_CLK

=PP3V3_S0_SMBUS_SMC_MLB

=PP3V3_S3_SMBUS_SMC_RMT

SMBUS_SMC_0_SCLMAKE_BASE=TRUEMAKE_BASE=TRUESMBUS_SMC_0_SDA

Trang 28

VSS2DQ5

SA1SA0VSS58DQ63DQ62VSS56DQS7DQS7*

VSS54DQ60VSS52DQ54VSS50VSS48CK1*

CK1VSS46DQ53DQ52VSS44VSS42DQS5DQS5*

VSS39DQ45DQ44VSS37DQ39DQ38VSS35DM4VSS34DQ37DQ36VSS32NC3VDD11NC/A13ODT0VDD9S0*

RAS*

BA1VDD7A0A2A4VDD5A6A7A11VDD3NC/A14NC/A15VDD1NC/CKE1VSS30DQ31DQ30VSS28DQS3DQS3*

VSS26DQ29DQ28VSS24DQ23DQ22VSS22DM2NC0VSS19DQ21DQ20VSS17VSS15DQ15DQ14VSS13CK0*

CK0VSS11DQ13VSS7DQ7VSS5DM0

DQ4VSS0

DM1DQ12DQ6

DQ47DQ46

DQ61DQ55DM6

VDDSPDSCLSDAVSS57DQ59DQ58VSS55DM7VSS53DQ56VSS51DQ50VSS49DQS6*

VSS47NC_TESTVSS45DQ49DQ48VSS43VSS41DM5VSS40DQ41VSS38DQ35VSS36DQS4DQS4*

VSS33DQ33DQ32VSS31NC/ODT1VDD10NC/S1*

CAS*

VDD8WE*

BA0A10/APVDD6A1A3A5VDD4A8A9A12VDD2BA2NC2VDD0CKE0VSS29DQ27DQ26VSS27NC1DM3VSS25DQ25DQ24VSS23DQ19DQ18VSS21DQS2DQS2*

VSS18DQ17DQ16VSS16VSS14DQ11DQ10VSS12DQS1DQS1*

DQ9DQ8VSS8DQ3DQ2VSS6DQS0DQS0*

VSS4

VSS1VREF

DQ0DQ1

DQ34

DQ40

DQ42DQ43

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

Yellow uses 10K divider and TLV2463

to drive MCH and DIMM connectors.

DIP DIMM CONN

(For return current)

DDR2 VRef One 0.1uF per connector

Power aliases required by this page:

when they get cheaper.

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

ADDR=0xA0(WR)/0xA1(RD)

NCNC

NC

516-0135NC

Page Notes (See Capell Valley pg 47)

2

1C2813

20%

402CERM

0.1uF

10V

2

1C281210V

40220%

0.1uF

CERM2

1C2811

402CERM

20%

4.7uF

CERM603

2

1C28100.1uF

10V

CERM40220%

2

1C2815

402CERM20%

10V

0.1uF

2

1C281410V

CERM20%

0.1uF20%

CERM

2

0.1uFCERM10V402

2

2.2UF20%

4VX5R

2

2.2UFX5R4V20%

10%

6.3V

CERM402

2

1C2832

402CERM

10%

1uF

CERM402

202

2011

181175169

151

141135

573

911

15171921232527293133353739414345474951535557596163656769717375777981838587899193959799101103105107109111113115117119121123125127129131133

137139

143145147149

155157159161163165167

171173

177179

183185187189191193195197199153

262014

24681012

1618

22

3234363840424446

50525456586062646668707274

7880

182176170

154152

828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150

156

160

164166168

172174

178180

184186188190192194196198200

76

158

3028

2

1

R2801

1/16W1%

402MF-LF

516-0154 CONN,200P STD SODIMM NEW REV 3.5 J2801 POST-RAMP-DIMM35

051-7173DDR2 SO-DIMM Connector A

Trang 29

VSS2DQ5

SA1SA0VSS58DQ63DQ62VSS56DQS7DQS7*

VSS54DQ60VSS52DQ54VSS50VSS48CK1*

CK1VSS46DQ53DQ52VSS44VSS42DQS5DQS5*

VSS39DQ45DQ44VSS37DQ39DQ38VSS35DM4VSS34DQ37DQ36VSS32NC3VDD11NC/A13ODT0VDD9S0*

RAS*

BA1VDD7A0A2A4VDD5A6A7A11VDD3NC/A14NC/A15VDD1NC/CKE1VSS30DQ31DQ30VSS28DQS3DQS3*

VSS26DQ29DQ28VSS24DQ23DQ22VSS22DM2NC0VSS19DQ21DQ20VSS17VSS15DQ15DQ14VSS13CK0*

CK0VSS11DQ13VSS7DQ7VSS5DM0

DQ4VSS0

DM1DQ12DQ6

DQ47DQ46

DQ61DQ55DM6

VDDSPDSCLSDAVSS57DQ59DQ58VSS55DM7VSS53DQ56VSS51DQ50VSS49DQS6*

VSS47NC_TESTVSS45DQ49DQ48VSS43VSS41DM5VSS40DQ41VSS38DQ35VSS36DQS4DQS4*

VSS33DQ33DQ32VSS31NC/ODT1VDD10NC/S1*

CAS*

VDD8WE*

BA0A10/APVDD6A1A3A5VDD4A8A9A12VDD2BA2NC2VDD0CKE0VSS29DQ27DQ26VSS27NC1DM3VSS25DQ25DQ24VSS23DQ19DQ18VSS21DQS2DQS2*

VSS18DQ17DQ16VSS16VSS14DQ11DQ10VSS12DQS1DQS1*

DQ9DQ8VSS8DQ3DQ2VSS6DQS0DQS0*

VSS4

VSS1VREF

DQ0DQ1

DQ34

DQ40

DQ42DQ43

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

NC

NCNC

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

- =I2C_MEM_SDASignal aliases required by this page:

- =PP1V8_S3_MEM

(See Capell Valley pg 47)

to drive MCH and DIMM connectors.

when they get cheaper.

One 0.1uF per connector DDR2 VREF (FOR CONNECTOR B)

DIP DIMM CONN

60320%

6.3V

CERM

4.7uFC2909

12

0.1uF20%

CERM402

C29001

2

1K

MF-LF1%

1/16W402

R2901

1

2

1/16W1%

CERM

0.1uF

10VC2913

1240220%

CERM

0.1uF

10VC2912

1240220%

CERM

0.1uF

10VC2911

1240220%

CERM

0.1uF

10VC2910

12

402

10V

0.1uF

CERM20%

C2915

12402

10V

0.1uF

CERM20%

C2914

12

4024V20%

2.2UF

C29201

2

CERM402

6.3V

10%

1uFC2916

12

1uF

10%

6.3V

402CERM

C29171

C29311

2

CERM402

6.3V

10%

1uFC29301

C29321

2

20%

CERM0.1uF402

C29211

2X5R4V20%

2.2UF402

C29221

2

10K

5%

1/16W 402

R2900

1 2

202

2011

181175169

151

141135

573

911

15171921232527293133353739414345474951535557596163656769717375777981838587899193959799101103105107109111113115117119121123125127129131133

137139

143145147149

155157159161163165167

171173

177179

183185187189191193195197199153

262014

24681012

1618

22

3234363840424446

50525456586062646668707274

7880

182176170

154152

828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150

156

160162164166168

172174

178180

184186188190192194196198200

76

158

3028

F-RT-TH2

OMIT

POST-RAMP-DIMM35J2901

CONN,200P STD SODIMM NEW REV 3.5

CRITICAL PVT-DIMMJ2901

CONN,200P STD SODIMM OLD REV

516-0149 1

051-7173

SYNC_MASTER=MEMORY

10829

Trang 30

IN

ININININININININININININININ

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED

BOMOPTION shown at the top of each group applies to every part below it One cap for each side of every RPAK, one cap for every two discrete resistors

56

R3011 1 2

402MF-LF1/16W5%

C30181

2

402 20%

CERM

0.1uFC30191

2

402

0.1uF

CERM 10V

C30211

2

402

0.1uF

CERM 10V

C30201

2

0.1uF

CERM 10V 402

C30241

2

0.1uF

CERM 10V 402

C30251

RP3003 2 7

SM-LF5% 1/16W

56

RP3003 3 6

SM-LF5% 1/16W

56

RP3003 4 5

SM-LF5% 1/16W

RP3004 3 6

SM-LF

56

1/16W5%

RP3004 4 5

SM-LF

56

1/16W5%

RP3005 1 8

SM-LF

56

1/16W5%

RP3005 2 7

SM-LF5% 1/16W

56

RP3005 3 6

SM-LF5% 1/16W

RP3006 1 8

SM-LF

56

1/16W5%

RP3006 2 7

SM-LF5% 1/16W

RP3007 2 7

SM-LF

56

1/16W5%

RP3007 1 8

SM-LF5% 1/16W

RP3008 3 6

SM-LF5% 1/16W

56

RP3008 2 7

SM-LF5% 1/16W

56

RP3008 1 8

SM-LF5% 1/16W

RP3009 2 7

SM-LF5% 1/16W

RP3011 1 8

SM-LF5% 1/16W

RP3011 4 5

SM-LF5% 1/16W

56

RP3006 4 5

SM-LF5% 1/16W

CERM

0.1uFC3000

1 2

402 20%

CERM

0.1uFC3001

1 2

402 20%

CERM

0.1uFC3007

1 2

0.1uF

CERM 10V 402

C3010

1 2

0.1uF

CERM 10V 402

C30231

2

402

0.1uF

CERM 10V

C3012

1 2

402 20%

CERM

0.1uFC3013

1 2

402 20%

CERM

0.1uFC3014

1 2

402

0.1uF

CERM 10V

C3015

1 2

0.1uF

CERM 10V 402

C3016

1 2

402

0.1uF

CERM 10V

C3017

1 2

0 1

1 0

2

0 1 2 3 4 5 6 7

10 11 9 8

13 12

2 3

0.1uF

CERM 10V 402

C3009

1 2

0.1uF

CERM 10V 402

C3006

1 2

402 CERM 20%

0.1uFC3005

1 2 20%

402 20%

CERM

0.1uFC3003

1 2 20%

0.1uF

CERM 10V 402

C3011

1 2

0 1 2 3

Trang 31

VTTGND

VTT_INENVTTSVDDQ VCC

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

disable MEMVTT in sleep

If power inputs are not S0,

10uF

603

CRITICAL

37

84

5 6

12

U3100

BD3533FVM

MSOP-82

6.3V 20%

CERM1 603

21R3104

2205%

MF-LF4021/16W

2

1C31030.1uF

X5R 10%

402

2

1C3100

CERM 10%

Trang 32

OUT

OUTOUT

OUT

INOUT

OUT

OUTOUTOUTOUT

INIO

OUTIN

IO

OUTOUT

IN

OUTOUT

IN

VSS_SRC

THRML_PADVSS_REFVSS_PCIVSS_CPUVSS_48

NCSDA

PCIF_1PCIF_0/ITP_ENPCI_5/FCT_SEL_1PCI_4PCI_3PCI_2PCI_1FS_B_TEST_MODE

REF_1/FCT_SEL_0REF_0/FS_C/TEST_SEL

48M/FS_AVTT_PWRGD*/PD

VDD_A

XTAL_INXTAL_OUT

CPU_ITP/SRC_11*

CPU_ITP/SRC_11

SRC_0/LCD_CLKSRC_0/LCD_CLK*

SRC_1SRC_1*

SRC_2*

SRC_2

SRC_3SRC_3*

SRC_4SRC_4*

SRC_5*

SRC_5

SRC_7*

SRC_7SRC_8*

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

(TPM LPC 33MHZ)

(GMCH HOST 133/167MHZ) (ITP HOST 133/167MHZ)

(CPU HOST 133/167MHZ) (FROM ICH7 GPIO20 STPCPU* ) (FROM ICH7 GPIO18 STPPCI* )

(INT PU)(INT PD)

(FW PCI 33MHZ) (SMC LPC 33MHZ) (NO USED) (PORT80 LPC 33MHZ)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(ICH SM BUS)

(ICH7M PCI 33MHZ)

0 PIN 6

* FOR EXT GRAPHIC SYSTEM

* FOR INT GRAPHIC SYSTEM

SRCT0 SRCT0 DOT96C DOT96T

DOT96T

PIN 7 PIN 10 PIN 11

100MC_SST FCTSEL1

0 0

1

27M NONSPREAD 27MSPREAD

TBD

DOT96C 100MT_SST

SRCT0

SRCC0 SRCC0 SRCC0 FCTSEL0

(INT PU)(INT PU)

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?

(FOR PCI-E CARD) (GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

(ICH7M USB 48MHZ) (ICH7M,SIO,LPC REF 14.318MHZ)

(NOT USED )

(FROM GMCH CLK_REQ*)

(FROM CPU VCORE PWR GOOD)

PROTO TO REMOVE 100M FROM SIGNAL NAME)

(EACH POWER PIN PLACED ONE 0.1UF) (PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

(INT PU)

(INT PU)(INT PU)

(INT PD)(INT PD)

(INT PU)(INT PU)

10UF60320%

6.3V1

2

C3309

120-OHM-0.3A-EMI

21

0402-LF

L3302

0.1UF10%

X5R

C33051

2

C3306

16V40210%

0.1UF1

2

40216V0.1UF10%

C33071

2

0.1UF10%

40216V

C33081

2

15PF40250V1

2 CERM

C3390

5%

15PF5%

C3389

1

250VCERM402

MF-LF1%

4754021/16W

110UF 0.1UF

16V40210%

1

2C3311

40210%

0.1UF

C33041

2

X5R

0.1UF10%

C33031

20.1UF10%

402

C33021

2

16V402

0.1UF10%

C33011

2

1UF6.3V10%

4021

2C3310

10UF6036.3V20%

C33151

2

21

0402-LF120-OHM-0.3A-EMI L3301

1UF10%

CERM402

C33141

2

402MF-LF

R3302

12.225%

1/16W

4021/16W5%

MF-LF1

R3303

6.3V20%

603

10UF2

R3304

MF-LF402

2.25%

OMIT

4445

5

47

6865646358

38

QFN

31

6952666246

481

578

535442

5150

34

256020599

5556

4241

3637

1011

1314

1615

1819

2122

2423

302932

2726

33

76

CLOCKS

051-7173

PP3V3_S0_CK410_VDD48

MIN_NECK_WIDTH=0.2mmVOLTAGE=3.3V

CK410_CPU0_P CK410_CPU1_N

SMB_CK410_DATA

CK410_SRC8_N CK410_SRC7_P CK410_SRC7_N CK410_SRC_CLKREQ6_L

CK410_XTAL_OUT

CK410_PCIF0_CLK

CK410_IREF

CK410_PCIF1_CLK CK410_PCI5_FCTSEL1

CK410_PCI4_CLK CK410_PCI3_CLK CK410_PCI2_CLK CK410_PCI1_CLK CK410_FSB_TEST_MODE

CK410_REF1_FCTSEL0 CK410_CLK14P3M_TIMER CK410_USB48_FSA CK410_PD_VTT_PWRGD_L CK410_SRC_CLKREQ8_L

CLK_NB_OE_L SB_CLK100M_SATA_OE_L SMB_CK410_CLK

CK410_CPU2_ITP_SRC10_P

CK410_SRC3_N

CK410_SRC4_P CK410_SRC4_N

CK410_SRC5_N CK410_SRC5_P

CK410_SRC6_N CK410_SRC6_P

CK410_SRC8_P

CK410_DOT96_27M_N CK410_DOT96_27M_P

MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK410_VDD_REF

VOLTAGE=3.3VMIN_LINE_WIDTH=0.5mm

CK410_CPU2_ITP_SRC10_N CK410_CPU1_P PM_STPCPU_L

CK410_SRC_CLKREQ3_L CK410_SRC3_P

CK410_SRC2_N CK410_SRC_CLKREQ1_L CK410_LVDS_P

CK410_CPU0_N PM_STPPCI_L

CK410_XTAL_IN

PP3V3_S0_CK410_VDDA

PP3V3_S0_CK410_VDD_PCI

MIN_LINE_WIDTH=0.5mmVOLTAGE=3.3V

PP3V3_S0_CK410_VDD_CPU_SRC

Trang 33

ININ

IN

OUTOUT

OUT

IOIO

ININ

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY (ICH7M 14.318MHZ)

(PORT80 LPC 33MHZ)

(TO ICH7M USB 48MHZ)

(TO MCH FS_A)

(TO MCH FS_B)

# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED, M42 133MHZ

(TO ICH7M PCI 33MHZ)

(FROM CPU FS_C) (FROM CPU FS_B)

(GMCH DISPLAY PLLB FOR LVDS SPREAD 100MHZ) (GMCH DISPLAY PLLA 96MHZ)

(FROM CPU FS_A)

# 0

1

FS_C 0 0

1 FS_B 0 1

0 1 1 1

0 FS_A

(TO TPM PCI 33MHZ) (TO FIREWIRE PCI 33MHZ)

CPU 100M 166M 133M

NEED TO CHECK THE BSEL PULLS

(TO MCH FS_C)

1/16W49.91%

402MF-LF

R3441

NOSTUFF

1/16W4021%

MF-LF5%

2

1/16W

1R3419

4025%

MF-LF0

2R3420

402

1

5%

1/16W0

02R34211

5%

1/16W402

R3422

1/16W

21

4025%

0

21R3423

402MF-LF5%

1/16W0

21

5%

4021/16W0

MF-LF

R3465

5%

1/16W402

21

MF-LF0

21R3428

5%

MF-LF0

R342721

5%

4021/16W0

1%

49.9

MF-LF4021/16W

4025%

1/16W

R3433

331/16W5%

402MF-LF5%

1/16W0

1

5%

MF-LF4021/16W

02R3434

NOSTUFF49.91/16W4021%

MF-LF

NOSTUFF

402MF-LF49.9

1/16W

R3463

22 33

2 1/16W

10K

MF-LF 5%

402

1 R3467

402 1/16W

10K

MF-LF 5%

1K5%

1

2

NOSTUFF

402MF-LFR34681/16W1K5%

R3472

1K1/16W4025%

R3470

402MF-LF5%

1K1/16W1

2R3471

1K5%

MF-LF402

211/16W4021%

49.9

R3409

NOSTUFF

NOSTUFF1KMF-LFR3473

24025%

1

R34751/16W402

1K5%

R34741/16W1K

402MF-LF5%

23

1%

1/16W402

149.92

5%

402MF-LF01/16W

R3478

2

MF-LF402

01

1/16W5%

R3477

NOSTUFF

MF-LF402

21%

49.91/16W

R3439

1

402MF-LF1K

R34801

5%

1/16W2

402MF-LF1%

402

1/16W

R3450

01

MF-LF4025%

2

R3453

05%

1/16W402

R34544025%

1K1/16W1

2

NOSTUFF

1/16W49.91%

1K1/16WR34521

2

1K4021

2

R34905%

21

MF-LF5%

0

NOSTUFF

MF-LF

49.91%

402

R3440

402MF-LF

21R3413

5%

1/16W0

21

402MF-LF

NOSTUFF49.91%

4021%

NOSTUFF

1%

1/16W49.9

R3442

MF-LF402

21R3412

402MF-LF5%

1/16W0MF-LF

R3414

402

21

5%

0

R3403

NOSTUFF49.91%

402

MF-LF

NOSTUFF49.91%

1/16W402MF-LF

R3405

NOSTUFF49.91%

MF-LF5%

402

ITP0

2

5%

MF-LF4021/16W

1R3417

33

2.2K

MF-LF4025%

CK410_CPU1_N

FSB_CLK_NB_P CK410_CPU0_P

CPU_XDP_CLK_P

ENET_CLK100M_PCIE_P CK410_PCIF1_CLK

SB_CLK100M_DMI_N

FSB_CLK_NB_P

FSB_CLK_CPU_P ENET_CLK100M_PCIE_N

PCI_CLK_FW

PCI_CLK_SMC

PCI_CLK_TPM CK410_PCI2_CLK

Trang 34

OUT

GD

S

GD

S

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

ODD detect need less than 100ms include OS latency

Indicates disk presence, to SMC

SB_GPIO5 IS PULLED HIGH

NC

ARE CONTROLLED BY PP5V_RUN 1MM / 0.6MM

Per ATA Spec

NC

MIN_NECK & MIN_LINE WIDTH

PER ATA SPEC

NC

PER ATA7 SPEC

NCNC

NC

516S0339NC

APPLY A WIDE TRACE SHAPE FROM JC901 TO C3805/C3806

PLACE C3805/C3806 CLOSE TO JC901 FOR PP5V_PATA

4.7K

21/16W5%

402MF-LF

R38511

50VCERM10pF4025%

NO STUFF

2

MF-LF5%

6.2K1/16W402

R38591

2402

MF-LF5%

0

R38581

2

402

10V

CERM20%

NOSTUFF

C38061

2

5%

10K1/16WR3824MF-LF

NOSTUFF

40221

5%

33K1/16W402

R38531

2

FDC638PSM-LF

Q3810

1256

34

220%

CERM0.1UF

402

C38761

6.2K5%

1/16W402

R38651

2

10K

R3876MF-LF4025%

21

SOT-3632N7002DW-X-F

Q38756

2

1

2N7002DW-X-FSOT-363Q3875

4

3

5

402MF-LF5%

100K

R38771

2

CRITICAL

J380151

52

1

101112131415161718192

202122232425262728293

303132333435363738394

404142434445464748495

50

7896

M-ST-SM5-1775184-0

10%

2

6.3VCERM-X5R0.47UF402

10K1/16W5%

R3825

402

21

C051-7173

PATA CONNECTOR

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25MMVOLTAGE=5V

Trang 35

IN

OUTOUTIN

OUT

SYM_VER-1

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

CAPS TO BE SAME DISTANCE

SATA DIFF PAIR GND VIASPLACE L3902 NEAR SB

518S0390

(TO IR RECEIVER)

NCNCNCNC

PLACE NEAR ICH7 PIN

VALUE=3900PF IN REFERENCE SCHEM

SYSTEM (SLEEP) LED FILTER

21C3903

0.0047UF

402

6036.3V2

110uFX5R

C3921

NOSTUFFC3920

1

220%

10V402CERM0.1uFNOSTUFF

24.91%

1/16W402

R39011

2

0

100

MF-LF4025%

R3900

2012H90-OHM-300mAL3901

3

12

4

CERM 16V 0.01UF

C3922

4021

2

600-OHM-300MA0402

21

L3912

CERM50V470PF

11002

402MF-LFC3950

21

6034.7UFCERM20%

90-OHM-300mA2012H3

12

4

L3902

C390221

J3901

20247-019E

20

12345

76

8910

1211

13

1514

171816

Trang 36

XTALOXTALI

SPI_DOSPI_CLKSPI_CSSPI_DI

VPD_CLKVPD_DATA

MDIP3MDIN3MDIN2MDIP2MDIN1MDIP1MDIN0MDIP0WAKE*

REFCLKN

TX_NVDDO_TTL3 VDDO_TTL2

VDD3 VDD2VDD6 VDD5 VDD4

TX_P

PU_VDDO_TTL0PU_VDDO_TTL1TEST

MEDIA LED

E2

WC*

NC0 NC1 VCC

VSS SCL SDA

ININ

IOIOIOIOIOIOIOIO

ININ

INOUT

OUTOUT

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

ASF IS UNAVAILABLE ON 8053INTERNAL PULL-UP

NCNCNCNC

NC

PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6

NC NCNC

NC

1 KEEP ENET_XTALI AND ENET_XTALO

NCNC

SCHEME MATCHES DOC MVL100258-01PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

PLACE C4107 NEAR U4101 AVDD

TRACE LENGTH <12MIL

PLACE C4140 NEAR U4102 VCC

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101SCHEME MATCHES DOC MVL100258-01

NCNC

PLACE RESISTORS CLOSE TO U4101

SCHEME MATCHES DOC MVL100258-01

PLACE C4110 AND C4111 WITHIN

12 MIL OF U4101 PIN 49 AND 50

PLACE C4113 AND C4112 WITHIN

12 MIL OF U2100 E27 AND E28

2 DO NOT ROUTE UNDER CRYSTALNC

2 150VCERM5%

402

C415115PF

0.1UF

24

656

4138

29

46

119

3435

3637

5453

16

55

4342

30262017

3127211810

63626059

2543

C41400.1UF

8

562

13

2 1X5R10%

2

C4110

402 16V

0.1UF

X5R 10%

1 10%

402 X5R 0.1UFC4111

1 2

2 1

C4112

10%

0.1UF

402 16V X5R

2 1

C4113

402 16V

0.1UF

49.9

1%

1/16W 1

1

R4120

402 1/16W 1%

1/16W 2

1

R4104

402 MF-LF 1%

49.949.9

R4105

24021 MF-LF 1%

2

1C4116

50V 402 CERM

0.001UF

2

1C4118

402 10%

0.001UF

50V CERM 2

1C41170.001UF

CERM 10%

402 50V

0.001UFC4115

2 1 402 10%

CERM 50V

2

1C4100

402 CERM 10%

1UF

FERR-120-OHM-1.5AL4100

5%

1/16W 402

R4130

MF-LF 2 1 402 1/16W 5%

R4124

NOSTUFF

MF-LF5%

4.7K

R41011

CERM10%

402

2 X5R10%

0.1UF

40216V

C4104

110%

1X5R

2 16V

0.1UFC41030.1UF

2

1C4128

40216V

0.1UF

X5R10%

2

1C41330.001UF

10%

40250VCERM 2

1C4134

50V402CERM

1C4127

16V402

2

1C4139

CERM10%

40250V

C41380.001UF

2 150V402CERM

C41370.1UF

10%

2 116V40216V

2

1C4136

40210%

C4150

150V5%

15PF

SYNC_MASTER=ENET

C051-7173

PCIE_A_R2D_N

=PP3V3_S3_ENET

=PP1V2_S3_ENET

ENET_RSET ENET_CTRL12 ENET_CTRL25

Trang 37

NC2 NC1

CHIP SIDE

SIDE LINE

NC3 NC4

NC2 NC1

CHIP SIDE

SIDE LINE

NC3 NC4

IOIO

TABLE_5_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

4

9 8

7 6 3 2

0.1UF

X5R 10%

402

C4201

1 2

402 16V

0.1UFC4203

1 2

75

1%

1/16W 402

R4200

1

2 402

MF-LF 1%

75

1/16W

R4201

1 2

1/16W

75

1%

402 MF-LF

R4202

1

2 402

MF-LF 1%

75R4203

1 2

50V40210%

CERM

0.001UFC4204

1 2

0.001UF

CERM10%

40250V

C4205

1 2

40250VCERM

0.001UFC4206

1

2 CERM

10%

40250V

0.001UFC4207

1 2

0.001UFCERM10%

402

C42111

2

0.001UF10%

CERM402

C42121

2

0402-LF

120-OHM-0.3A-EMI

21

5

78

E&E AND DELTA TRANSFORMER

10842

Trang 38

IOIOIOIOIOIOIOIO

IOIOIOIO

IOIOIOIOIOIOIOIO

IOIOIO

IOIOIOIOIOIO

IOIO

IO

OUTIN

IN

OUTOUT

IOIOIOIO

IO

IOIOIOIOIO

MPCI_ACTN_323

TPB0_PTPBIAS0PCI_AD12

R1

R0

TPA0_NTPA0_P

TPB0_NTPBIAS1TPA1_P

TPB1_PTPA1_N

TPA2_PTPA2_NTPB2_PTPB2_N

MODE_AMODE_420

TEST0TEST1PTESTSESM

PCI_AD2

PCI_AD4PCI_AD5PCI_AD3

PCI_AD6

PCI_AD11

PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20

PCI_AD23PCI_AD22

PCI_AD25

PCI_AD28PCI_AD26

PCI_AD29PCI_AD30

PCI_GNT*

PCI_PERR*

PCI_SERR*

PCI_CLKCLKRUN*

PCI_AD27PCI_AD24

PCI_AD7

PC1

IOIOIOIOIO

IO

IN

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

1 2

3 4

5 6

7 8

B C D

6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)

THIS IS FROM ICH-7MPLACE R4432 VERY CLOSE TO PIN B18 OF U2100

0.001A DURING SLEEP

PLACE ONE CAP PER TWO PINS STARTING WITH C4424 ON VDD0

7/26/2005 - CONNECTED PIN E10 TO GND

5/19/2005 - FIRST REVISION OF PAGE

6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)

FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS

PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L

PCI_AD<0 31>,PCI_C_BE_L<0 3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,

6/20/2005 - BGA VERSION OF FW323-06 ADDED

6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)

6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L

6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE

INT_PIRQD_L - INTERRUPT TO SB

PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)

FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER

PCI_RST_L - PCI RESET FROM SB

PCI_REQ3_L - PCI REQUEST TO SB

PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL

PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE

INPUT/OUTPUT

FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS

DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)

LOW = NOT BUS MANAGER

MANUFACTURING TEST PINS

NEED TO CHECK CRYSTAL LOAD CAPACITANCE

LOW = PCI OPERATION

SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)MODE FOR EXTERNAL LINK

FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS

6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE

197S0030 3.2MMX2.5MM

CONNECT TO VDD FOR 3.3V OPERATION

=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)

=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)

MOBILE TURNS OFF CONTROLLER POWER DURING SLEEP

PLACE ONE CAP PER TWO PINS STARTING WITH C4416 ON VDDA0

10UFX5R20%

402MF-LF

0.1UFCERM40220%

C4428

1

20.1UFCERM40220%

C4426

1

20.1UFCERM40220%

C4422

1

210VCERM402

0.1UF20%

C4418

1

2

40216V0.1UF10%

C4425

1

20.1UF

X5R10%

C4417

1

2

0.1UFX5R10%

R4400

X5R6.3V10UF

C44241

2

600-OHM-300MA0402

E10

E12F13F12

F10G10

L11M12M11N12M10N11M4N5N4M3H10

M2N3K4M1K2J4K1J2J1H2H12

H4H1

J13J12K13K10L12M13

K12M9L3L1

G2

N8N6

E1L2

D2

M6N10

M8

F2

E2

F1N9

M7N7G13

A4

B7A6B4

A3B3

C2C1

B9A9

B11A11

C12C11

A10B10

A12B12

D12D13

1/16W402

R44201

1/16W

22MF-LF4025%

1 3

Y4403

24.576MHZ CRITICAL

402

15pF50V5%

C4430

1

2

0.1UFCERM40220%

FIREWIRE CONTROLLER

SYNC_MASTER=ENET

PCI_TRDY_L PCI_IRDY_L PCI_FRAME_L

PCI_AD<31>

PCI_C_BE_L<2>

PP3V3_S3_FW_AVDD

VOLTAGE=3.3VMIN_LINE_WIDTH=0.5MM

FW_B_TPB_N FW_B_TPB_P FW_B_TPA_P FW_B_TPBIAS

FW_C_TPA_P FW_C_TPB_P FW_C_TPA_N FW_C_TPBIAS PCI_AD<22>

Trang 39

IOIOIOIO

TPI#

VGND VP

GD

S

DSIZE

OFSHTDRAWING NUMBER

1 2

3 4

5 6

7 8

B C D

PORT 0 1394A

Plexi: 514-0124

(PPFW_PORT0_VP)(GND_FW_PORT0_VGND)

CAPS MAY NOT BE NECESSARY

FW_TPA0_P/N,FW_TPB0_P/N,FW_TPBIAS0 - FIREWIRE DIFF PAIRS

FW_PC0 - POWER CLASS IDENTIFIER (SINGLE PORT - TIE LOW)

Page Notes

=PPBUS_FW - PORT POWER

=PP3V3_S5_FW - DIGITAL POWER

OUTPUT:

7/26/05 - CHANGED FL4590 TO 1.1A VERSION

7/26/05 - REMOVED R4520 - IT HASN’T BEEN STUFFED FOR MANY PRODUCTS

7/26/05 - SWITCHED TO 514-0124 FOR PRE-PROTO CONNECTOR

7/26/05 - CHANGED CONNECTOR PORT NAMING TO PORT0

7/26/05 - UPDATED LATE-VG POWER RAIL CIRCUIT FROM M1

5/19/05 - INITIAL REVISION

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

INPUT:

PAGE HISTORY

6/22/05 - CHANGED DIFF PAIR NAMES TO MATCH REUSE

6/22/05 - REMOVED CONSTRAINTS BECAUSE USING ALLEGRO CONST MANAGER

6/22/05 - CONNECTED FW_PC0 FOR SINGLE PORT

7/26/05 - REMOVED ETHERNET LOW-POWER MODE CIRCUIT

7/26/05 - UPDATED SIGNAL NAMES FOR FW PORT POWER ENABLE

NO STUFF FOR NOW THOUGH

1 FOR DUAL PORT

PORT POWER CLASS

0 FOR SINGLE PORT

LATE-VG PROTECTION POWER

=FWPWR_PWRON - ADDITIONAL POWER CONTROL

=GND_CHASSIS_FW_PORT0 - CHASSIS GROUND

(TPB+)(TPA+)

Enables port power whenever

or system at run state with battery only

Enclosure: 514-0289

machine AC Adapter is plugged

"Snapback" & "Late VG" Protection

2

1C4501

25V5%

402CERM

10%

0.01uF

CERM16V402

C452512

FERR-250-OHML4510

21

SM

2

1C45100.001uF

CERM50V402

4

32

4

D4521BAV99DW-X-F

SOT-363

35

D4521BAV99DW-X-F

SOT-3632

2

1C4552

NO STUFF

50VCERM

0.001uF

10%

402

2 1

1%

1/16W402

2 1

FL45901.1A-24V

4022

1

R4590470K

MF-LF4025%

1/16W

61

D4591BAS16TW-X-F

SOT-363

5 2

D4591BAS16TW-X-F

402MF-LF

470K

43

D4591BAS16TW-X-F

SOT-363

2

1

R4593100K

5%

4021/16W

2 1

R4594

402

10K

MF-LF5%

402

56.2

OMITCRITICAL

7 8 F-RT-TH1

2 1

3

Q45912N7002

SOT23-LF

2

1C452016V402

0.01UF10%

1C452110%

4020.01UFCERM

1

402CERM16V 2

C4522

0.01UF

21

CERM40216V

Q4590

FDC638PSM-LF

2

10%

603-1X7R0.01UF

2

1

R4504

4021%

21

R4550

3305%

NORMALCRITICALJ4500

1

514-0359 CONN,6P 1394A RCPT,MIDPLANE,MG3,LF

FANCYCRITICAL

1 CONN,6P 1394A RCPT,MIDPLANE,BLACK,LF J4500

514-0316

FW_PORT0_TPB_NFW_PORT0_TPB_PFW_PORT0_TPA_PPP3V3_S5_FWLATEVG

FW_PORT0_TPA_N

VOLTAGE=19VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

PPFW_SWITCH

=PP3V3_S5_FWLATEVG

FW_A_TPB_PFW_A_TPA_NFW_A_TPA_P

FW_A_TPB_NFW_A_TPBIAS

PP3V3_S5_FWLATEVG

FW_PORT0_TPB_P_FL

FW_PORT0_TPA_P_FLFW_PORT0_TPA_N_FL

FW_PORT0_TPB_N_FL

=GND_CHASSIS_FW_UPPER

=GND_CHASSIS_FW_DOWN

Tiêu đề	Apple Macbook Pro Fa255 M42c Mlb
Thể loại	Tài liệu
Năm xuất bản	2006
Thành phố	n/a

Định dạng
Số trang	79
Dung lượng	1,29 MB