fabrication technology

A thermal oxide separates adjacent transistors,chemical vapor deposition CVD silicon dioxide layers are used as dielectriclayers between the metallization levels and a PECVD plasma enhan

O Brand, School of Electrical and Computer Engineering,

Georgia Institute of Technology, Atlanta, GA, USA

Abstract

This chapter provides an overview on fabrication technologies for CMOS-basedmicroelectromechanical systems (MEMS) The first part briefly introduces the ba-sic microfabrication steps, highlights a CMOS process sequence and how CMOSmaterials can be used for microsystems design While a number of microsystemscan be fabricated within the regular CMOS process sequence, the focus of thechapter is on combining CMOS technology with micromachining process mod-ules CMOS-compatible bulk and surface micromachining techniques are intro-duced in the second part of the chapter together with an overview of the designchallenges faced when combining mechanical microstructures and electronics onthe same substrate The micromachining modules can either precede (pre-CMOS), follow (post-CMOS) or be performed in between (intra-CMOS) the regu-lar CMOS process steps The last part of the chapter provides an extensive over-view on the different CMOS-based MEMS approaches found in the literature

Keywords

Micromachining; CMOS-based MEMS; MEMS fabrication;

microsystem fabrication

1.1.1 Basic Microfabrication Steps 4

1.1.1.1 Thin Film Deposition 5

Advanced Micro and Nanosystems Vol 2 CMOS – MEMS.

Edited by H Baltes, O Brand, G K Fedder, C Hierold, J Korvink, O Tabata

Copyright © 2005 WILEY-VCH Verlag GmbH & Co KGaA, Weinheim

1.1.2 CMOS Process Sequence 9

1.1.3 CMOS Materials for Micro- and Nanosystems 11

1.2 CMOS-compatible Micromachining Process Modules 17

1.2.1 Bulk Micromachining 18

1.2.2 Surface Micromachining 22

1.3 CMOS-compatible Design of MEMS and NEMS 23

1.3.1 Tolerable Process Modifications 24

1.3.2 Design Rule Modifications 26

1.3.3 Simulation of Circuitry and MEMS 27

1.4.2 Intra-CMOS Micromachining 37

1.4.3.1 Post-CMOS Micromachining of Add-on Layers 43

1.4.3.2 Post-CMOS Micromachining of CMOS Layers 49

(sili-on a single chip An example is Apple Computer’s 64-bit PowerPC-G5 processorwith more than 58 million transistors [2], manufactured using IBM’s 90 nmCMOS technology

Researchers at IBM’s T J Watson Research Center have recently used the per-based interconnect technology of such modern CMOS processes to fabricatemicroelectromechanical devices, namely r.f switches and resonators [3, 4] Up tonow, however, most commercially available microsystems combining (microma-chined) transducer elements and integrated electronics on a single chip rely onCMOS or BiCMOS processes with minimum feature sizes typically between 0.5and 3lm and 4 or 6 in wafer sizes While the underlying CMOS technologies arebetween 10 and 15 years old, their capabilities are sufficient for most microsystemapplications An example is the pressure sensor KP100 by Infineon Technologies,

cop-a surfcop-ace micromcop-achined pressure sensor cop-arrcop-ay with on-chip circuitry for signcop-alconditioning, A/D conversion, calibration and system diagnostic, which is based

on a 0.8lm BiCMOS technology on 6 in wafers [5]

A typical cross-section of a sub-lm (0.5–1.0 lm) CMOS technology used forCMOS-based microelectromechanical systems (MEMS) is shown in Fig 1.2 [6]

The twin-well technology is based on 6 in p-type wafers and uses a cide gate, low-doped drain (LDD) technology for source and drain formation, sili-cide source/drain contacts and a two-level metallization based on tungsten plugsand aluminum interconnects A thermal oxide separates adjacent transistors,chemical vapor deposition (CVD) silicon dioxide layers are used as dielectriclayers between the metallization levels and a PECVD (plasma enhanced CVD) sili-con nitride layer or a silicon dioxide, silicon nitride sandwich are employed as pas-

polysilicon/sili-Fig 1.1 Cross-section of IBM’s 90 nm CMOS

technology 9S2 with 8-level copper

metalliza-tion (labeled M1–M8) with close-up of three

metal–oxide–semiconductor field effect

tran-sistors (MOSFETs) Images courtesy of national Business Machines Corporation; un- authorized use not permitted

Inter-Fig 1.2 Schematic cross-section of typical sub-lm (0.5–1.0 lm) CMOS ogy with two-level aluminum metallization and TiN local interconnects Adapted from [6]

technol-sivation layer The CMOS fabrication sequence is briefly highlighted in Section1.1.2 More detailed process descriptions can be found in a number of microelec-tronics textbooks, e.g [6–8].

When designing CMOS-based MEMS or microsystems, the designer must here, to a great extent, to the chosen CMOS process sequence in order not to sa-crifice the functionality of the on-chip electronics This limits the available ‘designspace’ for the integrated microsystems, as e.g materials, material properties andlayer thicknesses are determined by the CMOS process In the following, a briefintroduction into integrated circuit fabrication will be given: the basic fabricationsteps are highlighted (Section 1.1.1) and a CMOS process sequence is summa-rized (Section 1.1.2) Section 1.1.3 discusses how the different CMOS materialsand layers can be used in micro- and nanosystems and Section 1.1.4 depicts a fewmicrosystems that can be completely formed within a regular CMOS sequence

ad-1.1.1

Basic Microfabrication Steps

The fabrication of integrated circuits (ICs) using CMOS or BiCMOS technology isbased on four basic microfabrication techniques: deposition, patterning, dopingand etching Fig 1.3 illustrates how these techniques are combined to build up an

IC layer by layer: a thin film, such as an insulating silicon dioxide film, is ited on the substrate, a silicon wafer A light-sensitive photoresist layer is then de-posited on top and patterned using photolithography Finally, the pattern is trans-ferred from the photoresist layer to the silicon dioxide layer by an etching process.After removing the remaining photoresist, the next layer is deposited and struc-

depos-Fig 1.3 Flow diagram of IC tion process using the four basic mi- crofabrication techniques: deposi- tion, photolithography, etching and doping Adapted from [8]

fabrica-tured, and so on Doping of a semiconductor material by ion implantation, thekey step for the fabrication of diodes and transistors, can be performed directlyafter photolithography, i.e using a photoresist layer as mask, or after patterning

an implantation mask (e.g a silicon dioxide layer)

Silicon is the standard substrate material for IC fabrication and, hence, the most

common substrate material in microfabrication in general It is supplied as gle-crystal wafers with diameters between 100 and 300 mm In addition to its fa-vorable electrical properties, single-crystal silicon also has excellent mechanicalproperties [9], which enable the design of micromechanical structures CMOS pro-cesses for digital electronics typically use low-doped (doping concentration in the

sin-1016cm–3range) silicon wafers, whereas processes for mixed-signal or analog tronics are often based on high-doped (doping concentration in the 1019cm–3range) wafers with a low-doped epitaxial layer to minimize latch-up The choice ofthe substrate material might already require a compromise between the require-ments for the MEMS part and the on-chip electronics: the fabrication of mem-brane structures for, e.g., pressure sensors is typically based on anisotropic siliconetching in a potassium hydroxide (KOH) solution (see Section 1.2) High p-type

elec-doping (NA³1019

cm–3) substantially reduces the silicon etch rates in KOH tions, thus preventing the use of highly p-doped CMOS substrates in combinationwith KOH etching

solu-In the following, a brief overview on the four basic microfabrication steps will

be given More details can be found in textbooks and reference books on ductor processing [6–8, 10, 11]

semicon-1.1.1.1 Thin-film Deposition

The two most common thin-film deposition methods in microfabrication are

chemical vapor deposition (CVD), performed at low pressure (LPCVD), atmospheric pressure (APCVD) or plasma-enhanced (PECVD), and physical vapor deposition

(PVD), such as sputtering and evaporating Typical CVD and PVD film nesses are in the range of tenths of nanometers up to a few micrometers Otherfilm deposition techniques include electroplating of metal films (e.g the coppermetallization in state-of-the-art CMOS processes) and spin- or spray-coating ofpolymeric films such as photoresist Both processes can yield film thicknessesfrom less than 1lm up to several hundreds of micrometers

thick-Dielectric layers, predominantly silicon dioxide, SiO2, and silicon nitride, SiNx,are used as insulating material, as mask material and for device passivation Sili-con dioxide is either thermally grown on top of a silicon surface (thermal oxide)

at high temperatures (900–12008C) in an oxidation furnace or it is deposited in aCVD system (CVD oxide) CVD oxides can be deposited at temperatures between

300 and 9008C, with the high-temperature depositions usually yielding better filmproperties Low-temperature CVD oxide films are typically deposited in PECVDsystems and high-temperature CVD oxide films in LPCVD equipment Silicon ni-tride layers deposited in LPCVD furnaces are commonly used as masking

material during local oxidation of silicon (LOCOS process), while PECVD siliconnitride films are used for e.g device passivation.

Highly doped polycrystalline silicon (polysilicon) is used as gate material for

me-tal oxide semiconductor field effect transistors (MOSFETs), as electrode and tor materials, for piezoresistive sensing structures, as thermoelectric material, andfor thermistors Polysilicon microstructures released by sacrificial layer etching arealso widely used in sensor applications (see Section 1.4) Polysilicon is usually de-posited in an LPCVD furnace using silane (SiH4) as gaseous precursor

resis-Metal layers are used, e.g., for electrical interconnects, as electrode material, for

resistive temperature sensors (thermistors) or as mirror surfaces Metals, whichare widely used in the microelectronics industry, such as aluminum, titanium andtungsten, are routinely deposited by sputtering Depending on the application, alarge number of other metals, including gold, palladium, platinum, silver or al-loys, can be deposited with PVD methods A number of metals and metal com-pounds, such as Cu, WSi2, TiSi2, TiN and W, can be deposited by CVD MetalCVD processes are less common, but can provide improved step coverage or localdeposition of metals Whereas aluminum has been the standard metallization in

IC fabrication for many years, the state-of-the-art sub-0.25lm CMOS technologiesoften feature copper as interconnect material, owing to its lower resistivity andhigher electromigration resistance as compared with aluminum An example isIBM’s interconnect metallizations based on the so-called damascene process [12],which employ copper films electroplated in a dielectric mold After each metalliza-tion step, planarization is achieved with a chemical–mechanical polishing (CMP)step

Polymers such as photoresist are commonly deposited by spin- or spray-coating.

Polymers can be used as dielectric materials, passivation layers, and as chemicallysensitive layers for chemical and biosensors ([13]; see also Chapter 7)

1.1.1.2 Patterning

Photolithography is the standard process to transfer a pattern, which has been signed with computer-aided-engineering (CAE) software packages, on to a certainmaterial The process sequence is illustrated in Fig 1.4 A mask with the desiredpattern is created The mask is a glass plate with a patterned opaque layer (typi-cally chromium) on the surface Electron-beam lithography is used to write themask pattern from the CAE data In the photolithographic process, a photoresistlayer (photostructurable polymer) is spin-coated on to the material to be pat-terned Next, the photoresist layer is exposed to ultraviolet (UV) light through themask This step is done in a mask aligner, in which mask and wafer are alignedwith each other before the subsequent exposure step is performed Depending onthe mask aligner generation, mask and substrate are brought in contact or closeproximity (contact and proximity printing) or the image of the mask is projected(projection printing) on to the photoresist-coated substrate Depending onwhether positive or negative photoresist was used, the exposed or the unexposedphotoresist areas, respectively, are removed during the resist development process

de-The remaining photoresist acts as a protective mask during the subsequent ing process, which transfers the pattern onto the underlying material Alterna-tively, the patterned photoresist can be used as a mask for a subsequent ion im-plantation After the etching or ion implantation step, the remaining photoresist

etch-is removed, and the next layer can be deposited and patterned

The so-called lift-off technique is used to structure a thin-film material, which

would be difficult to etch Here, the thin-film material is deposited on top of thepatterned photoresist layer In order to avoid a continuous film, the thickness ofthe deposited film must be less than the resist thickness By removing the under-neath photoresist, the thin-film material on top is also removed by ‘lifting it off’,leaving a structured thin film on the substrate

Thick photostructurable polymer layers, such as SU-8 [14], can be used as amold for electroplating metal structures A thick polymer layer is deposited on top

of a metallic seed layer and photostructured During the subsequent electroplatingprocess, the metal is only deposited in the areas where the seed layer is exposed

to the plating solution, i.e the polymer layer acts as a plating mold

Recently, microcontact printing or soft lithography [15] has been introduced as

an additional method for pattern transfer A soft polymeric stamp is used to duce a desired pattern directly on a substrate Routinely, feature sizes on the or-der of 1lm can be achieved with this technique The polymer stamp, often madefrom poly(dimethylsiloxane) (PDMS), is formed by a molding process using amaster fabricated with conventional microfabrication techniques After ‘inking’the stamp with the material to be printed, the stamp is brought in contact withthe substrate material, and the pattern of the stamp is reproduced Surface proper-

repro-Fig 1.4 Schematic of a

photolithographic process

se-quence to structure a

thin-film layer

ties of the substrate can therefore be modified to, e.g., locally promote or preventmolecule adhesion Soft lithography has been specifically developed for biologicalapplications such as patterning cells or proteins with the help of, e.g., self-as-sembled monolayers (SAMs) [15].

1.1.1.3 Etching

The two different categories of etching processes include wet etching using liquidchemicals and dry etching using gas-phase chemistry Both methods can be eitherisotropic, i.e provide the same etch rate in all directions, or anisotropic, i.e providedifferent etch rates in different directions (see Fig 1.5) The important criteria forselecting a particular etching process encompass the material etch rate, the selectivityfor the material to be etched, and the isotropy/anisotropy of the etching process Anoverview on various etching chemistries used in microfabrication can be found in [16].Wet etching is usually isotropic with the important exception of anisotropic sili-con wet etching in, e.g., alkaline solutions, such as potassium hydroxide (see Sec-tion 1.2) Moreover, wet etching typically provides a better etch selectivity for thematerial to be etched in comparison with neighboring other materials An exam-ple includes wet etching of silicon dioxide using hydrofluoric acid-based chemis-tries SiO2is isotropically etched in dilute hydrofluoric acid (HF–H2O) or bufferedoxide etch, BOE (HF–NH4F) Typical etch rates for high-quality (thermally grown)silicon dioxide films are 0.1lm/min in BOE

Dry etching, on the other hand, is often anisotropic, resulting in a better patterntransfer, as mask underetching is avoided (see Fig 1.5) Therefore, anisotropic dry

etching processes, such as reactive ion etching (RIE), of thin-film materials are very

common in the microelectronics industry In an RIE system, reactive ions are erated in a plasma and are accelerated towards the surface to be etched, thus provid-ing directional etching characteristics Higher ion energies typically result in moreanisotropic etching characteristics, but also in reduced etching selectivity

gen-Fig 1.5 Schematic of isotropic and anisotropic thin-film etching

1.1.1.4 Doping

Doping is used to modify the electrical conductivity of semiconducting materialssuch as silicon or gallium arsenide It is hence the key process step for fabricatingsemiconductor devices such as diodes and transistors In the case of silicon, dop-ing with phosphorus or arsenic yields n-type silicon, whereas p-type silicon resultsfrom boron doping By varying the dopant concentration of n-type silicon from

1014to 1020cm–3, the resistivity at room temperature can be tuned from mately 40 to 7´10–4X cm

approxi-Dopant atoms are introduced by either ion implantation or diffusion from agaseous, liquid or solid source Ion implantation has become the key process tointroduce precisely defined quantities of dopants in the microelectronics industry.The substrate material, i.e a silicon wafer, is bombarded with accelerated ionizeddopant atoms in an ion implanter The result is approximately a Gaussian distri-bution of the dopant atoms in the substrate wafer with a mean penetration depthcontrolled by the acceleration voltage A high-temperature diffusion process canthen be used to additionally ‘drive-in’ the dopant until a desired doping profile hasbeen achieved

1.1.2

CMOS Process Sequence

To be able to integrate microelectromechanical devices with CMOS circuitry, thedesigner must have an excellent understanding of the underlying CMOS processsequence The particular process flow is, of course, strongly dependent on thechosen CMOS technology and a detailed description of a CMOS technology goesway beyond the scope of this chapter Nevertheless, we briefly summarize a typi-cal CMOS process sequence in the following, highlighting the main process stepsand their importance for co-integration of CMOS and MEMS We thereby followthe CMOS process sequence described in detail in [6] (see schematic cross-section

in Fig 1.2), which is typical for a sub-lm technology with minimal feature sizesbetween 0.5 and 1lm

The starting wafer material is a lightly p-doped (100) wafer with a typical

dop-ing concentration of NA&1015

cm–3 The first step is the definition of the activeareas by local oxidation of silicon (LOCOS), thus growing a thick (*0.5 lm) fieldoxide in the areas between the individual transistors Next, the p-wells for the n-channel MOSFETs and the n-wells for the p-channel MOSFETs are implanted Ajoint drive-in for both wells establishes the desired junction depth of 2–3lm Typ-ical drive-in times are 4–6 h at 1000–11008C We will see later (Section 1.2) thatthe n-well diffused in the p-substrate can be used to define accurately the thick-ness of a silicon membrane Such membranes are commonly released by aniso-tropic wet etching from the back of the wafer using an electrochemical etch-stoptechnique at the p–n junction between n-well and p-substrate [17, 18]

After n- and p-well formation, the MOSFET gate and channel regions are neered First, channel implants for the n- and the p-channel transistors are im-planted to adjust their threshold voltages to the desired values After removing the

engi-implantation oxides in the active area, the gate oxide with a thickness£10 nm inmodern CMOS processes is thermally grown in the active areas Next, a 0.3–0.5lm thick polysilicon layer for the gate electrodes is deposited across the wafer

in an LPCVD furnace operating at about 6008C and doped by ion implantation.Finally, the polysilicon layer is patterned to define the actual gate regions InMEMS, the gate polysilicon can also be used for resistors, piezoresistors, thermo-piles, electrodes and as structural materials The last application often requires ahigh-temperature anneal of the polysilicon to reduce its residual stress to valuesacceptable for the microstructures Such a high-temperature step can be critical atthis stage in the CMOS process, as it might effect previous doping distributionsand, hence, the CMOS device characteristics

After gate formation, the source/drain regions are implanted In typical sub-lmCMOS technologies, this is done using a LDD (lightly doped drain) process It pro-vides a gradient in the doping of the source/drain regions towards the channel re-gion, reducing the peak value of the electric field close to a channel and, hence, in-creasing device reliability First, phosphorus (or arsenic as alternative n-type dopant)

is implanted in the source/drain of the NMOS transistors to form n–regions, lowed by a boron implantation of the source/drain of the PMOS transistors to form

fol-p–regions Next, a conformal spacer dielectric layer is deposited on the wafer andanisotropically etched back, leaving sidewall spacers along the edges of the polysili-con gates After growing a thin screen oxide for the following implantation, thesource/drain regions of the NMOS and PMOS transistors not protected by the side-wall spacer are successively implanted to form n+and p+regions, respectively Thefinal step of the source/drain engineering is a furnace anneal, typically at*9008Cfor 30 min, to activate the implants, anneal implant damage and drive the junctions

to their final depth Alternatively to the furnace anneal, a much shorter rapid mal anneal at higher temperatures can be performed (e.g 1 min at 1000–10508C).The fabrication of the active devices is now completed Any subsequent high-tem-perature step (above 700–8008C) necessary for the MEMS fabrication must be care-fully qualified, as it might affect the doping distributions in the active devices, thuspotentially changing the device characteristics

ther-In the back end of the process, the individual active devices are interconnected

on the wafer to form circuits and pads for input/output connections off the chipare created Although a large number of back-end metallization process flowswith up to eight metallization levels exist, the exemplary CMOS process described

in [6] uses three metallization levels with a local interconnect level based on nium nitride and two wiring levels based on aluminum The contacts to thesource/drain regions and to the gate polysilicon are based on titanium silicide(TiSi2) To this end, a thin titanium layer (50–100 nm) is sputtered on the waferafter removal of the implantation oxide During an annealing step at about 6008C

tita-in N2, the titanium reacts with Si where they are in contact (e.g source, drainand gate polysilicon) to form TiSi2and with N2to form TiN elsewhere The result-ing TiN layer is patterned to create a local interconnect Subsequently, the wafersurface is typically planarized using a PSG (phosphosilicate glass) or BPSG (boro-phosphosilicate glass) layer reflown at 800–9008C Modern CMOS processes often

use chemical mechanical polishing (CMP) for interconnect and interconnect electric planarization In the process described in [6], each of the following wiringlevels uses CVD tungsten vias with a TiN adhesion/barrier layer and an alumi-num (with a small percentage of Si and Cu) interconnect layer Finally, the passi-vation layer is deposited (typically by PECVD) and patterned to form the padopenings necessary to contact the device from the outside The composition of thepassivation layer and especially its residual stress can be adapted according to theneeds of the microstructures (see Section 1.3.1) After passivation, the wafers areannealed at low temperatures (400–4508C) for about 30 min in forming gas (10%

di-H2in N2) to alloy the metal contacts

The CMOS process presented in [6] and briefly described here requires 16masks A schematic device cross-section is shown in Fig 1.2

1.1.3

CMOS Materials for Micro- and Nanosystems

The particular CMOS technology chosen for the implementation of a micro- ornanoelectromechanical system (MEMS or NEMS) dictates the overall process se-quence, the doping profiles and junction depths of doped silicon regions, and thematerial properties and thicknesses of the different thin-film layers In general,only minimal adaptations can be made in order not to compromise the perfor-mance of the CMOS circuits (see Section 1.3) However, the different layers of theCMOS process can be used for the fabrication of the microstructures themselves.Tab 1.1 summarizes the different doping regions and layers of a typical CMOSprocess and their use in MEMS and NEMS

Two examples, namely a CMOS-based mass-sensitive chemical sensor [19–21]and a CMOS-based thermal imager [22, 23], will be discussed in the following.The mass-sensitive chemical sensor (see Fig 1.6) is based on a 150lm long and

140lm wide cantilever beam consisting of the n-well of the CMOS process ered by the CMOS dielectrics [21] Thus, the n-well and the CMOS dielectrics areused as structural materials The cantilever is released after completion of theCMOS process by three post-CMOS micromachining steps: first, a silicon mem-brane is formed by anisotropic wet etching from the back of the wafer in combi-nation with an electrochemical etch-stop technique at the p–n junction between p-substrate and n-well; thereafter, the cantilever is released by two reactive ion etch-ing (RIE) steps The two aluminum metallization layers are used to form a planarcoil on top of the cantilever, enabling the generation of transverse vibrations inthe presence of an external DC magnetic field parallel to the cantilever length.The transverse vibration are detected with stress-sensitive diode-connected PMOStransistors, arranged in a Wheatstone bridge configuration at the cantilever’sclamped edge Alternatively, piezoresistors can be formed using either the p+-source/drain implantation of a PMOS transistor or the n+-doped gate polysilicon.The cantilever beam is coated with a chemically sensitive polymer layer Upon ab-sorption of analyte in the polymer layer, the cantilever’s mass increases and,hence, its resonance frequency decreases The change of resonance frequency is

cov-sensed by incorporating the resonant cantilever into an amplifying feedback loop[20, 21].

The thermal imager shown in Fig 1.7 is based on a *3´3 mm2 membraneconsisting of the dielectric layers of the CMOS process [22, 23] The membrane isreleased by wet anisotropic silicon etching from the back of the wafer after com-pletion of the regular CMOS process sequence The thick field oxide is used as anintrinsic etch-stop layer The CMOS dielectrics, i.e the field oxide, the contact ox-ide, the intermetal oxide and the passivation, are used as structural materials Agrid of electroplated gold lines provides additional structural support to the mem-brane and divides it into 100 pixels The gold lines are electroplated after theCMOS process in a standard process step normally preparing the wafers for TAB(tape automated bonding) Sandwiched in between the CMOS dielectrics on eachpixel is a polysilicon/aluminum thermopile and a polysilicon heating resistor The

Tab 1.1 Common CMOS materials and their use in micro- and nanoelectromechanical systems (MEMS and NEMS)

CMOS layer/structure Use in MEMS and NEMS

Thermal conductor/mass

Piezoresistor Thermopile Electrode

Thermal insulator Sacrificial material Gate polysilicon

(and optional 2nd polysilicon)

Resistor Piezoresistor Thermopile Electrode Structural material Sacrificial material

Thermal insulator Sacrificial material Metallization

(and optional multi-level metallizations)

Conductor Mirror Thermal conductor Electrode

Structural material Sacrificial material

Thermal insulator Stress compensation Infrared radiation absorber

incoming infrared (IR) radiation is absorbed in the CMOS thin-film sandwich

Fig 1.6 (a) Photograph and (b) schematic

cross-section of a cantilever-based

mass-sen-sitive gas sensor The cantilever structure

fea-tures an integrated planar coil for

electromag-netic excitation of transverse vibrations in the

presence of a DC magnetic field and PMOS transistors in a Wheatstone bridge arrange- ment for deflection detection [21] Photograph courtesy of C Vancura, ETH Zurich, Switzer- land

Fig 1.7 (a) Photograph and (b) schematic

cross-section of a CMOS-based infrared

radia-tion sensor array The sensor array is located

on a micromachined membrane consisting of

the dielectric layers of the CMOS process An

electroplated gold grid divides the membrane

in a 10 ´10 array of pixels, each incorporating

a thermopile with 16 polysilicon/aluminum thermocouples for temperature sensing On- chip circuitry includes a multiplexer and a low-noise chopper amplifier [22, 23] Photo- graph courtesy of Prof H Baltes, ETH Zurich, Switzerland

(including the passivation), resulting in a measurable temperature elevation of theindividual pixels All structures necessary for IR radiation sensing are completelyformed within the regular CMOS process sequence [22, 23].

1.1.4

CMOS Microsystems

A number of microsensors can be completely formed within the regular CMOSprocess sequence, typically not requiring any additional process steps Well-knownexamples include temperature sensors [24, 25], magnetic field sensors (especiallyHall sensors) [26] and CMOS imagers [27, 28] An additional subset of CMOS-based microsystems only requires either the modification of a CMOS layer or thedeposition and patterning of additional layers, but no micromachining steps Afew selected examples will be given in the following

Chemical sensors and biosensors relying on an electrochemical sensing ple require an electrode in contact with the sample to be sensed Examples in-clude amperometric sensors, palladium-gate FET and ISFET (ion-sensitive field ef-fect transistor) structures, and also chemoresistors and chemocapacitors A num-ber of these electrochemical sensors have been co-integrated with CMOS circuitry(see Chapter 7), typically requiring deposition and patterning of special metal elec-trodes and/or passivation layers in addition to the regular CMOS process se-quence

princi-Examples are the CMOS-based biosensor arrays developed recently for DNAanalysis [29, 30] and recording of neural activity [31] The sensor arrays are based

on a standard 0.5lm CMOS process optimized for analog applications [30] Afterdeposition and patterning of the second aluminum layer, a silicon dioxide layer isdeposited, followed by a planarization step using CMP and the deposition of a sili-con nitride passivation The actual sensor electrodes are fabricated on top of thenitride passivation First, vias are etched to enable contacts to the aluminum me-tallization and are filled with a Ti/TiN barrier layer and CVD tungsten [30] In thecase of the DNA arrays, the final interdigitated gold electrodes are deposited byevaporation of a Ti/Pt/Au electrode stack, which is patterned using a lift-off tech-nique ([30]; see Fig 1.8) In the case of the sensor arrays for neural activity record-ing, the sensor electrodes and the contact pads are defined by depositing and lift-off patterning of a Ti/Pt layer Subsequently, a dielectric layer sandwich consisting

of different TiO2 and ZrO2 layers is deposited and opened at the location of thebond pads Neural activity is recorded capacitively with the sensor electrodes cov-ered by the protective dielectric layer sandwich Finally, a gold layer is deposited

on the Pt pads and structured using a lift-off process [31]

Researchers at ETH Zurich have recently reported a CMOS-integrated electrode array for stimulation and recording of natural neural networks [32] Themicrosystem is fabricated using a 0.6lm CMOS process in combination with atwo-mask post-CMOS process sequence to deposit and pattern biocompatible plati-num electrodes The post-CMOS process sequence starts with the deposition andpatterning of 50 nm TiW and 270 nm Pt The metal layer sandwich is structured

micro-using a lift-off technique Finally, a 1lm silicon nitride sealing layer is deposited

by PECVD and patterned with RIE

A CMOS-based biochemical multisensor microsystem requiring no chining has been developed by IMEC, K U Leuven and Siemens [33] The micro-system combines, on a single CMOS chip, an array of ISFETs, an amperometricoxygen sensor and a conductometric cell The biochemical analysis system isbased on double-metal, 1.2lm CMOS technology A special ISFET module hasbeen integrated into the regular CMOS process sequence to form a protectiveLPCVD nitride layer on top of the ISFET gates In addition, Ti/Pt electrodes forthe amperometric sensor are deposited and patterned and Ag/AgCl reference elec-trodes are formed by electroplating and electrochloridation [33, 34] ISFET struc-tures requiring no modifications to the CMOS process sequence have been pre-sented in [35]

microma-Capacitive chemical microsensors based on interdigitated metal electrodes can

be fabricated completely within the regular CMOS process sequence Examples clude microsensors for detection of humidity [36, 37] and volatile organic com-pounds in air [38, 39] Typically, the interdigitated electrode structure is formed bythe metallization layers of the CMOS process The capacitive sensor structure de-tects changes in the dielectric constant of a sensing layer deposited on top of itupon absorption of analyte molecules CMOS-integrated capacitive humidity sen-sors are produced by Sensirion, Switzerland [40, 177]

in-Hall plates can be formed completely within a regular (Bi)CMOS process quence and Hall sensor systems with on-chip circuitry are commercially available,e.g from Micronas [41], Infineon Technologies [42], Allegro Microsystems [43]and Melexis [44] Regular Hall plates are arranged parallel to the chip surface andare sensitive to magnetic fields perpendicular to the chip surface Using spinning-current methods for offset reduction, commercially available CMOS integratedHall sensors have offsets as low as 0.5 mT [45] To improve sensor performance,i.e sensitivity and offset, the Hall sensors have been combined with integratedmagnetic flux concentrators by bonding and patterning thin high-permeability,

se-Fig 1.8 (a) Photograph of an 8´4 element

DNA sensor array with a single sensor

diame-ter of 200 lm and a sensor pitch of 400 lm;

(b) SEM photograph of sensor cross-section

showing the standard CMOS metallization, the tungsten vias and the gold sensor electro- des Adapted from [30]

low-coercivity ferromagnetic layers to the chip surface [46] In addition to trating the magnetic flux at the location of the Hall sensors, the flux concentra-tors allow the measurement of magnetic fields in the chip plane with standard lat-eral Hall sensors [46] Alternatively, magnetic fields parallel to the chip surfacecan be sensed by vertical Hall sensors, rotated 908 to the chip surface [47, 238].Recently, CMOS-based vertical Hall sensors have been fabricated by developing apre-CMOS trench etching technology to define the geometry of the Hall plates([47]; see Section 1.4.1).

concen-Ferromagnetic films not only are used in combination with Hall sensors, butare also essential for highly sensitive fluxgate sensors The operation of a fluxgatesensor requires a ferromagnetic core which needs to be saturated periodically bythe control circuitry CMOS-based fluxgate sensors with minimal detectable mag-netic fields in the nanotesla range (typical noise levels in the range 5–100 nT/Hz

p

) have been demonstrated at the Fraunhofer Institute IMS [48, 49], ETH rich [50, 51] and EPF Lausanne [52] In [49], a ferromagnetic Ni81Fe19core is em-bedded in the intermetal dielectrics between the two metallization layers of aCMOS process In this way, the required excitation and pick-up coils consisting ofmetal-1 and metal-2 lines can be wound around the core The electron beam-eva-porated nickel–iron cores are sandwiched between tantalum layers, serving as ad-hesion layers and diffusion barriers The metal sandwich is patterned using lift-off techniques In [50, 51], two 1lm thick ferromagnetic NiFeMo cores are elec-troplated on top of the CMOS chip Finally, the approach presented in [52] uses asoft-magnetic amorphous alloy (Metglas 2714A, Honeywell), which is mounted ontop of the CMOS die and structured using a photolithographic process

Zu-The final two examples both require a direct contact with the surface of aCMOS chip during sensing Fingerprint sensors are used for access control andauthentication and are covered in detail in Chapter 8 In the case of a capacitivesensor, a two-dimensional electrode array measures the capacitance between thechip surface and the finger’s surface touching the chip with a resolution of typi-cally 500 dpi The fingerprint sensor developed by Siemens is based on a double-metal, 0.8lm CMOS process and features, on a single chip, a 256´256 pixel sen-sor array with a pitch of 50lm, the necessary data acquisition circuitry, A/D con-version and a parallel interface [53] The sensor is protected against electrostaticair discharge, caused by touching the sensor with a charged finger, using agrounded refractory metal grid (see Chapter 8)

Wire bonding remains the predominant method for providing electrical connections between chip and substrate Increasing bonding speed paired with de-creasing pad-pitch requires careful optimization of the wire bonding process and

inter-a profound understinter-anding of the physicinter-al processes occurring during the inter-actuinter-albonding process Recently, CMOS-based force sensors have been developed for insitu investigation of the forces acting on the bond pad during thermosonic ball-

wedge wire bonding [54, 55] The test chips comprise an array of xyz-force sors connected to a multiplexer (see Fig 1.9) Each xyz-sensor features three Wheatstone bridges with piezoresistors to measure the x, y and z-components of

sen-the force acting on sen-the bond pad during sen-the wire bonding process The p+and n+

source/drain implantations of a double-metal, 0.8lm CMOS process are used toform the piezoresistors surrounding the bond pad Hence, the force sensors can

be completely formed within the regular CMOS process sequence, potentially lowing the implementation of bonding test structures into regular CMOS designs

al-In all of the above cases, no micromachining steps are involved The focus ofthe remainder of this chapter (and the main focus of this book) is on CMOS-based micro- and nanosystems requiring either bulk or surface micromachining

to release micromechanical structures

1.2

CMOS-compatible Micromachining Process Modules

The basic microfabrication processes described earlier are often combined withspecial micromachining steps to produce (three-dimensional) microstructures,such as cantilevers, bridges and membranes In the following, the fundamentalmicromachining techniques are reviewed More details on micromachining tech-niques can be found in dedicated books on microsystem technology [56–59]

The micromachining techniques are categorized into bulk micromachining [60]and surface micromachining processes [61] (see Fig 1.10) In the case of bulk mi-cromachining, the microstructure is formed by machining the relatively thickbulk substrate material, whereas in the case of surface micromachining, the mi-crostructure comprises thin-film layers, which are deposited on top of the sub-strate and selectively removed in a defined sequence to release the MEMS struc-ture

Fig 1.9 Test chip with 48xyz-force sensors

connected to a multiplexed bus; the close-up

of onexyz-force sensor shows the test pad

with a size of 65 lm and the surrounding piezoresistors forx, y and z-force sensing [54]

Bulk Micromachining

Bulk micromachining techniques [60], i.e etching techniques to machine the icon) substrate, can be classified into isotropic and anisotropic, and into wet anddry etching techniques, as can be seen in Tab 1.2

(sil-The most common isotropic wet silicon etchant is HNA, a mixture of

hydrofluo-ric acid (HF), nithydrofluo-ric acid (HNO3), and acetic acid (CH3COOH) In this etching tem, nitric acid oxidizes the silicon surface and hydrofluoric acid etches thegrown silicon dioxide layer The acetic acid controls the dissociation of HNO3,which provides the oxidation of the silicon The etch rates and the resulting sur-face quality strongly depend on the chemical composition [58]

sys-Anisotropic wet etching of silicon is the most common micromachining

tech-nique and is used to release, e.g membrane and beam structures Anisotropicwet etchants etch single-crystalline silicon with different etch rates along differentcrystal directions The resulting etch grooves are bound by crystal planes, alongwhich etching proceeds at slowest speed, i.e the (111) planes of silicon In case ofthe commonly used (100) silicon wafers, the (111) planes are intersecting the wa-

Fig 1.10 Schematic of (a) bulk and (b) surface micromachining

Tab 1.2 Examples of etching techniques for machining the silicon substrate

HF–HNO3–CH3COOH

Vapor-phase etching XeF2

KOH, NaOH Ammonium hydroxide solutions (CH3)4NOH (TMAH), NH4OH EDP solutions

Other solutions, e.g hydrazine

Plasma etching RIE, deep-RIE

fer surface at an angle of 54.78, yielding the typical pyramid-shaped etch groovesshown in Fig 1.11 Masking materials for anisotropic silicon etchants are silicondioxide and silicon nitride It is important to note that ‘convex’ corners of the etchmask (as shown in Fig 1.11) are underetched in the case of (100) silicon sub-strates, leading to, e.g., completely underetched cantilever structures The etchrates in preferentially etched crystal directions such as theh100i and the h110i di-rections, and the ratio of the etching rates in different crystal directions dependstrongly on the exact chemical composition of the etching solution and the pro-cess temperature [57, 58, 60, 62].

The most common anisotropic silicon etching solution is potassium hydroxide,KOH As an example, a 6-M KOH solution at 958C provides a h100i etch rate of

150lm/h and an anisotropy, i.e etch rate ratio, between the h100i and h111i rections of 30–100 : 1 [63] Since the etch rate of silicon dioxide in KOH solutions

di-is fairly high (for thermal oxide *1 lm/h in 6 M KOH solution [58]), silicon tride films are often used as etching mask KOH solutions are very stable, yieldreproducible etching results and are relatively inexpensive KOH is, therefore, themost common anisotropic wet etching chemical in industrial manufacturing Thedisadvantages of KOH include the relatively high SiO2and Al etch rates, which re-quire protection of IC structures during etching Etching with KOH is typicallyperformed from the back of the wafer, with the front side protected by a mechani-cal cover and/or a protective film [63] Another issue is the detrimental impact of

ni-Fig 1.11 (a) Schematic of a cantilever beam

released by anisotropic silicon etching from

the front side of the wafer The etching mask

defines the cantilever shape The

underetch-ing of the cantilever structure starts at convex

corners The resulting etch groove is bound

by characteristic (111) side walls and a (100)

bottom surface (b) SEM photograph showing

two bulk-micromachined thermal converters cointegrated with CMOS circuitry The devices are released from the front side of a CMOS wafer by combining anisotropic silicon etch- ing using TMAH with an electrochemical etch-stop technique SEM photograph cour- tesy of Prof G T A Kovacs, Stanford Univer- sity, USA

alkali metal ions on the characteristics of MOSFET structures Investigation ofMOSFET characteristics after KOH etching from the back of CMOS wafers, how-ever, did not reveal any etching-related damage [63].

Alternative silicon etchants are ammonium hydroxide compounds, such as ramethyl ammoniumhydroxide (TMAH), and ethylenediamine–pyrocatechol(EDP) solutions Certain EDP formulations, such as EDP type S, exhibit relativelylow Al and SiO2 etch rates, which make them suitable for releasing microstruc-tures from the front side of CMOS wafers [232] However, EDP solutions age rap-idly, are potentially carcinogenic and are very difficult to dispose of TMAH solu-tions exhibit similar etching characteristics to EDP, but are easier to handle Bycontrolling the pH by, e.g., dissolving silicon in the etching solution, the etch ratefor aluminum metallizations can be reduced [60, 64], making TMAH also a candi-date etchant for releasing microstructures from the front side of CMOS wafers.More detailed discussions of wet etching of silicon can be found, e.g., in [57, 58].Reliable etch stop techniques are very important for achieving reproducibleetching results As already mentioned, wet anisotropic silicon etchants ‘stop’ etch-ing, i.e the etch rate is reduced by at least 1–2 orders of magnitude, as soon as a(111) silicon plane or a silicon dioxide (or silicon nitride) layer is reached In addi-tion, the etch rate is greatly reduced in highly boron doped regions (doping con-centration³1019cm–3) The etching can also be stopped at a p–n junction using aso-called electrochemical etch stop technique (ECE) [56, 65] This method hasbeen extensively used to release silicon membranes and n-well structures (seeFig 1.12) ECE relies on the passivation of silicon surfaces when an anodic poten-tial is applied that is sufficiently high with respect to the potential of the etchingsolution

tet-Fig 1.12 Micrograph of an anisotropically

etched cavity of a capacitive chemical

micro-system (see Chapter 7, Fig 7.32) At the

bot-tom of the cavity, an n-well island structure

carrying a thermally stabilized

capa-citive sensor [67] is visible The n-well is pended by a membrane consisting of the CMOS dielectric layers (the embedded metal interconnects connecting the sensor are clearly visible)

sus-Isotropic dry etching of silicon can be done using xenon difluoride, XeF2 This por-phase etching method exhibits excellent etch selectivity with respect to alumi-num, silicon dioxide, silicon nitride and photoresist, all of which can be used asetch masks However, the resulting etched silicon surfaces are fairly rough TheXeF2 silicon etch rates depend on the loading (size of the overall silicon surfaceexposed to the etchant) with typical values of*1 lm/min XeF2etching systemsare commercially available from XACTIX [66] (Alternatively, reactive ion etching

va-(RIE) can be used for isotropic dry etching see also anisotropic dry etching below) Anisotropic dry etching of silicon is usually performed by reactive ion etching

(RIE) in plasma-assisted etching systems By controlling the process parameters,such as process gases and process pressure, the etching can be rendered eitherisotropic or anisotropic The dry-etching anisotropy mainly originates from the di-rection of ion bombardment, and is, therefore, independent of the crystal orienta-tion of the substrate material Most bulk etching of silicon is accomplished usingfluorine free radicals with SF6 as a typical process gas Adding chlorofluorocar-bons results in polymer deposition in parallel with etching, which leads to en-hanced anisotropy

Very high aspect ratio microstructures can be achieved with deep (D)RIE, amethod which has gained importance during recent years DRIE systems rely onhigh-density plasma sources and an alternation of etching and polymer-assistedsidewall protection steps In a process known as the Bosch process [68], a mixture

of trifluoromethane and argon is used for polymer deposition Owing to the ion

Tab 1.3 Comparison of characteristics of common bulk silicon etchants; the etch rates given are typical numbers, the actual etch rates depend on the process parameters (sources for etch- ing rates and selectivities: HNA [9, 58], KOH [58], TMAH [57, 72], XeF2 [66], DRIE [57])

6 M

TMAH 22%

a) For isotropic etchants, the etch rate is independent of the crystal orientation; for anisotropic dry etching, the etch rate given is in direction of the ion bombardment.

b) SiNxetch rate in HNA is smaller than SiO2 etch rate.

c) Selectivities between etch rates SiO2 : Si and SiN : Si are given rather than etch rate itself

bombardment, the polymer deposition on the horizontal surfaces can almost beprevented, while the sidewalls are passivated with a Teflon-like polymer In thesecond process step, SF6-based etching chemistry provides silicon etching in thenon-passivated regions, i.e the horizontal surfaces Both process steps are alter-nated, resulting in typical silicon etch rates of 1–3lm/min with an anisotropy ofthe order of 30 : 1 [60] Silicon dioxide and photoresist layers can be used as etchmasks The DRIE system achieves exceptional anisotropy, which is independent ofthe crystal orientation, but is far more expensive than e.g a simple wet-etchingsetup, and can process only one wafer at a time Commercial etchers of this typeare available from, e.g., Surface Technology Systems (STS) [69], Unaxis Semicon-ductor [70] and Alcatel [71].

The characteristics of the most common bulk silicon etchants are summarized

in Tab 1.3 In addition to the described ‘basic’ micromachining processes, a largenumber of specific silicon-based micromachining processes have been developed.The ones relevant for the fabrication of CMOS-based microsystems will be dis-cussed in Section 1.4

1.2.2

Surface Micromachining

The most commonly used surface micromachining process is sacrificial-layer ing [61] In this process, a microstructure, such as a cantilever beam or a sus-pended plate, is released by removing a sacrificial thin-film material, which waspreviously deposited underneath the microstructure The release of polysilicon mi-crostructures by removing a sacrificial silicon dioxide film is the most popular sur-face micromachining technique [61] Sacrificial aluminum etching (SALE) hasbeen developed to release dielectric microstructures with embedded metal layers[73] Metallic microstructures deposited by low-temperature PVD processes canuse polymer films as sacrificial layers, which are removed using, e.g., an oxygenplasma [74, 75]

etch-A prominent example of a device based on surface micromachined tures is the digital micromirror device (DMD) developed by Texas Instruments([74], see Section 1.4.3) The DMD consists of an array of micromirrors (seeFig 1.13 a), fabricated on top of a CMOS substrate by deposition and patterning offour metal and two polymer layers The micromirror array with a pitch of 17lm

microstruc-is released by removing the polymer sacrificial layers Fig 1.13 b shows a micromachined bolometer structure made from polycrystalline Si57Ge43 at IMEC(Leuven, Belgium) and Fig 1.13 c gives details of a 4lm thick, released polysili-con microstructure fabricated at Analog Devices (Norwood, MA, USA)

CMOS-compatible Design of MEMS and NEMS

Can I modify the CMOS process sequence to co-integrate microelectromechanicalsystems with CMOS circuitry? Can I modify the CMOS process design rules to im-plement my microstructure? Maybe the questions should be less ‘Can I?’ but rather

‘Where and how much can I?’ In the following section, we would like to give thereader an idea of possible process and design modifications First and foremost,any modification on the CMOS process sequence and the established design rulesfor a particular process must not compromise the characteristics and yield of thecircuitry components Therefore, every process modification has to be properly qua-lified Even if a process modification is not affecting the circuit characteristics, itmight be difficult to implement it in a process run done at a commercial CMOSfoundry: it can be very challenging to persuade a CMOS foundry to use pre-pro-cessed wafers as starting material or to interrupt the regular process sequenceand have additional process steps performed (probably even outside the CMOS foun-dry) before resuming the ‘standard’ process sequence We will see in Section 1.4 that

Fig 1.13 (a) Top: SEM photograph of 3 ´3

array of pixels of Digital Micromirror Device

(DMD TM ) by Texas Instruments; the mirror of

the center pixel has been removed to show the

underlying metal structures Bottom: SEM

photograph shows details of the micromirror

yoke and hinges (images from Texas

Instru-ments DLP image library:http://www.dlp.com).

(b) SEM image of surface-micromachined Si57Ge43 bolometer structures Courtesy of IMEC, Leuven, Belgium (c) Detail of surface- micromachined 4 lm thick polysilicon micro- structure Courtesy of Steve Lewis, Analog De- vices, Norwood, MA, USA

poly-‘substantial’ process modifications, as required for pre-CMOS and intra-CMOS proaches, most often require in-house CMOS capabilities In the following, we willconcentrate on ‘small’ process modifications that might be tolerated by a majority ofindependent CMOS foundries Since the author’s background is especially in thearea of post-CMOS microsystem approaches, most of the discussed process modifi-cations will enable different post-CMOS micromachining modules.

ap-1.3.1

Tolerable Process Modifications

If the microstructures are to be released by wet anisotropic silicon etching cially from the back of the wafer), the wafer starting material for the CMOS pro-cess must be considered carefully Modern CMOS processes often use epitaxialwafers with a weakly p-doped epitaxial layer on top of heavily p-doped substrate asstarting material in order to improve latch-up stability If the substrate p-type dop-ing is above 1019cm–3, the silicon etch rates in common anisotropic etchants,such as KOH and TMAH, are drastically reduced In addition, the startingmaterial has typically a rather broad specification range for the substrate doping,which, in case of highly p-doped substrates, can result in substantial etch rate var-iations from wafer to wafer To ensure compatibility with anisotropic silicon etch-ing, either epi-wafers with reduced substrate doping (£5´1018cm–3) or low p-doped non-epi wafers can be used as a starting material [18]

(espe-A second challenge for the bulk-micromachining using anisotropic wet etchants

is the relatively high interstitial oxygen concentration in the wafer startingmaterial, as required for internal gettering in the CMOS process With an intersti-tial oxygen concentration larger than its solid solubility, the oxygen precipitatesduring annealing steps in the form of oxide particles Defects caused by oxygenprecipitation are commonly used for internal gettering of transition metal impuri-ties during CMOS processing The oxygen precipitates and the associated crystaldefects in CMOS-processed wafers deteriorate the quality of etched cavities, result-ing in uneven (111) sidewalls (with crater-like depressions) and large, locally vary-ing underetching of the silicon nitride etch mask, yielding membranes with poorgeometric definition [18, 76] It should be noted that membranes with well-de-fined lateral dimensions can always be achieved by appropriate design, e.g usingeither a p++-doped ‘etch-stop’ ring surrounding the membrane [77] or an electro-plated metal ring [22, 63], defining the mechanical edge of the membrane A re-duction of the interstitial oxygen concentration in the starting material from

*8´1017to (6.0–6.9)´1017cm–3resulted in a strongly improved quality of the leased microstructures (see Fig 1.14; [18, 76]) However, the wafer material withreduced defect density also has reduced internal gettering capability and externalgettering using, e.g., hard mechanical damage on the wafer back, must be em-ployed The introduced crystal defects on the wafer back have to be removed atthe end of the CMOS process, prior to the deposition of the etch mask

re-Any additional (high-temperature) process step performed during or after theregular CMOS process sequence must be considered carefully in terms of the

overall thermal budget of the process The overall thermal budget critically ences the various doping profiles and thus the resulting device characteristics.Prolonged additional high-temperature process steps with peak temperatures

influ-³8008C are likely only possible prior to the channel and source/drain tions Medium-temperature processes, such as LPCVD deposition of polysilicon atabout 6008C, have been performed after the source/drain implantations [78], butprior to the back-end aluminum metallization High-temperature annealing stepsrequired, e.g., for stress relief in the deposited polysilicon layers have to be care-fully evaluated, as their thermal budget might influence shallow junction profiles

implanta-Of course, the initial doping profiles can be adapted so that additional thermalprocess steps are taken into account, but this generally requires substantial re-qua-lification of the CMOS process The standard aluminum metallization employed

in most CMOS processes with minimal feature sizes above 0.25lm is known towithstand maximum process temperatures of about 4508C (recent work indicatescompatibility with temperatures up to 5258C [79]), strongly limiting the range ofprocess steps that can be performed after completion of the CMOS process se-quence (see Section 1.4.3)

Deposition and patterning of the passivation layer are typically the last processsteps of the regular CMOS process sequence Hence, the passivation compositioncan often be adjusted to the customer’s needs If the passivation is part of the re-

Fig 1.14 Quality of etch cavities released by

wet anisotropic etching using a 27 wt% (6 M)

KOH solution at 908C; photographs of

(a) (111) sidewalls and (b) (100) etch fronts

are shown for test wafers with a normal

inter-stitial oxygen concentration of *8´10 17

cm–3and a low interstitial oxygen concentration of (6.0–6.9)´10 17

cm–3; prior to KOH etching, the wafers were exposed to a thermal simula- tion of a CMOS process Adapted from [18]

leased microstructure, its residual stress can be used to tune the stress of the overallmicrostructure An example is the thermal imager shown in Fig 1.7 The membranewith embedded infrared sensor array has a layered structure comprising the differ-ent dielectric layers of the CMOS process with polysilicon and metal structures sand-wiched in between them The overall stress of the layer sandwich without the CMOSpassivation is compressive in this example, which could result in membrane buck-ling To reduce the overall compressive stress in the membrane, a passivation layerwith tensile stress is deposited The stress of a PECVD silicon oxynitride passivationcould be controlled in the range from –300 to +300 MPa by choosing an appropriatelow frequency (400 kHz) to high frequency (13.56 MHz) power ratio and chamberpressure in the used PECVD system [63] It should be noted that the stress in thepassivation can influence the characteristics of the previous layers, e.g the electro-migration behavior of the underlying metal lines.

1.3.2

Design Rule Modifications

Typically, CMOS foundries provide rule-files for their CMOS processes for a ber of supported design environments in order to perform design rule checks(DRCs) and extraction of the layout for layout-versus-schematic (LVS) check Theenforced design rules ensure a high yield of the fabricated circuit componentswithin the given process specifications, but might be problematic for the MEMSpart Two examples are given in the following: in order to release microstructures,such as the thermal converters shown in Fig 1.11, from the front of the wafer,the silicon substrate must be exposed to the etchant in certain areas on the wafer.This can be achieved in a CMOS process by superimposing an active area (i.e nofield oxide), a contact (i.e no contact oxide), a via (i.e no intermetal oxide) and apad opening (i.e no passivation), thus locally removing all dielectric layers of theCMOS process and exposing the silicon substrate to the environment [80] Thestandard design rules of the used CMOS process will, e.g., not allow a via withoutmetal below and on top of it, because a via in a CMOS circuit only makes sense

num-as an interconnect between two metallization levels Thus, the automated rule checker (DRC) will give error messages In another area one might want touse a non-connected aluminum area as a mirror surface The DRC will again give

design-an error message because of a non-connected conducting area Both design ples make no sense in a circuitry environment, but are useful for the MEMS partand, very important, do not compromise the integrity of most CMOS processes(for completeness, it should be mentioned, that sub-0.5lm CMOS technologieswith plated vias might not allow a contact layer without metal overlap in ordernot to compromise via plug plating and CMP) So, how can one allow such de-sign rule violations and still use the extremely helpful DRC? The ideal case is towrite a complete set of design rules for the MEMS areas, having the circuitrychecked by the foundry-supplied ‘standard’ design rule set and the MEMS by anextended design rule set This approach might be initially more time consuming,but will, in the long run, prevent design errors in the complex MEMS designs

exam-Modern sub-lm CMOS processes use lithography based on wafer steppers, viding an array of step fields on the wafer with no mutual connection Post-CMOS micromachining based on anisotropic wet etching in combination with anelectrochemical etch-stop technique (see Section 1.4.3) requires the application ofetching potentials to (structural) n-well and substrate contacts across the wafer[17, 18] To supply these etching potentials, a contact network implemented in themetal-1 and metal-2 level of the CMOS process routes the etching potentials fromlarge contact pads to the individual etch contacts To achieve this, each metalmask step field is surrounded by a predefined frame (see Fig 1.26 b), routing oneetching potential on metal-1 level and the second etching potential on metal-2 lev-

pro-el to reduce the risk of short-cuts between the etch networks [18] The frames areconnected to each other at the corners of the step field by metal structures placed

in the scribe channel, i.e the individual metal-level step fields actually overlapduring the stepper-based lithography The construction of these metal bridgesmust not affect the regular test structures in the scribe channel Within the reti-cle, the individual etch contacts are connected to the metal frame In order tohave large contact pads for applying the etch potentials with spring-loaded con-tacts, a dedicated ‘contact’ step field (see Fig 1.26 a, top of the wafer) is printedwhich has the same size as the other step fields This is done on the second me-tal mask level using a special ‘contact’ reticle In addition, a ‘blank’ reticle is used

to remove the metal around the edges of the wafer in order to avoid short circuits

in the etch network at the wafer edge The described method requires three tional masks (‘blank’ reticle, ‘contact’ reticle and ‘contact opening’ reticle), whichcan, however, be reused if the reticle size from design to design is not changing.Besides exposing the wafer on the metal mask level with different reticles, nomodification in the process flow is required

addi-1.3.3

Simulation of Circuitry and MEMS

Traditionally, MEMS and IC designers have used very different design tools.While IC designers rely on schematic-driven circuit simulators offered by the ma-jor electronic design automation (EDA) companies, such as Cadence [81], MentorGraphics [82] and Synopsys [83], the MEMS designer typically relies on finite-ele-ment modeling (FEM) software, such as ANSYS [84], FEMLAB [85], Coventor-Ware [86], or IntelliSuite [87], for multi-domain analysis of their microstructures

In order to simulate and design integrated circuits based on a particular CMOSprocess, the CMOS foundries supply process-specific design kits, including designrules, process specifications, transistor-level models and analog and digital cell li-braries, to support the major EDA tools In order to simulate CMOS-based micro-systems including micromechanical transducers and analog and digital circuitry,behavioral models for the transducer elements are required To be compatiblewith the standard mixed-signal simulators delivered with common EDA packages(e.g SPECTRE [81], ADVance MS [82], SABER [83]), these behavioral modelsmust be expressed in an analog hardware description language (HDL), such as

Verilog-A or VHDL-A The generation of such models for the transducers ing multiple signal domains from either the layout or the results of the FEM sim-ulation is not straightforward Simple lumped-element circuit models of the trans-ducers might be developed manually on a case-by-case basis For certain catego-ries of microstructures (e.g comb-drive resonators), the generation of macro-models is supported by academic [88, 89] and commercial tools [86, 90] INTE-GRATOR, developed by Coventor [86], is able to generate reduced-order macromo-dels of dynamic mechanical systems, consisting of spring, mass and damping ele-ments, from detailed 3-D finite element (FEM) or boundary element (BEM) simu-lations for export in standard circuit simulators NODAS, developed at CarnegieMellon [88, 91, 92] is a library of parameterized components, including beams,plate masses, anchors, electrostatic comb drives and gaps, to simulate surface-mi-cromachined MEMS structures using the SABER and SPECTRE simulators Com-plex microstructures are build by interconnecting individual library elements NO-DAS also has the ability to generate automatically the layout from the developedschematic.

involv-Once the top-level layout of the integrated microsystem is completed, a designrule check (DRC) and a layout-versus-schematic (LVS) check are performed In or-der to account for different design rules in the circuitry and the MEMS part, thestandard design rule files supplied by the CMOS foundry might need to be ex-tended (see Section 1.3.2) In addition, the standard extraction rules can beadapted in order to recognize and extract at least the electrical features of thetransducer elements [93] This allows the verification of the top-level design bycomparison with the simulated top-level schematic and avoids, e.g., wiring errors.Some of the available tools also permit extraction of non-electric features [94].More details on MEMS modeling in general and the extension of circuit simula-tion to include micromachined devices can be found in several books and over-view articles [94–98]

1.4

CMOS and Micromachining

The integration of micromachining processes with CMOS technology can be complished in different ways The additional process steps (or process modules)can either precede the standard CMOS process sequence (pre-CMOS) or they can

ac-be performed in ac-between the regular CMOS steps (intra-CMOS) or after the pletion of the CMOS process (post-CMOS) [99, 100] In the case of post-CMOSmicromachining, the microstructures are built from either the CMOS layersthemselves or from additional layers deposited on top of the CMOS wafer.Tab 1.4 summarizes various CMOS-based microsystem approaches found in theliterature Some of these approaches require several additional process modules,e.g a pre-CMOS and a post-CMOS module; in these cases, we have categorizedthem by their first non-standard process sequence The cited publications are ex-emplaric and the list provided is by no means considered to be all-inclusive

com-Tab 1.4 CMOS-based microsystems using pre-, intra- or post-CMOS process modules to ment the microstructures

imple-Surface micromachining

Bulk micromachining

– Accelerometer [141]

Tab 1.4 (cont.)

Surface micromachining

Bulk micromachining

Tab 1.4 (cont.)

Surface micromachining

Bulk micromachining

ETH Zurich [17, 80]

– Chemical sensors [19, 169, 170] – Thermal imager [22, 23, 171] – Tactile sensor [172]

NIST and George Washington Univ [188]

– Chemical sensor [203]

MEMSIC [204]

– Accelerometer [205]

Depending on the chosen integration path, a number of fabrication constraintsare imposed on the micromachining steps in order not to deteriorate the perfor-mance of the CMOS electronics An important example is the thermal budget al-lowed for the micromachining process steps Polysilicon microstructures are de-posited at temperatures between 575 and 6258C in an LPCVD furnace and typical-

ly require thermal annealing at temperatures³9008C to reduce residual stresses[215, 216] However, after deposition of the aluminum metallization of a CMOSprocess, the maximum process temperature is limited to£4508C in order not todegrade the aluminum-silicon contacts Therefore, polysilicon cannot be depositedafter the completion of a CMOS process with standard aluminum metallization

In order to enable the deposition of polysilicon microstructures after the

comple-tion of the CMOS process sequence, an alternative high-temperature stable lization, such as tungsten, must be used for the CMOS process [61, 142] Consid-ering that IC manufacturers have invested enormous resources into the develop-ment of reliable, multi-level aluminum interconnect technologies, and furtherconsidering the inferior resistivity of tungsten versus aluminum, it seems unlikelythat such a process would be adopted in industry Alternatively, the standard poly-silicon gate material of the CMOS process is used as well for the microstructures

metal-or an additional structural polysilicon layer is deposited and structured befmetal-ore the

standard CMOS metallization is applied In this approach, the regular CMOS cess sequence is interrupted before the metal deposition, a dedicated microma-chining module is inserted and then the CMOS process sequence resumes withthe back-end aluminum interconnect technology This intra-CMOS approach mini-

pro-Tab 1.4 (cont.)

Surface micromachining

Bulk micromachining

– Accelerometer [214]

mizes performance degradations for both electronic and mechanical components,but requires interruption of the CMOS process sequence and, more critical, theneed to return CMOS wafers into a CMOS line after performing non-standardprocess steps As a result, this fabrication approach for CMOS-integrated polysili-con microstructures has been commercialized by companies with in-house CMOS

or BiCMOS fabrication facilities (e.g Analog Devices [78, 107, 118] and Infineon[5, 120])

1.4.1

Pre-CMOS Micromachining

Pre-CMOS micromachining or ‘MEMS-first’ fabrication approaches avoid thermalbudget constraints during the MEMS fabrication In this way, e.g thick polysili-con microstructures requiring stress relief anneals at temperatures up to 11008Ccan be co-integrated with CMOS circuitry Typically, the MEMS structures are bur-ied and sealed during the initial process module After the wafer surface is planar-ized, the pre-processed wafers with embedded MEMS structures are used as start-ing material for the subsequent CMOS process Challenges include the surfaceplanarization required for the subsequent CMOS process and the interconnec-tions between MEMS and circuitry areas

The M3EMS (Modular, Monolithic MicroElectroMechanical Systems) technologydeveloped at Sandia National Laboratories was one of the first demonstrations ofthe MEMS-first integration concept [61, 101] In this approach, the multi-layerpolysilicon microstructure is built in a trench, which has been etched into thebulk silicon using an anisotropic wet silicon etchant After formation of the polysi-licon microstructures, the trench is refilled with LPCVD oxide and planarizedwith a CMP (chemical mechanical polishing) step Subsequently, the wafers withembedded microstructures are used as starting material in an unmodified CMOSprocess, fabricating CMOS circuitry in areas adjacent to the MEMS areas TheCMOS metallization is used to interconnect circuitry and MEMS areas The back-end of the process requires additional masks to open the protective silicon nitridecap over the MEMS areas prior to the release of the polysilicon structures by sili-con oxide sacrificial layer etching A cross-section of the M3EMS technology usedfor the fabrication of inertial sensors [102] is shown in Fig 1.15 a Theoretically,the planarized wafer with embedded MEMS structures can serve as startingmaterial for any microelectronics foundry service, since the technology does notrequire significant modifications of the CMOS process sequence [102] Of course,the pre-processed starting material requires stringent qualification by the CMOSfoundry in order not to compromise their process yield A resonant accelerometerfabricated with Sandia’s M3EMS technology has been reported in [103] Research-ers at the University of Michigan have developed a similar trench-based MEMS-first technology to co-integrate polysilicon microstructures with a 3lm CMOStechnology [104]

Recently, an alternative pre-CMOS MEMS process called Mod MEMS has been

demonstrated by Analog Devices, Palo Alto Research Center and UC Berkeley

[105] Mod MEMS enables the integration of 5–10lm thick polysilicon MEMS vices with sub-lm CMOS circuitry In contrast to the Sandia approach, the thickpolysilicon structures are build on top of the silicon substrate and not in anetched trench (see Fig 1.15 b) An 11008C anneal ensures nearly stress-free polysi-licon layers with very small stress gradients [105], which is especially importantfor thick polysilicon microstructures The intra-CMOS approach used by AnalogDevices for the fabrication of their ADXL and ADXRS series inertial sensors (seeSection 1.4.2) does not allow such high annealing temperatures and thus limitsthe thickness of the structural polysilicon layer After forming isolation trenches

de-to provide electrical isolation between MEMS regions at different potential, a

2lm capping oxide/nitride sandwich is deposited on the polysilicon, the MEMSstructural regions are defined by a polysilicon etch step and the sidewalls of theMEMS regions are passivated by a thermal oxidation Next, a selective epitaxial sil-icon growth process is used to provide planarization around the thick MEMS

Fig 1.15 Schematic cross-section of two

pre-CMOS MEMS processes for fabrication of

monolithically integrated polysilicon

micro-structures: (a) M 3 EMS technology by Sandia

National Laboratories Adapted from [101] (b) Mod MEMS technology by Analog De- vices, Palo Alto Research Center and UC Ber- keley Adapted from [105]