Iec 63003 2015

info@ie .c w w.e .c About t he IEC Th Inter natio al Ele trote h ic l Com is io IEC is th le din glo al or ga izatio th t pr ep res a d publsh s Internatio al Sta dard for al ele tri al

IEC 63003

Edit ion 1.0 2 15-12

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INTER NA TIONA L

STA NDA R D

Standard for t he common test int erfac e pin map configura on for high- de sity,

single- t ier electronic te t re uireme ts ut ilzing IEEE Std 15 5™

Cont ent s

1 Ov erv iew 1

1.1 Sco e 1

1.2 Purpose 2

1.3 Sta t ement o the pro lem 2

2 Norma tiv e references 3

3 Definitons, a cron y ms, a nd a bbrev ia tions 4

3.1 Definit io s 4

3.2 S e ifica tio ter ms 4

3.3 Acron yms and a bbrev ia t ions 4

4 Common test nterfa ce requ iremen ts 8

4.1 Introduct io 8

4.2 CTI o en system req uirements 8

4.3 CTI cost req uirement s 9

4.4 V ertica l integ ra tio test su pp rt req uirement s 9

4.5 CTI configura tio /int eropera bi t y requirement s 10 4.6 Ma inta ina bi t y/end-user supp rt requirements 10 4.7 Sca lea ble a rchit ecture requirement s 10 4.8 Ph ysica l framewor k requir emen ts 12 4.9 Rela bi t y req uirement s .17 4.10 CTI connector fotprint/ pa ra met ric requirement s 18 4.1 CTI pin ma p requirement s 2

4.12 CTI pin ma p input / output config ura t io 3

A n nex A (nor ma tiv e) Common t est nt er fa ce sig na l defin it ions fr pin ma p 34 A.1 Analo instr u ment s (AI) .34 A.2 Bus 36 A.3 Dig ita l 37 A.4 Instrumen t control 37 A.5 Power loa ds 37 A.6 Power upples 38 A.7 Sense a nd control, DCPS, a nd loa d s 38 A.8 Swit ch 39 A.9 System 4

A n nex B(in for ma t iv e) Biblog ra ph y 1 9

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STANDARD FOR THE COMMON TEST INTERFACE PIN MAP

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rig ts,a dth risk of infin eme t of s c rig ts,ise tirely th ir own resp nsibi ty

Intern tio al Sta d rd IEC 6 0 3/IEEE Std 15 5.1-2 0 h s b e pro es e thro g IEC

te h ic l c mmite 91: Electronic as embly tec nolog , u d r th IEC/IEEE Du l L g

IEEE St an ard Co rdin t i g Commit t ee 2 on

Te t a d Dia nosis for Ele t ronic Syst ems

Approv ed 2 Se t emb r 2 0

IEEE- SA St and rd Board

Approv ed as a Ful-Use St an ard on 14 Ju e 2 13

IEEE- SA St and rd Board

Abst ra t : This st an ard re resents an ex t en ion t o t he IEEE 15 5 rec eiv er fix t ure int erac e (R FI)

st an ard sp c ific at ion Part ic ular emphasis is plac ed on definin w it hin t he IEEE 15 5 R FI

st an ard a more sp cific set of p rormanc e req irement s t hat employ a c ommon sc ala le: (a)

pin ma c onfig rat ion; (b) sp cific c on ec t or mod les; (c ) resp ct iv e c ont ac t s; (d) rec ommen ed

sw itc hin implement at ion; an (e) legac y aut omat i t est eq ipment (ATE) t ran it ional dev ices

This is int ent ionaly done t o st an ardize t he fo t print an as ure mec hanic al an elec tric al

int ero era i t y b t w een p st an fut ure aut omat ic t est sy st ems (ATS)

Keyword : ATE, ATS, fix t ure, ICD, IEEE 15 5.1

M

, int erac e, ITA, mas t erminat ion, rec eiv er,

sc ala le, T S, UUT

•

I(((,nt roduct ion

Th is in t rod uct i on is n ot part o IE E Std 15 5.1-2 0 , IE EE St an d ard fr t h e Common Test Interface Pin Ma p

Con fig uration fr Hig h -Den sit y, Sin g le-Tier Ele tron ics Test Requ iremen ts U t ilz in g IE E Std 15 5

™

This sta nd a rd stems from t he histor y o ATE implementa t ions h av ing un iq ue input/out put (/O) pin out

d efinit ions This u niq uenes h a s prev ented t he intero era bi t y o test prog ram set s (TPSs) amon g d iferen t

ATEs wit hin the same org a n iza tions Ev en ift he same RFI wa s used b t he t a rg et ATE, the signa ls I/O

could not be gua ra nteed to be a t the same pin loca tion This is due to t here bein g n suit a ble sta nd a rd pin

out d efinitio fr g enera l purpose ele tronic testin g a pplca tions

IE E Std 1 05-2 0

a

ha s ad d res ed pa rt o the intero era bi t y problem b d efinin g the common

mechanica l in terfa ce fr the ATE This proje t t a kes the TPS int ero era bi t y problem one st ep further

t owa rd completion b sta nd a r d izin the ele trica l signa l I/ O pin ma p fr g en era l purp se ele t ronic test in g

a pplca tions

Pa rt icula r emphasis is pla ced o defining wit hin the IEE 1 05 RFI sta nd a rd a more spe ific set o

perf rmance requirements t hat emplo a com mo sca la ble: (a ) framewor k; (b) pin ma p configura tion; (c)

spe ific con nector modules; (d ) respe t iv e conta ct s; (e) recommend ed swit chin g implement a tion ; a nd (f)

leg a cy ATE tra nsit io a l d evic s This is in tent iona lly d one to sta nda rdiz the f otprint a nd a ssure

mechanica l a d ele trica l in t ero erabi t y bet ween p st an d future ATS The sugg ested me hanica l and

ele trica l requirement s nec s a ry to implemen t a spe ific IE E 1 05 RFI prod uct n supp rt o a common

t est in t erfa ce (CTI) a cros a ll U S Depa rt men t o Defen se (DoD) defense a g encies, rela t ed a erospa ce

ind u str y, a nd a v a riet y o non -U S g ov ern ment a g encies su ch a s the U K Ministr y o Defen se (MoD) is

prov id ed

The DoD is a ma jor bu yer and u ser o ATE; however, ex ist in g a cquisit io guid a nce desires t he use o

commercia l stand a rd s a nd/or best pra ctc s fr these systems Suita ble standa rd s curren tly d o not exist n

the commercia l ma rketpla ce; t heref re, t his st and a rd wi pr ov id e such spe ifica tion

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htp:/ tan ard ie ee org/IP /disc laime rs tml

in terface (RFI) Th e pin ma p defin ed w ith in this stan dard sh a ll a pply to m iltary an d aerospa ce autom a tic

test equipmen t (A TE) testin g applca tion s

1.2 Purpose

Sta nda rdiza tio o a commo input /output (/O) wil ena ble the int ero era bi t y o IE E 1 05 compla nt

int erfa ce fix t ures [a lso known a s i nte fa ce test a da pte s (TA), i nte fa ce dev i ces (Ds), or i nte co ne ti ng

dev i ces (CDs) o multiple A TE systems utilzing t he IE E 1 05 RFI

1.3 Stateme t of the problem

1.3.1 U.S Gov rnme t g id n e

From 19 0 to 19 2, the U S Depa rt men t o Defense (DoD) inv estmen t in field , d ep t, a nd fa ctor y

a utoma t ic test systems (ATS) ex ce d ed $3 bi io wit h a n a dd itiona l $1 bi io fr as ocia ted su p rt

Most o t his test ca pa bi t y w a s a cq uired a s pa rt o ind iv idua l wea po system procurements This led to a

prolfera tio o d iferent cust om eq uipment t ypes with un iq ue inter fa ces Re en t p lcy d ecision s ha v e

cha n g ed t he d irectio o t he purcha se o t est equipment t owa rds a sta nda rd s ba sed a pproa ch wit h b t h

ha rdwa re a nd so t wa re critica l interfa ce requirement s

The U S DoD Instructio 50 0.2-R1 ATS Polcy sta tes: “A TS ca a bi ties sha ll be d efined th rough cri cal

ha rdwa re and sotwa re element s” ( e [B2] ) This p lcy h owev er, d id n t d efine t hese critica l element s

The Critica l Interfa ces Proje t wa s crea ted to define critica l ATSelement s

1.3.2 Critic l Interfa e Proje t

The Fa ct ory -t o-Field Integ ra tio o Defen se Test Systems Proje t (common ly referred to a s the Cri ti ca l

Inte fa ces Proj ect wa s sta rt ed in t he la tt er pa rt o 19 5 The Crit ica l In terfa ces W orkin g Group (CIW G)

wit hin t he J oin t -Serv ic ATS Resea rch a nd Dev elo ment Int eg ra t ed Product Team (A RI) was est a blshed

to perform the proje t The ATS Ex ecutiv e Ag ent Ofic (EAO) ha s prov id ed proje t mana g ement and

co rdina tio amon g t he Air Forc , Ar my, Ma rine Corps, a n d Na vy pa rticipa nt s In a d d ition, man y ind u str y

representa t iv es ha v e pa rticipa ted The CIW G publshed their find in g s in t he A utoma tic Test System

Critica l Inter fa ces Rep rt [B1] a nd t his rep rt serv ed a s the ba sis f r the dev elo ment o t he RFI

a rchitect ure a nd subsequen t spe ifica t ion

The o je tive o the Critical Interfa ces Proje t wa s to d emonstra te t he feasibi t y o red ucing t he cost to

re-host test prog ram sets (TPSs) a nd increa se t he intero era bi t y o TPS sot wa re among t he mi ta r y ser v ic s

b usin g standa rd iz d interfa ces

Interfa ces tha t ofer t he p tentia l t o a ch iev e t his o je tiv e a re d eemed critica l Potent ial sa v in g s wil be

qua nt ified t hrough demonst ra t io The A ut oma t ic Test S stem Crit ica l Int er fa ces Rep rt [B1] is ma inta ined

b the ATS EA O a nd prov id es guid a nce to DoD ATE a cq uisitio prog rams This d ocu ment a lso a d d res ed

the req uirement s o DoD Regula tio 50 0.2-R1 [B2] a nd as isted in mig ra tin t he DoD d esigna ted tester

fmiles t owa rd s a common solution The Ha rdwa re Int er fac s (HI) Subcommit tee o t he IE E Sta nd a rds

Co rd ina t in g Com mitt ee o Test a nd Diag nosis fr Ele tronic Systems (SCC2 ) a ppled the

re ommend a tions o the rep rt a s i rela t ed to t he RFI, to th e ex tent t ha t the current R FI sta nd a rd is in full

complance wit h t he rep rt

Durin g t he Common Test Int erfa ce W orkin g Group (CTIW G) October 2 03 me t ing , the DoD prov id ed

the flowin g recommend a t ions a s guid a nce fr the Workin g Gro p’s succ s :

2

a ) Id ent if a mod ula r/ sca lea ble interfa ce

b) Allow use o d iferent siz ID/ fix ture o the same g enera l purpose int erfa ce (GPI)

c) Ensure TPS ha rd wa re compa tibi t y a s int er fa ce grows

d ) Prov id e leg a cy system supp rt

e) Prov id e a t ra nsit io pa th to supp rt eg a cy TPS ha rdwa re

f) Adhere to a n o en a rchitect ure system

g ) Buil to one spe ifica tion

h) Multiple sources

i Non-proprieta r y d esig a nd comp nen ts

j) Ensure ca pa bi ties t hat prov isio f r g rowth and spe ia l req uirement s

k) Prov id e room fr fut ure ex pan sio a nd TPSrequirements

l Supp rt a nd Promote the use o commercia l-o f-t he-shelf(COTS) interconnect comp nents

m) U se industr y stand a rd connect or technolo y

1.3.4 CTIWG le a y te t program s t s pp rt

In supp rt o these re ommen d a tions, the CTI a rchitect ure sha ll a ssure pa st eg a cy and fut ure TPS plu g a nd

pla y compa t ibi t y bet ween defen se a g encies and d efense-a erospa ce suppler Area s a d dres ed b t he

The flowin g referenc d docu ment s a re ind ispensa ble fr the a pplca tio o t his d ocu ment (i.e they mu st

be und erstood a nd used, so each referenced d ocu ment is cited in tex t and its rela t ionship to this d ocu ment is

ex pla ined) For d a ted references, only the ed itio cited a pples For und a ted referenced , t h e la test ed ition o

the referenced d ocu ment (includ in g a n y amendmen ts or corrig enda ) a pples

IE E St d 1 05-2 0 , IEE Sta nda rd fr Re eiv er Fix t ure In t erfa ce

3,4

3

IE E pu bl icti n s a re a va il abl e from the In stitute of El ectrica l a nd El ectron ics E n g in eer, 4 5 H oes La n e, Pisca ta wa y, N J 08 54,

USA (h t tp://st and a rd s.ie e.org / )

4

T h e IE E sta nd a rd s or pro ucts re r red to in Cl au se 2 a re trad em a rks own ed y th e In stitute of El ectrica l an d Ele tron ics En gin eer,

3 Definit ions, acronyms, and abbreviat ions

3.1 Definitions

For the purp ses o t his d ocu men t, t he f lowin g ter ms and d efinition s a pply The Auth ri ta tiv e Di cti ona ry

o IE E Sta nda rds Te ms [B5] should be referenced fr t erms not defined in t his clause

3.1.1 pi n m ap: The d a ta ta ble a nd ex pla na tor y tex t t ha t prov id es the a ssig n ment o ele t rica l cha ra cterist ics

or instrument I/ O t o spe ific pins

3.2 Spe ific tion terms

The spe ifica t io t er ms used t hroughou t t his standa rd a re d escribed a s flows

Rul e: Ru les sh l be flowed t o ensure compa tibi t y to the st a nd a rd A rule is cha ra cteriz d b the use o

the word s sha ll a nd sha ll n t These word s a re not used fr a n y ot her purpose ot her tha n st a t in g rules

Re omm en at ion: Re om mend a tions co sist o a d vic to a pplca nts t hat wil afe t t he usa bi t y o t he

fina l d ev ic Discus ion s o pa rticula r ha rdwa re to enha nce throu g hput would fa ll u nd er a recommend a tion

These should be f lowed to a v oid problems and to o ta in o timum perfor ma nce

S g es i on: A sugg est io con t a ins a dvic t ha t is helpul but not v ita l The rea d er is encou ra g ed to consider

the a dv ic befre disca rding it Sug g estion s a re includ ed to help the novic d esigner with problema tic a rea s

o the d esig n

Pe m is i on: Permis ions a re includ ed t o cla rif t he a reas o the spe ifica tio tha t a r e not spe ifica lly

prohibited Permis ions reas ure the rea d er t ha t a c rta in a pproa ch is a cc pt a ble a n d wi ca u se no

pro lems The word ma y is reserv ed fr indica tin g per mis ions

Obse v ti on: Observ a tions spel out implca tion s o ru les a nd brin g a tten tio to t hin gs tha t might

other wise be ov erlo ked They also g ive t he ra t iona le behind c rta in rules, so tha t the r ea d er und er ta nd s

wh the ru le must be flowed

A CPS a lt erna t ing current p wer u ply

ADC a na lo -t o-d ig it a l conv ert er

AW G a rbitra ry wav efr m g enera tor, A merica wire g aug e

CA L ca libra t io

CASS Consold a ted Automa ted Supp rt System

DA C d ig ita l-to-ana lo co v erter

FTIC freq uency time interv a l counter

IAIS improv ed a vion ics inter med iat e shop

5

U S N a v y Tester, AN /U SM-636 (V )

6

ITA interfa ce test a da pter

L X I LAN ex tensions fr instr u men ta tion

MTBF mea n t ime bet ween fa ilures

7

U S Army T est er, AN /U SM-632 (V )3

8

LM-STAR is a reg istered t ra d em a rk f L ockh eed Ma rtn Corp ra tion Th is in form at io is g iven for th e con v en ien ce of u ser of t h is

stan da rd a nd d oes n ot con stitut e a n end orem en t b th e IE E of t h ese prod ucts Equ iv a l en t pro u cts m a y be u sed if th ey ca n be sh own

PECL p sit iv e emmitt er-coupled log ic

PM pulse (or pha se) mod ula tion,p wer meter

PX I PCI Ex tensions fr Instr u ment a tio (compa ct PCI f r ma t)

ResL oa d resistve loa d

RFI re eiv er fix t ure inter fa ce

RSIA ra ster troke imag e a cq uisition

SAMe sistema a u toma tico d e manten imiento est and a r

T L tra nsistor-tra n sistor log ic

U BIC univ ersa l bus interfa ce co troler

U SB U niv era l Seria l Bu s

U U T unit u nd er test

V GA Vera tile Gra phics Ad a pter

9

V ME v ersa-mod u le ex tend ed

V X I V ME ex t end ed fr instr u ment a tion

4.1 Introduc tion

The flowin g subclauses a nd i ustra t ion s describe t he requirement s fr t his standa rd , IE E St d 1

05.1-2 0 , t o supp rt mi ta r y/ a erospa ce t est requirements This infor ma t io is supplement a l a n d not sta nd-a lon e

a nd sha ll coex ist with t ha t presented in the IE E Std 1 05 RFI spe ifica tions, Cla u se 1 thr ough Clause 6

The IE E 1 05.1 sta nd a rd fr the u se o IEE 1 05 RFI t o supp rt milt a r y/ a erospa ce t est requiremen t s

represent s a higher ord er subset o cost/ ph ysica l/ signa l perfrmance requirement s t o me t spe ific industr y

and d efen se a g ency g oa ls o a common t est nt erfa ce (CTI) These hig order requiremen t s ex pa nd o t he

prev iously defined R FI: (a ) framework; (b) conne t or modules and respe tiv e conta cts; t o me t o je tiv es

fr: (c) a common sca la ble pin ma p con figura tion ; (d ) switchin g ;and (e) leg a cy ATS tra n sitiona l d evic fr

Third Echelo Test System (TE TS), Consold a ted A utomated Supp rt System (CA SS), Integ ra ted Family

o Test Eq uipment (FT ), a nd ot her as deemed nec s a r y b the co nizant ag encies Th is is int ent iona lly

done to stand a rd iz the fotprint and a ssure mechanica l and ele t rica l intero era bi t y bet we n pa st a nd

fu ture ATS

On 2 Nov ember 19 4, t he Honora ble Pa ul G Kaminski, U nd er Se ret a r y o Defen se fr Acquisit io a nd

Te hnolo y, dire ted a cquisit io ex ecutiv es in t he DoD to u se “o en systems” spe ifica tions and sta nda rd s

(ele trica l, me hanica l, t her ma l, etc.), fr a cq uisitio o al wea po syst ems ele tronics to the g reat est

ex ten t pra ctica l The Open S stems J oint Ta sk Forc (OS-J TF) was f r med in September 19 4 to:

“ Sp n sor a nd a cc lera t e t he a doptio o o en systems in wea pons systems a nd subsyst ems ele t ronics t o

red uce lfe-cycle costs (L CC) a nd fa ci ta te efe tiv e wea po syst em intra - and interopera bi t y.”

4.2.2 CTI “o e ” arc ite ture

Rul e 4.2.2: An o en stand a rd CTI a rchi te ture sha ll identif comp nen ts, t he rela tionship bet we n

comp nent s, a nd the r ules f r the a rchitect ure’s comp sit ion

Re ommen ati on 4.2.2: Ty ica l g uid elnes fr a d dres in g t he CTI a rchit ecture should includ e:

a ) Define a nd describe a system a rchitecture t ha t is t ra cea ble to the Opera tio a l Requir emen ts

Document (ORD)

b) A preferred a rchit ecture is modula r, hiera rchica l a nd la ered, a nd is ba sed o o en sta nda rd s a t

it s in t erfa ces

c) Sele t io o a a rchit ecture sh a ll be a co pera t iv e proc s bet we n g overn ment a nd industry

d ) S e if key perfor mance a tt ributes o system build ing blocks includ ing inter na l in t erfa ce

sta nd a rd s

e) W here a new system is co templa ted, consensu s amon g p tent ia l contra ct ors and t heir key

suppler o a pplca tio o wid ely a cc pted standa rds is d esira ble

f) Id entif a spe ts o the prog ram that might lmi t he u se o a o en systems a pproa ch

g ) Det er mine the lev el a t wh ich t he a rchitect ure wil be d efined fr the system

h) Architect ure a pproa ch resultin g from a system en g ineerin g proc s sha ll be lnked to a busines

ca se a na lysis

i De ision s a bout a rchitect ure sha ll be ln ked to perfor ma nce, L CC, sched ule, and risk

j) Ident if o p rt unit ies fr reuse o ha rdwa re a nd sot wa re con figura t io it ems a d depend ence

upo inter fa ces

4.3 CT I cost re uireme ts

Re omm en ati on 4.3 : Fun d a menta l to t he implementa tio o the CTI recommend ed pra ctic should be

the pa ramount need to a dd res d esign-to-cost s (DTC) a nd L C a t tribut ed t o test int erfa ce a nd TPS

req uiremen ts

Re ommen at i on 4.3b: CTI shou ld improv e t he test a cquisition proc s b crea ting a competi v e mu

lti-vend or env iron ment t ha t prov isions commo mod ule comp nent s tha t ca be procured a s COTS, a t pricing

tha t benefit s from industr y e o omics-o-sca le prod uction/ qua lit y proc s es, a nd improv ed time-to-ma rket

av a ila bi t y

Re omm en ati on 4.3c: CTI should meet a dv a nced funct iona l and t ech nolog ical needs t hrough sha red

ind u str y R&D, multi-fu nctiona l/ v irtual mod ules tha t ca be replca ted , d istributed , a nd re onfigured to

me t a broa d set o a pplca tions wit hout customiz a t ion Ex tend leg a cy system lfe thr ough tech nolo y

insertio o plu g a nd pla en h a ncement s ba sed upo standa rd iz d infra str ucture, a nd rela ted cost-a v oid a nce

o ATS o solesc nce

Re omm en ati on 4.3d: CTI shou ld minimiz configura tio v a ria tions a nd rela t ed sot w a re cust omiza t ion

and a d just ments betwe n u nique test a ssets, integ ra tio met h od s, a nd signa l routing schem es

Re omm en at i on 4.3e: CTI shou ld promote co pera tiv e design, d esig reuse, sha red desig d a ta mod els,

automa t io in so t wa re d ev elo men rehosta bi t y and p rta bi t y o TPSs, implement a tio o les ons

lea rned , a nd enha nce lon g-ter m supp rt bet we n v end or , integ ra tor a nd users Stand a rd s a lso promote

common fa brica tio proc s es, sig na l routin g schemes, ca nn ed solutions t ha t could red uce TPS eng ineerin g

integ rat io time a nd cost

4.4 Vertical inte ra on test support re uireme ts

Re omm en at ion 4.4: The implementa t io o the CTI/RFI stand a rd a s common v ertica l i ntegra ted test

su p rt t hro g the product cycle a nd v a rious ma in t enance lev els a ssures the g rea test benefit s o common

system implement a t io and cost sa v in g s S e ific benefit s includ e the sha red d ev elo ment/ ma n ufa ct urin g

o ATS a nd TPS a ssets, enh a nced TPS verifica tio and refinements, a nd tra n sit iona l improv ement s in

les on s lea rned , hand s-o tra inin g and a sset ma nag ement

4.5 CT I configuration/ interopera i ity re uireme t s

Rul e 4.5: CTI pi n map r q i rements, a s d efined b gene a l pi n ma p r q irements in A nnex A, a nd

subsequent d eta iled CTI pi n ma p i np t/o tp t (IO ) co figura ti on, sha ll be implement ed to a ssure test

int erfa ce int ero era bi t y bet w een a g encies and ATS co fig u ra tions

Re omm en ati on 4.5: A com mo CTI pin ma p con figura tio has be n recommend ed a cros g ov er n ment

mu lti-a g encies, to stimu la te g rea ter use o com mo as ets, wh ich red uces prolfera t io a nd supp rt

duplca tion By sa tisfyin int ero era i t y req uirement s bet we n g ov ern ment a g encies TPS d ev elo ment,

deployment and a sset duplca t io ca n be elmina ted and rela ted wea po system supp rt en ha nced

4.6 Maintaina i ty/ end- user support re uireme ts

Rul e 4.6: The g enera l pin ma p req uirement s in A n nex A, and subseq uent d eta iled CTI pin ma p I/O

configura t ion, a s pa rt o this IE E 1 05.1 CTI document , sha ll be ma int a ined /upg ra d ed through IEE

sta nd a rd s rev isio proc s es

Re omm en ati on 4.6: The CTI implementa t io wit hin ind ustr y a nd the g ov ern ment, utilzing stand a rd

prod uct configura tio s, mult i-v end or interchan g ea ble pa rts, ca libra t ion, a nd ma in ten a nce supp rt is

re ommend ed

Obse v ati on 4.6: Applying common C I prod ucts to ATS a nd CTI fix t ure d eploymen t w ould d ra ma t ica lly

red uce d uplca tiv e req uirements fr unique system d evelo ment, v a lid a tio , prod ucton, d eployment,

co figura tio prod uct managemen t, a nd lon g-ter m supp rt This a pproa ch would furt h er enhance a sset

av a ila bi t y/ uptime mea time bet we n fa ilures (MT F), calbra tion/spa res consold a tion, a nd mea

n-time-to-repa ir (MT R) results User could a lso benefi from common ma intena nce pra ctic s, toolng , and

tra ining costs CTI implement a tio would a lso f cus product manag ement /fe dba ck on a sma ller n u mber o

unique insta lled systems, t heir rela ted fa ilures/les ons learned , a nd itera tiv e improv em ents, resultin g in

improv ed rela bi t y, les o solesc nce, and long er lfe cycles

4.7 Sc le ble arc itecture re uireme ts

4.7.1 Ov rview

Rul e 4.7.1: CTI sha ll supp rt modula r and sca lea ble concepts a s i u stra ted in Fig ure 1 Ba sed upo t he

IE E 1 05 RFI stand a rd, CTI sha ll supp rt upwa rd scala ble compa tibi t y without mod ifica t io or a d ded

ex ten sion s o a low-end (4-slot CTI configura tion), and a mid -siz d (2 -slot CTI configura tion), to a high

-end (2 -slot CTI config ra tion) test system ca pa bi t y

Obse v ti on 4.7.1: Sca la bi t yʊ“Ser v es to minimiz or elmina t e t he cost s o fix t urin g b sca ling t he

req uiremen ts to minimum framework and rela ted pin ma p configura tion This minimiz s t he siz , stora g e

requiremen t s, a nd complexit y o fix t uring , a s wel a s rela ted re eiv er a nd fix ture() cost s, t o only what is

ne es a r y to interfa ce t he unit under test (U U T) t o the ATS (e.g , a ca ble as embly ca n be plug g ed int o the

re eiv er wit hout a fix t ure b x being a ppled) This a lso permit s a n a v ionics b a rd man ufa cturer to d ev elo

a compa tible TPS f r fa ctory test a nd a llow t he Gov ern ment to utilz t ha t same fix t ure o the hig h-end

dep t tester wit hout mod ifica tions/a da pt er S ch ca pa i ties dema nd t ha t t he m echa nism supp rt

eng ag emen t a ct ua t or a t incremen ta l p ints to pull sma ller fix t ures in to t he re eiv er.”

4.7.2 Ge eral buidin bloc archite ture

Rul e 4.7.2: CTI sha ll supp rt a sca la ble build ing block a rchitecture wit h commo I/O pin ma p tha t rema in s

u wa rd ly comp t ible wit h ma tched con nector/co ta ct configura tio and sca la ble a plca tio lev els

4.8 Physical framework re uireme ts

4.8.1 IEEE 15 5 R FI sta dard compla c

Rul e 4.8.1: The CTI sha ll be fu lly compla nt with IEE St d 1 05 RFI sta nda rd fra mework spe ifica t ions,

Cla u se 5, ex pa nd a ble to two tiers, to a max imu m o 2 slots per tier (2 slots usa le f r conne tor

mou nting, se Fig ure 2 a nd Fig ure 3)

Table 1 — CTI buidin bloc s g e te config ration

W or se ca se:Hi gh-en t est syst em a pp ca t ionʊ2 c n e to slot s/ 3 bl anks

Ty i ca l: Mi d-r a nge t est syst em a ppli ca t ionʊ1 c n e t or slot s/ 2 bl a nks

Ba si c:Low-en t est syst em a plca t ionʊ4 c n e t or slot s

N OT —p s = p sition (in t erch ang eable wit h term c nta ct in th is c n tex t )

Fig re 2 —CTI s st em 2 - slot re eiv r con e t or config ration

Fig re 3 —CTI sy stem config ration t o fix ture o t ions

4.8.2 CTI mod lar combin t ion framework d sig

Rul e 4.8.2: U nd er IE E Std 1 05 combi na ti on fra mew ork spe ci f a ti on (d eta iled in the RFI framework

spe ifica tion, Cla use 5), t he CTI fra mework sha ll prov isio t hree (3) bla nks a t slot 5, 10, a nd 25 to

prov isio a 1.52 cm (0.6 in) spa cing fr the protective shrou d s o t wo a d joinin g fix t ures

Pe mis i on 4.8.2: Combina tiona l framework req uirement ca n be implemented in an y o t wo method s: (a )

combining segmenteda ndc onti nu us fra mework (i ustra t ed in Figure 6), to frm a 2 -slot config ura tio

ma de up o three (3) segment ed 5.6 cm (3 in) wid e frames, wit h fur (4) connector slots ea ch, a nd one (1)

contin uou s 2 9 cm (9 in) wide frame, tha t supp rts furteen (14) connector lots that supp rts frame/blan k

spa cin g a t slots 5, 10, 25; or (b) mod ifyin g a 2 -slot cont inuous framewor k (i u stra ted in Fig ure 5 a nd

Figure 6), to prov isio t hree bla nks a t slots 5, 10, 25

4.8.3 CTI re eiv r foot print/sc le ble re uireme ts

Rul e 4.8.3a : C I rec iver fra mework fotprint sha ll be a sca lea ble combinationa l implemen t a tio t ha t ca n

be incremented from the sm a llest fotprint o a segmen t ed framework o f ur (4) connector slot s, a nd

ex pa nd a ble to 2 slots b a dd ing segmented a nd/or continuous framewor k inter v a ls, wh ile ma inta inin g

d own wa rd compa tibi t y wit h a n y sma ller fix t ure increment s (2 slots f r connectors a nd 3 slots fr shroud

spa cin g s) Either o the framework implementa tion s ca n be red uced to a n y interv a l segmented a t slot 5, 10,

a nd 25 wit h combina t ions t h a t ca n supp rt 4, 8, 14, 18, or 2 slots usa ble f r con nector mou ntin g All

conne t or configura t ions sha ll sa t isf the IE E Std 1 05 framework/connector spe ifications, Cla se 5 a nd

Cla u se 6, a nd CTI pin ma p I/ O configura tio a nd g enera l pin ma p req uirement s, An nex A

Rul e 4.8.3b: Physica l fotprint o t he CTI r c i v er fra mework sha ll be in a ccorda nce wit h framewor k

spe ifica tion, Cla u se 5, t ha t d escribes re eiv er framework u nd er IE E Std 1 05 segmented a nd cont in uou s

framewor k la out s, a s t he ex amples in Fig ure 4 and Figure 6 furt her i ust ra te Alt houg h t he re eiv er driv e

system implemen ta tio is suppler d epend ent, the CTI rec iver me ha n ica l d riv e system sha ll not ex tend

bey nd the d imensiona l env elo e o a stand a rd 4 3 cm (19 in) ra ck wid t h or height o 3 6 cm (14 in)

(includ in g hand le height);

Rul e 4.8.3c: The CTI spe ifica tio per mit s int eg ra tor or users to a dd increment al rec iv er framework,

a n ytme, to sa tisf a n y mix o fix t ure req uirements, as shown in Fig ure 1 and Figur e 3, tha t includ es

mu lt iple tier increment s (t wo t ier shown in Fig ure 1), in a ccord a nce with t he CTI pin ma p I/ O configura t ion

a nd g enera l pin ma p req uirem ents, A nnex A

Rul e 4.8.3d: Ov era ll ph ysica l siz o ea ch CTI r c i v er ti er, includ ing driv e a ssembles, sha ll not ex ce d

sta nda rd 19 in equipment ra ck wid t h in a ccord a nce wit h EIA /ECA-3 0-E (2 05) [B3], or 3 56 cm (14 in)

height, or protrud e from t he m ountin g pla te more than 8.8 cm (3.5 in)

4.8.4 CTI re eiv r phy ic l weig t re uireme t s

Rul e 4.8.4: Physica l weig h t o t he CTI rec iv er framework sha ll not ex ce d a max imu m o 5.63 kg (8.0 lb)

per 7.6 cm (3 in) frame inter v a l a nd 21.8 kg (4 0 lb) fr ea ch C I 2 -slot t ier, includ in g fly p pula t ed

connector mod ules a nd t he en g a g ement mechanism

4.8.5 CTI me h nic l e g geme t re uireme ts

Rul e 4.8.5: The CTI r c i v er me ha ni ca l enga gement system sha ll be in a ccorda nce wit h framewor k

spe ifica tion, IE E Std 1 05, Cla u se 5, a nd prov id e su fficient mecha n ica l a d vantag e to ov ercome t he

ph ysica l ma tin in sertio frce o a fully-p pulated int erfa ce and t he cant ilev ered fixture weight

requiremen t s, a nd a pply su fficient mechanica l a dv antag e to a ssure a 1 9 kg (3 lb) o ha nd le frc is not

ex ce d ed

Fig re 4 —IEEE 15 5 rec iv r s gme te framework ex ample

4.8.6 CTI fix ture weig t re uireme ts

Rul e 4.8.6: Ea ch CTI rec iv er 4-slot fra me i nc ement sh a ll su p rt a max imu m sta tic fix ture weight

(fix t ure fly en g ag ed t o re eiv er) o 4.54 kg (10 lb) ca ntilevered a t 38.1 cm (1 in) from r ec iv er ma ting

interfa ce wh ile me tin g cycle lfe, int er fa ce in sertio f rc , a nd ele trica l pa ra metric requirement s In

increment s o 4.54 kg (10 lb) per 7.6 cm (3 in) frame interv a l, a C I 2 -slot re eiver with six frame

interv als sha ll supp rt a ma x imu m o 2 6 kg (50 lb) a t 38.1cm (1 in)

N OT —Implemen t er/ u ser sh all prov ide ad d it i on al sa fet y su pp rt t o assist o erat or du rin g lft , an d prev en t in ju ry or

d ama g e t o eq u ipmen t , wh en en g ag in g / d isen g ag in g h ea vy fixt u re a pplca t ion s

4.8.7 Ov rsize fix t ure k eep-out are

Rul e 4.8.7: Fixture ma n u fa ct urer that ofer la rg e (ov ersiz ) fix t ure fotprints sha ll n ot int rud e o t he

dimensiona l a rea s an not a ted in Fig ure 5

Obse v ti on 4.8.7: The a rea to t he right is reserv ed fr o era t io o t he eng ag ing hand le The a rea below

the fix t ure is reser v ed fr fix t u re supp rt fa ci ties

CA UTION

Ma nu fa ct urers should be cog n iza nt o cantilev ered weight and other urrou nd in g interference fa ctors

t ha t may impa ct mplement a tio when standa rd fot print s a re ex ce ded

Figure 5 —Fix ture (ITA) fo t print restricte are s

4.8.8 Tra sp rt abi ty/mo i ty re uireme t s

Rul e 4.8.8: CTI sha ll me t tra nsp rta bi t y/ mobi t y req uiremen ts per the IE E Std 1 05 RFI

env iron menta l/qua lit y spe ifica tions, d efined in Cla u se 4 a nd Cla use 5 o the sta nd a rd A fully a ssembled

CTI (fra mewor k, con ne t or modules, conta cts, and en g ag ement mechanism) sha ll wit hstand a 5 ms o

4 m/ s f r hock d rop test

Obse v ti on: 4.8.8: The intent o t he drop test s t o en su re the as embled inter fa ce does not d efr m or

other wise be ome u n usa ble ifi is “d ro ped ” d urin a ssem bly or epa ir The cond it io o th is t est nclud es

t he inter fa ce a s a stand -a lone o je t, impa cted o a ll cor ners a nd fa ces a t a 5 ms o 4 m / s f r shock d ro

test frc

Fig re 6 —IEEE 15 5 re eiv r contin ou framework e ample

4.9 Rel a i ty re uirement s

4.9.1 R epe tabi ty/reprod cibi t y/int erc a g abi ty

Rul e 4.9.1: CTI d esig n sha ll confor m to d imen siona l and fu nctiona l requirement s defined in IE E Std

1 05 RFI env iron menta l/q ualt y spe ifica tion s, d escribed i n Clause 5 a nd Cla use 6, in order to a ssure

comp nent pa rt ntercha n g ea bi t y/ inter ma tea bi ty and inter opera bi ty bet ween comp nents from mult iple

v end ors Comp nent pa rts sh a ll rema in “o era tiona l” through lfe o the prog ram A n y pa rt cha ng es t ha t

a ffe t fr m, fit, or funct io cannot o solete ex istn pa rts

4.9.2 Me n time betwe n faiure req ireme t s

Rul e 4.9.2: CTI comp nents sha ll be d esigned a nd prod uced to perfor m wit hout fa ilure bet ween

esta blshed d ura bi t y/life-cycle req uirements Fa ilures sha ll be a sses ed to d eter mine cau se a nd core tiv e

actions MTBF da ta f r the CTI comp nent s sha ll be ca lcula t ed in a ccord a nce wit h MIL -HDBK-217 [B21]

4.9.3 Durabi ty a d c cle l fe

Rul e 4.9.3: Dura bi t y and cycle lfe f r CTI re eiv er/fixt ur e me ha nism sha ll ha ve a minimu m dura bi t y

ra ting o 25 0 0 cycles Con nector mod ule conta ct s sha ll ha v e a minimu m d ura bi t y ra ting o 10 0 0

cycles Cycle lmit s a re consid ered end o lfe requiring replac men t o wea ra ble items Manu fa ct urer sha ll

va lida t e confor ma nce to this spe ifica tio in a ccord a nce wit h the IE E Std 1 05 RFI q ua lifica tion

requiremen t s, Clau se 4, cycle t esting , and per framewor k spe ifica tions, Cla u se 5

4.10 CT I connector footprint/ parametric re uireme ts

4.10.1 IEEE 15 5 RFI st an ard compla c

Rul e 4.10.1a: C I sha ll be complant wit h the IE E St d 1 05 RFI stand a rd co nector spe ifica tions,

Cla u se 6, t ha t est a blshes t he Euroca rd DIN sta nda rd connector fotprint a s t he ba sis o CTI a rchit ect ure

Obse v ti on 4.10.1: Both com mercia l a nd rugg ed iz d v er ions (u nd er MIL-C-5 30 /17 -18 [B2 ] were

av a ila ble in a 2 0-pin, 4-row conne tor b t wo o t he t hre prima r y interfa ce suppler s Signa l mod ule

me ts t he hig hest lev els f r o en system, low-cost, perfr ma nce, COTS a cc pt a nce, a nd lev el o

applca bi t y, re eiv ing more t ha n 25% h igher g ra d e over a n y o t he other connectors rev iewed

Rul e 4.10.1b: CTI sha ll implemen t three DIN connector t ypes: (a ) sig na l; (b) p wer; a n d (c) RF coa x ; a s

defined in IE E Std 1 05 RFI sta nd a rd con nector spe ifica tions, Clause 6, a nd r ela ted connector

spe ifica tions, Cla u se 7 throu g h Clause 12

4 10.2 CTI re uireme t s for compl a c

Rul e 4.10.2: Suppler o systems sha ll sta te t heir deg ree o compla nce to IE E Std 1 05.1 usin g the

definitions o complance in 4.10.2.1 a nd 4.10.2.2

4.10.2.1 Me h nic l compla c

Rul e 4.10.2.1: To me t this crit eria , a man ufa ct urer sha ll a t the min imu m supply a n IE E 1 05 RFI

complant int erfa ce t ha t con forms t o a connect or per slot type t hat ma tches t he config ura t io shown in

Figure 2 Tha t is, the p wer connector is used in slot ½, t he 2 0-pin sig na l module in slot 3, etc

Obse v ati on 4.10.2.1: This lev el o compla nce only ensures t ha t ph ysica l con nector d a mag e wil not

result from instal ng a fix t u re (TA/ID) from one minimu m lev el compla nt system onto a d iferent

minimu m lev el complant syst em’s re eiv er It does n t ensu re tha t the pro er sig na ls wil be routed

4.10.2.2 F l compla c

This is t he highest deg re o complance a nd requires full slot -by-slot me hanica l a nd ele t rica l

compa tibi t y fr t he stated compla nce ca t eg ories d efined as f lows

Rul e 4.10.2.2 : To sta te full complance, a manu fa ct urer sh a ll me t a ll t he req uirements f r t he signa ls fr

ea ch slot a s identified in A nnex A, ex cept f r th e column s la beled “Re om mend ed a t trib tes.” No -

p pula ted mod ules should be bla nk (e.g , ifblock is “bla nk,” i ca be keyed nor maly; ifblock ha s

diferent pin out, i sha ll be keyed d iferently) Both t he full complance a nd the flowin g ca teg or y shal be

sta ted

The f lowing a re t he defined ca teg ories:

a ) Ca teg or y 1ʊThis is defined as me hanica lly and ele trica lly complant wit h t he A n nex A slot s

6 through 9 This is the ba sic stimulus-mea sur ment se tio o the pin ma p

b) Ca teg or y 2ʊThis is defined a s me ha n ica lly and ele t ricaly complant with An nex A slots 1

throu g h 9 This is t he ba sic stimu lu s-measurement plus p w er upples a nd switching o t he pin

ma p

c) Ca teg r y 3ʊThis is defined a s me ha n ica lly and ele tricaly complant wit h A n nex A slot s 6

throu g h 2 This is t he b sic st imu lus-mea surement plus d ig ita l, switchin g , and a d d itiona l

a na lo o t he pin ma p

d ) Ca teg r y 4ʊThis is full slot complance (me hanica l and ele trica l) fr slots 1 throu g h 2 o

the A nnex A pin ma p

e) Ca teg r y 5ʊThis is full slot compla nce (mecha nica l a nd ele trica l) fr a ll 2 slots o t he

A n nex A pin ma p

N OT —Partia lly c mplan t approach es shall rot at e keys 18 deg re s t o in su re t h at ph ysical an d /or ele trical d a mag e is

n ot in cu rre d

Obse v t i on 4.10.2.2: This lev el o compla nce en sures b t h me hanica l compa tibi t y bet we n systems

a nd ele trica l sig na l compa tibi t y/ int ero era bi t y bet ween systems fr the slot s includ ed in the ca teg ories

The ca teg ories represent sca la le increments ba sed o t he segmented a rchitecture and t he ele trica l signa ls

includ ed in the sca la ble o t ions

Pe m is i on 4.10.2.2 : Pins may a lso hav e les er or high er ca pa bi t y as id ent ified in A nnex A ta bles as

long a s the pin ma pping o A n nex A is met a nd the ca pa bi t y is o the same/simila r fu nctiona lit y For

ex ample, a n id entified d c p wer supply (DCPS) ca pa bi t y id entified in An nex A shou ld be matched wit h a

DCPS, not a n a c supply

Pe mis i on 4.10.2.2b: The d esigner o a complant system is a llowed to implement ca pa bi t y id entified in

A n nex A wit h n n -cla ssica l in strumen ts

4.10.3 Sta d rdize k ey in

A stand a rdiz d keying a rra n gemen t is req uired to supp rt he compla n t int er fa ces Ea ch 4-slot se tio o

the IE E 1 05 RFI int er fa ce h a s a t op a nd b tt om key a s sh own in Figure 7 Ea ch key is set n a hex a g ona l

socket t ha t a llows one o six rota tional p sitions Therefre, wit h t he top a nd b ttom key bein g

i nd epend ently v a ria ble, the keyin g o one 4-slot segment ca hav e one o 36 d iferent keying a rra n g ements

Rul e 4.10.3 : S stems (e eiv ers a nd ITAs) tha t implemen t a me hanica lly or fully compla nt in t erfa ce as

defined in 4.10.2 a nd su pa rag ra phs sha ll implement the keyin g a s shown in Fig ure 7

Fig re 7 —Sta d rdize k ey in for compla t systems (rec iv r view)

Rul e 4.10.3b: S stems t ha t ha v e segments tha t a re non-complant per the d efinitio o 4.10.2 shall

implement a d iferent keyin g o tion The o tio used sha ll n t d uplca te a n y o t he keyin g o tions shown

fr a complant in terfa ce f r a n y se tion The g oa l is to pr v ent a n y a bi t y to mount a complant ITA on

a n y non -complant rec iv er or a non-complant ITA o a compla n t re eiv er

4.10.4 Po ulation polc

Rul e 4.10.4 : A test system dev elo er sha ll f low a set or d er o pre edence in t he sele t io o t est as et s

a nd the a ssocia t ed pins from t he pin ma p The flowing proc s sha ll be flowed :

a ) Ident if a n un u sed t est a sset/instr u ment t ha t meet s t he mi nimum test req uirements

b) Ifthe a sset/instr u ment is pa rt o a g roup o lke-ca pa bi ty as et s, u se t he lowest n u mbered ,

a v a ila ble (unu sed) a sset fr th e test

c) Proc ed in lke fshio fr the entire g roup o simia r a sset s

d ) Ift he mi nimum req uired ca pa i t y as et s be ome completely used (implemented ) in t he TPS,

proc ed to utilz the nex t highly ca pa bi t y a sset/ instr u ment

e) Ifthis a sset/ in stru ment is pa rt o a g roup, flow t he same ru les in wh ich t he lowest numbered is

utilz d fir t

Rul e 4.10.4b: A TPS dev elo er sha ll flow a set order o prec dence in the sele t io o t est a sset s a nd

pins from the pin ma p The flowin g proc s sha ll be flowed:

1) Sele t a n un used test a sset /in st rument t ha t meet s t he mi ni mum req uirements fr the test

2) Ifthe as et/ in stru ment is pa r t o a g roup o lke-ca pa bi t y a ssets, use t he lowest n u mbered ,

a v a ila ble (u nu sed ) a sset fr th e test

3) Proc ed in lke fshio f r the entire g ro p o simila r a sset s

4) Ift he mi ni mum req uired ca pa i t y as et s be ome completely used (implemen ted ) in t he TPS,

proc ed to utilz t he nex t highly ca pa bi t y a sset/ instru ment These should a lso be implem ented

from lowest n umbered a sset to higher n u mbered a sset

5) Ifthis a sset/instr u ment s pa rt o a g roup, f low t he same ru les in wh ich the lowest n umbered is

utilz d fir t

Re omm en ati on 4.10.4: Refer t o A nnex A ta bles f r cla rifica tio o a sset ca pa bi ties and how as et s a re

nu mbered

4.10.5 CTI con e t or parametric re uireme ts

Rul e 4.10.5: C I connector module wit h conta ct s sha ll comply wit h the d efin ition s cont a ined in IE E Std

1 05 RFI co nector spe ifica tions, Clause 6, a nd rela ted connector spe ifica tion s, Cla u se 7 throu gh

Cla u se 12, tha t sa tisfies t he respe tiv e pa rametric req uirements d efined b Ta ble 2

Table 2 —CTI con e tor module/ cont act mod le performa c req ireme t s

Si gna l c nta ct /m od le

Op rat in g v olt ag e: 3 0 Vd c max

Op ratin g cu rren t: 3.0 Ad c c nt inu ou s

Conta ct resista n ce: 10 Pȍ max

Insu lat i on resist an ce: 5.0 x 10 9 ȍ min

Fo tprin t : 0 5 in squ are pin s on 0.1 i n c n t e rs arran g ed in 4 row x 5 pin mu lt iples

Ma t in g frc : 2.0 oz / pin max

Modu le fotprin t: 2 0 p sit i on s i n 4 c l u mns

Powe m od ul e/ cont a ct

Op rat in g v olt ag e: 3 0 Vd c max

Op rat in cu rren t: 2 A d c/a c rms c n t in uous/fre st dg /a mbien t a ir

Ch a ra ct eristic imp d : n/a

Insu lat i on resist an ce: 5.0 x 10 9 ȍ min

Ma t in g frc : 18 o / pin ma x

Modu le fotprin t: 5 p sition s in 3 c lu mns, or 15 p sit i on s in 8 c l u mns

Table 2–CTI con e tor mod le/conta t module performa c re uireme ts (co tinu ed)

Coa x mod l e/ conta c t

Freq u en cy ban d wid t h : d c 3 GHz

Op rat in g v olta g e: 15 V ac, rms

Contact resista n ce: 10 Pȍ max

Vol tage sta n d in g wa v e rat io

Ch aract eristic imp d: 5 ± 2 ȍ

Insu lat i on resista n ce : 10 0 0ȍ min

Modu le fotprin t: 5 p sition s in 3 c lu mns or 15 p sit ion s in 8 c l u mn s

4.1 CT I pin map requireme ts

4.1 1 CTI s ale ble/mod lar pin map config ra on

Rul e 4.1 1a : The CTI sca lea le pin ma p con figura t io sha ll supp rt sca la bi t y (t he use o les t han a full

tier inter fa ce as prev iously discussed in 4.8.3), t hroug h the d istribut io o sta t io resour ces a s defined in

CTI pin ma p I/O con fig ura tio a nd g enera l pin ma p req uiremen ts, A nnex A

Rul e 4.1 1b: The CTI configura tio sha ll a pply the fiv e (5) connector mod ules: (a ) sig n a l, single slot 2 0

p sition; (b) p wer, sing le slot 59 p sit ion; (c) p wer, d ouble slot 1 2 p sit ion ; (d ) RF coa x , sin g le slot 59

p sit ion; and (e) RF co x , double slot 1 2 p sition; in t he con fig ura t io shown in Fig ure 2, a nd in

a ccorda nce wit h RFI con nector spe ifica t ion, con nector spe ifica t ions, Cla se 7 throu gh Cla use 12 o IE E

Std 1 05

Rul e 4.1 1 : The CTI configura tio sha ll be implemented in inter v a ls con for min to framewor k

segment a tio in a ccord a nce wit h RFI framewor k spe ifica t ion, Clause 5 o IE E Std 1 05, t ha t supp rt s

mou ntin o connector t ypes in inter v a ls o fur (4), f ur (4), furteen (14), a nd fur (4) slots, or a n y

reduced fot print, a s det er min ed b the spe ific a pplca t ion

4.1 2 CTI pin map I/O c t ego e

Rul e 4.1 2: The CTI conn ector config ra tion, a s i ust ra ted in Fig ure 2, sha ll be implemented in

accorda nce with d et a iled C I pin ma p I/O configurat io a nd g enera l pin ma p req uiremen t s, A n nex A

These req uirements shal be d iv id ed into sev era l I/O p rametric ca teg ories, d escribed a s f lows, and

distributed in scalea ble segments, to a ssure test sig na l ma pping is a ma inta ined fr a ll CTI a pplca tio s

The f lowing d escribes t he genera l pin ma p ca teg ories:

a ) Dig ita l I/O

b) A na lo instru men ta tion

c) Prog ra mma ble a c/ dc loa d

d ) Prog ra mma ble a c/d c p wer upples

e) Bus I/O

f) Switchin g implementa t ion

4.1 2.1 Digital I/O

Rul e 4.1 2.1a: CTI sha ll implement a sca lea ble d ig it a l I/O pa ra metric/ pin ma p co figura tio in

a ccorda nce wit h CTI pin ma p I/O configura tio a nd g enera l pin ma p req uirement s, An nex A

Rul e 4.1 2.1b: C I d ig ita l I/O sha ll be a ppled utilzin g Euroca rd DIN/ MIL-DTL-5 30 / 18 4-row 2 0

p sit io con nect or desig spe ifica tion s in a ccorda nce wit h IEE St d 1 05 RFI st a nda rd connect or

spe ifica tions, Cla u se 7 throu g h Clause 12

S g es i on 4.1 2.1: Dig ita l I/O signa l chan el ma be implemented with 2 0 d iscrete wires, 10 twisted

pa irs, or two pins per chan nel o precisio p intto-p int 50 ȍ ma tched imped a nce wiring ha vin g a

ba ndwid t h from d c to 750 MHz to a ma x imum o 10 cha n nels increment s (2 0 pins), a s nec s a r y to me t

sele t ed ATE d ig ita l req uirem ents

4 1 2.2 An log in trume ta on

Rul e 4.1 2.2a : CTI sha ll implement a sca lea ble AI (AI) I/O pa rametric/pin ma p con figura tion in

a ccorda nc with CTI pin ma p I/O config ura t io a nd g enera l pin ma p requirements, An nex A, a nd

subsequent req uirements CTI AI I/O shall be implem en ted utilzin g eit her the CTI sig na l or coa x

connectors a s subsequent ly d escribed

Rul e 4.1 2.2b: Ifimplemented , the CTI AI I/O sha ll a pply Euroca rd DIN/MIL -DTL-5 30 /18 4-row 2 0

p sitio connector d esig spe ifica tions in a ccord a nce wit h IE E Std 1 05 RFI connect or spe ifica tion s,

Cla u se 7 throug h Clause 12

S g es i on 4.1 2.2: AI I/O sig na l cha n nel may be implemented wit h 2 0 discrete wires, 10 twisted pa ir ,

or two pins per chan nel o precision p int-to-p int 50 ȍ ma tched impedance wirin g h a v in g a ba ndwidth

from d c t o 750 MHz t o a max imu m o 10 cha nnels increments (2 0 pins), or a s nec s a r y t o me t sele t ed

ATE d ig ita l req uirement s

Rul e 4.1 2.2c: Ifimplemen t ed , the C I AI I/O sha ll a pply RF co x ia l siz 16 co ta ct wit h RF coa x siz

16 connector module d esig a nd wirin g spe ifica tions in ac orda nce wit h IEE Std 1 05 RFI connector

spe ifica t ions, Cla u se 7 t hrou g h Clause 12

4.1 2.3 Programmable a /dc loa

Rul e 4.1 2.3a : CTI sha ll implement a sca lea ble prog ramma ble d c loa d I/O pa rametric/pin ma p

configura tio in a ccord a nce w ith CTI pin ma p I/O con fig urat io and g enera l pin ma p req u iremen t s, A n nex

A

Rul e 4.1 2.3b: CTI prog ramma ble d c loa d I/ O sha ll be a ppled ut ilzin g t he CTI p wer connector using

23 a mp con t a ct n a 59 or 1 2 p sitions p wer mod u le con n ector d esig in a ccord a nce wit h IE E St d 1 05

RFI connect or spe ifica t ion s, Cla use 7 through Clause 12 These conta cts sha ll be d era ted to 18 A, when

six or more a re clust ered a dja cent to ea ch ot her a nd o era t in g simulta neously and contin uously a t t ha t

current lev el

S g es i on 4.1 2.3: Discrete 23 amp pin s should be implemented with 14 AWG MIL-spe (hig h

tempera ture a nd flamma ble resistant) discrete or t wisted pa ir wiring

Pe m is i on 4.1 2.3: CTI prog ramma ble d c loa d I/O where a pplca ble ma utilz low level (current <3 A)

discret e I/O sig nal pins u sin g Euroca rd DIN 41612 a nd MIL-C-17 / 18 5 row 2 0 p sit io con nector

desig spe ifica t ion s in a ccord a nce wit h IE E Std 1 05 RFI connect or spe ificat ions, Cla use 7 t hrou gh

Cla use 12, a nd t he CTI pin ma p I/O con fig ura t io and g enera l pin ma p req uiremen ts, A n nex A Discrete

pins ma be implemented wit h 2 AW G d iscrete or t wisted pa ir wirin g

4.1 2.4 Programmable a /dc p wer s p ly

Rul e 4.1 2.4a : CTI sha ll implement a sca lea ble prog ram ma ble d c/ a c p wer supply I/ O pa rametric/ pin

ma p configura tio in a ccorda nce wit h CTI pin ma p I/O configura t io and g enera l pin m a p requirement s,

A n nex A

Rul e 4.1 2.4b: CTI prog ra m ma ble d c/a c p wer supply I/O sha ll be nor ma lly a ppled uti zing t he CTI

p wer connector usin g 23 amp co ta ct in a 59 or 1 2 p sitions p wer mod ule connector d esig

spe ifica tions in a ccord a nce wit h IE E Std 1 05 RFI connector spe ifications, Clause 6 a nd Cla use 8

These conta ct s sha ll be d erat ed t o 18 A, wh en six or more a re clust ered a dja cent to ea ch ot her, a nd

o era ting simu lt aneously and contin uou sly at tha t current lev el

S g es i on 4.1 2.4: Discrete 23 amp pin s should be implemented with 14 AW G MIL-spe (hig h

tempera ture a nd flamma ble resistant) d iscrete or t wisted pa ir wiring

Pe mis i on 4.1 2.4: C I prog ramma ble dc/ a c p wer supply I/ O wh ere a pplca ble ma utilz low -lev el

(current <3 A) discrete I/ O sig na l pin s using Euroca rd DIN/ MIL-DTL-5 30 / 17 / 18 4-row 2 0 p sit ion

connect or d esig spe ifica tions in a ccord a nce wit h IE E Std 1 05 RFI con nect or spe ifica t io s, Clause 7

throug h Cla u se 12 Discrete pins sha ll be implemented wit h 2 AWG d iscrete or t wisted pa ir wiring

4.1 2.5 Bu I/O

Rul e 4.1 2.5 : CTI sha ll implement a sca lea ble bus I/ O pa ramet ric/pin ma p config ura tio in a ccorda nce

wit h CTI pin ma p I/O con fig u ra tio a nd g enera l pin ma p requirement s, A n nex A

Rul e 4.1 2.5b: C I bus ca pa bi t y sha ll be a ppled utilz ing Euroca rd DIN/MIL-DT -5 30 / 18 4-row

2 0 p sit io con nect or desig spe ifica tion s in a ccord a nce wit h IE E St d 1 05 RFI st a nd a rd connect or

spe ifica t ions, Cla use 7 throug h Clause 12

S g es i on 4.1 2.5: Bus I/O sig a l channels ma be implemen ted wit h 2 0 d iscrete wires, 10 t wisted

pa irs, or two pins per chan nel o precisio p int-to-p int 50 ȍ ma tched impeda nce wiring ha v in g a

ba ndwid t h from d c to 50 MHz to a ma ximum o 10 cha n nels increment s (2 0 pins), a s ne es a r y to me t

sele ted ATE bus req uirement s

4.1 2.6 Switc in impleme t ation

4.1 2.6.1 Ge eral re uireme ts

These interfa ces d escribe t he ha rdwa re requirements nec s a r y t o swit ch stimu lu s, resp nse, a nd p wer

signa ls bet we n t he UU T a nd the test instru menta tion The switchin g ma be implemented in v a rious ways

Obse v ti on 4.1 2.6.1: The combina t io o t he swit ch a nd CTI I/ O prov ides t he A TS dev elo er the

a bi t y t o sele t v a riou s sig nal pa ths bet ween the instru men t a nd U U T Ex amples o switch implement a t ions

a re shown in Figure 8 a s: (a ) benchtop unit s; (b) integ ra ted switch ca rds; (c) ra ck -mou nted unit s; a nd (d)

switch modules meeting publshed ind u str y stand a rd s such a s (but not imited to) LX I, USB, VME, V XI,

a nd PX I

Fig re 8 —Swit chin prod ct d sig s

4.1 2.6.2 Swit ch con erns

Obse v ati on 4.1 2.6.2: Gen era l req uirements fr t he swit ch inter fa ce, d escribed in Ta ble 3 a nd Ta ble 4,

were d eriv ed from ma n y so rces representn g g enera l ind ustr y need s, Gov ern ment a nd commercia l

interest s, Gov ern ment o en -system d ire t iv es, indu st r y t echnolo y t rends, Gov ern ment/ a erospa ce t est

requiremen ts prev iou sly d escribed (functional test req u iremen ts), a nd test ind ustr y switch d efa cto

sta nd a rd s The CIW G a nd CTI Switching Ta sk Group rev iewed the wid est spe tru m o requirements,

leg a cy supp rt req uirements, a nd other interest s to a ssure switch elemen ts were add res ed These

req uiremen ts were ex tra ct ed from t he env elo e o t he ca ses rev iewed This is ex pe t ed t o provide

ca pa bi t y f r a lmost ev er y req uirement the solutio wil en co nter During t he review proc s sta nd a rd s or

prod ucts tha t could meet these req uirements were sought The switching philoso hies consid ered in th e

a na lysis a re t he f lowin g :

a ) Switchin g ou tsid e ATE—This a pproa ch incorpora tes switch ing in to the test fixture ba sed o the

U UT req uiremen ts This pla ces fina ncial b rden o the en d user since switchin g needs t o be

incorpora ted in man y test fix t ures This is a significa n t re u rrin cost

b) Switchin g in t he ATE—This a pproa ch integ ra tes t he swit chin g ca pa bi t y into the ATE a nd

trea ts i a s ad d itiona l in stru menta tion This simplfies test fix ture d esign, red uces TPS cost, a nd

pla ces t he switchin g und er control o t he ATE system so t wa re This ca n be a ccomplshed in

one o t wo ways:

1) Inte na l ha rdw i ri ng o in stru men ta tion to ATE switching The inter na l a pproa ch simplfies

test fix t ure d esig n and implemen ta tion; howev er, a performa nce tra d e-o fd iscussio resulted

in prov id in g instr u ment pa rt s d irectly a t t he C I Costs a ssocia ted wit h con nect ing the

inst r u ment s to the switch a re releg a ted t o the ele trica l co ne tiv it y wit hin t he ATS-to-U U T

interfa ce a da pt er

2) Exte na l ha rdwi ri ng o instr u menta t io to ATE switchin g in t he test fix t ure The ex t erna l

a pproa ch wil g rea tly increa se test fix t ure complex it y, however; t he TPS d ev elo er ha s g reater

flex ibi t y should hig her perfrmance in stru menta tio req uire uncompromising a cc s a t the

tester inter fa ce

S g est i on 4.1 2.6.3: The Critica l Inter fa ce W orkin g Group (CIW G) Rep rt sugg est ed c rta in switch

req uiremen ts tha t could implemen t COTS solut ions a nd preserv e t he need s o the Gov ern ment leg a cy

prog ra ms The f lowin g g oa ls were utilz d in a sses in sw itching cand id a tes:

a ) I widely a cc pt ed b indu st r y wit h multi-v end or sources

b) Ha s esta blshed d esig n definitio s

c) Ofer a full rang e o o tion s t o me t sig na l, p wer, a nd coa x requirements

d ) Supp rt s hig h lfe-cycle perfr ma nce and ma inta ina bi t y

e) I a v a ila ble tod ay in v olu me prod uctio a nd is in its ea rly pr od uct ife-cycle pha se

f) Prov id es a sca lea ble switch wit h a modula r framework d esig tha t per mits ATS integ rators to

incrementa lly augment t heir ystems through a d d-on/duplca tiv e fea t ures This wil ena ble them

t o me t wor t ca se req uirements wh ile ma inta inin g d own w a rd compa tibi t y wit h a n y sma ller

I/O increment

g ) Esta blsh es a common switch spe ifica tio tha t ofer mu lt i-vend or sources, is flex ible enou g h

to supp rt a wid e v a riet y o sig nal perfor mance/swich con fig ura tions (1x 2, 1x 4, 1x 8), a nd ca n

ev olv e wit h new test need s

h) Minimiz s pin out con figura t io to efe t g rea ter tra n sp rt a bi t y and re on fig ura bi t y is not

impa ired

i Red uces t he prolfera tio o switch d esig s

j) Defines a minimum set o perfor ma nce req uirement s t ha t wil meet t he Gov ern men t I/ O ba sic

switch need s Common I/O ba sic switch en v elo e t ha t supp rts leg a cy 1x 2, 1x4, 1x 8 wra

p-a roun d signa l casca d e TPS requiremen t s

Re omm en ati on 4.1 2.6.3: The integ ra tor d eter mines switch req uiremen t s ba sed o t he nu mber o

instr u ments and the flex ibi t y wit h wh ich t hey must be a ppled Switch d esig n s req u ire a compromise

bet we n d ire t wire perf r mance and switch flex ibi t y Th e CIW G conclud ed tha t switchin g in the ATS

wit h int erna l ha rd wirin g should be req uired t o a chiev e g rea ter cost-efe t iv enes a nd minimiz fix t ure

complex ity

4.1 2.6.4 CTI switc re uireme ts

Rul e 4.1 2.6.4: The C I sha ll emplo a sca lea ble switch tha t a pples h ig perf r mance a na lo switch

ca rd s fr a n y g enera l purp se high-end ATE system All switch fu nctional req uir emen ts shal be

implement ed d irectly t hroug h t he CTI t o supp rt eg acy switch req uirements, in a ccord a nc wit h CTI pin

ma p I/O con figura tio and g enera l pin ma p req uirements, A n nex A The d eta iled d escriptions o Ta ble 3,

Ta ble 4, Ta le 5, a nd Ta ble 6, a s wel a s Figure 9, prov id e a d d itiona l switch d efinition /req uirements to be

implement ed und er t he CTI S e ifica t ion

Table 3 —Sig al swit ch performa c re uireme t s

Vol ta g e, breakd own > =10 0 V d c

Sig a l 1x2, 4A

Cu rren t , swit ch ed 4 A ac/ d c

Vol ta g e, breakd own > =10 0 V d c

Table 3–Sig al switc performa c re uireme ts (continu ed)

Vol ta g e, breakd own > =10 0 V d c

Cu rren t , stea d y stat e 2.0 A

Cu rren t , swit ch ed 2 A ac/ d c

Imp d an ce, sh u n t cap <0.5 ȝ)

Resist an ce t o g rou nd >10 0ȍ

Table 4 —Power swit ch performa c re uireme t s

Powe 1x1, 1 A

Cu rren t , st ead y stat e 10.0 A

Cu rren t , swit ch ed 10 A ac/ d c

Resist an ce t o g rou nd >10 0ȍ

Vol ta g e, brea kd own > 10 0 V d c