INTEGRATED FIBER-OPTIC RECEIVERS: AN OVERVIEW
1.4 OVERVIEW OF FIBER-OPTIC RECEIVER DESIGN
1.4.4 Clock Extraction and Data Recovery
Clock extraction circuits for nonreturn-to-zero (NRZ) data can be grouped into two main categories: open loop filters, and closed loop synchronizes. Formally, filters have been used almost exclusively in high bit-rate receivers. With this open loop technique, the periodic timing information is extracted from the data by first using a nonlinear edge-enhancement circuit to generate a spectral line at the bit rate. The signal is then passed through a narrowband filter, centered at the bit-rate frequency, as shown in Fig. 1.6. The filter must be highly selective (highQ) in order to minimize the phase-jitter in the clock signal. Typically, surface-acoustic-wave (SAW) filters have been used for this purpose, however commercially available SAW filters are limited to a frequency of less than 3 GHz [26].
The open-loop technique is attractive because it doesn’t suffer from instabilities and nonlinear problems, such as frequency acquisition and cycle-slipping. However, open- loop systems usually need to be manually adjusted to center the clock-edge in bit- interval. This one-time adjustment will not track phase offsets due to temperature variations and component aging. The filter is also external to the receiver electronics and bulky, leading to both packaging and interconnect problems.
In contrast to an open loop filter, a closed loop system is integrable, and can continually compensate for changes in the environment and the input bit-rate. This technique requires that a voltage-controlled oscillator (VCO) be tuned by a suitably filtered error signal, so as to align its transitions to the center of the bit interval. This is illustrated conceptually in Fig. 1.7. Although the loop has the desirable property of being self- adjusting, complications due to nonlinear frequency acquisition and tracking makes the circuit difficult to design.
Integrated Fiber-Optic Receivers 17
Data In
EDGE
DETECT DELAY
PHASE ADJUSTMENT
DECISION Data Out
Clock
PHASE DETECT
LOOP
FILTER VCO
ON-CHIP PLL
ε
Figure 1.7 Block diagram of a clock recovery and data retiming circuit using a PLL.
Clock recovery circuits presently limit the obtainable data-rate of multigigabit-per- second integrated fiber-optic receivers. Currently, practical receivers that include methods for extracting the clock signal are limited to about 2.5 Gb/s, both for systems using a SAW filter for clock extraction [27, 28], and systems using a PLL [18], although recently reported experimental circuits are fast approaching the 10-Gb/s range [19].
Several groups are working to produce practical 10-Gb/s integrated fiber-optic re- ceivers. Among them are: AT&T, Bellcore/Rockwell, NTT, NEC, Ruhr Univer- sitat in Bochum Germany, and UCLA/TRW. Preamplifier and postamplifier ICs [29, 30], an amplifier and mixer [31], a demultiplexer and phase-aligner IC [32, 33], a phase/frequency-detector [34, 35], a PLL (phase-lock loop) [36, 37], and a clock- extraction and data-retimming circuit [19] are among the circuits presented recently.
Thus far, all of the main functional blocks of a 10-Gb/s receiver have been demon- strated with one notable exception — the clock recovery circuit. This circuit is the most complicated, and the most difficult to design; it’s not surprising that development of high-speed clock recovery has lagged behind development of the simpler amplifier and demultiplexer circuits.
One of the major thrusts of this book will be in developing the clock extraction and data recovery circuit. Several special challenges exist in designing a single chip system. In keeping with the goal of economy, the amount of external trimming should be minimized. For an integrated solution, a phase-locked loop will be used.
Several advantages of integration will be exploited in this circuit. For example, simple oscillator circuits, such as multivibrators and ring oscillators, can be realized with sufficiently low phase-jitter, and PLLs can be used to further purify the spectrum and reduce low-frequency jitter and drift. Also, one can take advantage of the matching of devices to obtain continual phase alignment and frequency acquisition.
A conceptual diagram of a self-correcting clock-recovery and data-retiming circuit using this technique is shown in Fig. 1.8. The clock recovery loop measures the clock- phase and aligns it so as to minimize the bit-error-rate. Since we propose to design
18 Chapter 1
Data
Σ VCO
PHASE DETECTOR
Phase error correction
EDGE DETECTOR
DECISION CIRCUIT
F(s)
Data out D Q
Clock Self-Adjusting Clock Recovery PLL
Figure 1.8 Block diagram of a self-adjusting clock recovery circuit.
a fully-integrated receiver, no external delay lines can be used for tuning. Therefore, the optimal phase alignment of the clock recovery circuit must be done on chip; a self-correcting circuit additionally requires the decision circuit to be included in the feedback loop for final clock-phase adjustment. This is shown explicitly in Fig. 1.8 as the phase error correction signal.
Practical High-Speed Clock Recovery and Data Retiming Circuits
Clock recovery circuits are explained in considerable detail in chapters 4 and 5. Here we will briefly describe three self-adjusting circuits capable of high-speed operation.
One method of recovering the clock was first described by Alexander [38]. A block diagram of this approach is shown in Fig. 1.9. The basic idea of this circuit is to use the decision flip-flop in conjunction with an identical reference flip-flop to obtain a differential error signal. The sample (a) is the previous data symbol, and the sample (c) is the current data symbol. The reference sample (b) is taken at the data crossover. The timing of these three samples is illustrated in Fig. 1.10. The digital logic block looks at the three samples, and decides whether the clock was early, late, or indeterminate for each sampling interval. This decision is averaged, and used to control a VCO.
A second method is a variation on the early-late gate technique. This circuit, illustrated in Fig. 1.11, is similar to the one previously described, in that it uses identical decision circuits to arrive at a differential phase-error measure. In this circuit, data is detected using an early clock, a late clock, and an on-time clock. By subtracting the late from the early signal, and multiplying by the retimed data to remove random polarity variations, a phase-error signal is derived, which will go to zero when the early and
Integrated Fiber-Optic Receivers 19
D Q
D Q Data - in
CENTER
TRANSITION
Data - out Clock - out
VCO
D Q
D Q
F(s)
PHASE / FREQUENCY LOGIC ε
(a)
(c)
(b)
Figure 1.9 A self-correcting phase detector for a clock-recovery and data retiming circuit.
(b) (c) (a)
T
On- Time (b) (c)
(a) T
Early (a) = (b)
(b) (c) (a)
T
Late (b) = (c)
Figure 1.10 Illustration of timing of samples in Alexander’s clock recovery and data retiming circuit.
Data In
VCO
Phase error
F(s) ε
MATCHED FILTER
S/H S/H
Clock
Data - Out
Early Data Cross-over
Samples
Σ +
-
S/H
S/H
Late
X
Figure 1.11 An early-late gate clock synchronizer for data retiming.
20 Chapter 1
Data
In VCO
Phase error
F(s) ε
MATCHED FILTER
S/H S/H
Clock
Data - Out
Data Cross-over Samples
X S/H
+/-
sample on positive and negative transitions
+/-
+\-
Figure 1.12 Block diagram of a data transition tracking loop for timing recovery and data regeneration.
late clocks are exactly centered about the optimal sampling point. The usual depiction of the early and late gates as dumped integrators has been replaced by a matched filter with sample-and-holds, which facilitates high-speed operation. An alternative implementation of this circuit could use two levels of bit-interleaving, so that dual track-and-holds can be multiplexed to perform the sample-and-hold function, and the VCO would run at half the data rate. Since the early- and late-gate correlators are matched to the decision circuit correlator, their delay times will track each other, and the circuit will be automatically, and continually, optimally phase aligned.
A practical clock recovery circuit will require some type of frequency acquisition aid.
A PLL-based clock recovery circuit is only capable of pulling-in a frequency error of the same order of the closed-loop bandwidth, which is typically a factor of 1000 less than the bit-rate. Therefore, without frequency acquisition aids, the VCO center frequency will have to be stable to within 0.1% over all processing and temperature variations, which is quite a stringent specification.
A third clock recovery circuit that was adopted for application to 10-Gb/s systems is known as a data transition tracking loop (DTTL) [39, 40]. A conceptual block diagram of DTTL circuit is shown in Fig. 1.12; this circuit is discussed in detail in chapter 5, and simulations results are given in chapter 10. A frequency discriminator was added to the DTTL to increase the pull-in range, and the circuit can be implemented using two levels of bit-interleaving. A block diagram of the interleaved DTTL with frequency detection is shown in Fig. 1.13. This circuit has several desirable properties as discussed in section 5.4; these advantages are briefly outlined in table 1.2.
Integrated Fiber-Optic Receivers 21
Data In
VCO
Fp(s)
ε
Q (lead) I (lag)
M U X + MATCHED -
FILTER
M U X + -
T/H
T/H T/H T/H
M U X + -
T/H T/H
Clock Data-Out
f = BT / 2 -
Data Cross-over Samples M
U X + -
T/H T/H
Σ
Phase Error
B BT / 4
∆fε Σ
+ -
~ ~ B B~ ~ T / 4
Frequency Error Ff(s)
LOCK DETECT GATE
Figure 1.13 Block diagram of an interleaved DTTL with frequency detection.
Advantages of DTTL Clock Recovery Circuit Can function at very high-speeds Is inherently self-adjusting
Using Sample-and-holds before decision circuits improves sensitiv- ity
Phase-detector function is monotonic over the bit interval
[;T=2;T=2], improving phase-tracking and frequency-acquisition The phase-error is independent of the transition density, eliminating pattern dependent jitter.
Resampling the phase error only after a data transition eliminates ripple, and significantly reduces ripple-induced phase-jitter
Table 1.2 Advantages of data transition tracking loop for clock extraction and data retiming of random NRZ data.
22 Chapter 1
In order to understand the design trade-offs employed in the optimization of circuit performance, a solid grasp of the fundamentals of communication theory, as it applies to high-speed, broadband digital receivers is required. This theory is outlined in the remainder of Part I, and special emphasis in placed on clock recovery in broadband systems. The circuit designs, and measured results of the fabricated test structures will be presented in Part II.