A straightforward application of a frequency detector to a clock recovery PLL is shown in Fig. 5.1(a). In this application, the error signalis the sum of a phase-error term, and a frequency error term. One requirement of the frequency detector is that its output go to zero when frequency acquisition has been obtained. Problems with this approach is that ripple from the frequency detector can still exist when the loop is in lock, causing excess phase-jitter. Also the frequency detector output needs to be taken into consideration when optimizing the loops dynamic response. Some systems use a dead-zone that breaks the frequency detector (FD) from the loop when the phase-error is within a zone surrounding zero. This prevents the FD from interfering with the phase acquisition process. A second alternative is to use a phase/frequency detector (PFD) as shown in Fig. 5.1(b). Although this may seem a trivial extension, later we will see that, with simple modifications, both phase, and frequency can be detected with the same circuit, thus eliminating duplicate functions.
Practical High-Speed Clock Recovery 261
Data VCO
Ff(s)
Frequeny error Phase error
PHASE DETECT
FREQ DETECT
εf
Fc(s)
εc Fine
Coarse
Data VCO
Ff(s)
Phase / Frequeny error Phase error
PHASE DETECT
PHASE/
FREQ DETECT
εf
Fc(s)
εc Fine
Coarse
(a) (b)
Figure 5.2 Bad ideas for using frequency acquisition aids for a VCO with two coarse and fine tuning inputs.
A Couple of Bad Ideas
In some cases it is desirable to have a VCO with two controls. One is a coarse adjustment used to set the center frequency close to the bit-rate, the other is a fine adjustment that is used to track the input, once the frequency error is within a specified range. A tempting idea, that invites all types of trouble, is shown in Fig. 5.2(a). Since no real integrator can be realized without dissipation, a VCO input signal will have to be continually updated to maintain its value at the proper level. This will require the error signalsf andc to periodically deviate from a zero value. However, any significant deviation from zero in the signalc will require a frequency error, and several cycle-slips will have to occur before the tuning signal can be readjusted to the proper value.
Another bad idea is to replace the FD in Fig. 5.2(a) with a PFD, as shown in Fig. 5.2(b).
Since a non-zero value can appear at the output of the PFD in the absence of a frequency error, lock can be maintained without intermittent cycle-slips. However, now we have two loops that are fighting each other for control of the VCO phase. Provided that this condition produces a steady-state output, the resulting phase will most likely not be what is desired.
Techniques for Simultaneous Coarse and Fine Tuning
When adjusting two signals simultaneously, there must be sufficient degrees of freedom for a solution to exist. In other words, we can not try to drive the phase of a VCO to two different values simultaneously. A master-slave approach to setting the center frequency is shown in Fig. 5.3. The master-loop is used to acquire the input frequency.
262 Chapter 5
Data
VCO
Fc (s) Frequeny error
Phase error PHASE
DETECT FREQ DETECT
εc Fine
Coarse
VCO
Ff (s)
εf Fine
Coarse Feed Forward Center Frequeny
Adjust
FLL MASTER LOOP
PLL SLAVE LOOP
Ref
Figure 5.3 Illustration of a master-slave approach for simultaneous coarse and fine adjust- ment of the VCO controls.
Since the clock from the master loop is not the clock that samples the data, cycle- slipping is allowed in the master clock. It is only in the slave clock where cycle- slipping is forbidden. Therefore, an FD can be used in the master loop, creating a frequency-locked loop (FLL), that will not maintain phase-lock. The tuning signal can be fed forward to the slave loop, which contains a VCO matched to the master VCO. Using a filter in the feedforward path decouples the dynamic response of the two loops. For example, the master filterFc(s)can be adjusted to meet specific dynamic response requirements. Then using a lowpass filter in the feedforward path, can make the slave-loop appear as if the coarse tuning signal is a dc value. The master-slave approach can be used to reduce the steady-state phase offset, without requiring a high dc gain in the slave loop. The steady-state phase offset in a PLL is proportional to the frequency deviation of the input signal from the center-frequency of the VCO, and inversely proportional to the dc gain. The master-loop will reduce the frequency offset to within the matching accuracy of the VCOs, allowing the slave-loop to operate in the center of the dynamic range, without a high dc gain.
Delay-Locked Loops for Fine-Tuning the Clock Phase An alternative approach for adjusting the clock phase, after frequency and phase acquisition is established is shown in Fig. 5.4. In this circuit a PFD must be used so that the top-loop can maintain phase- lock. The resulting loop is a phase/frequency-locked loop (PFLL). However, the final VCO phase may still need compensation to achieve optimal clocking of the input data stream. This can be achieved by using a delay-locked loop (DLL), where a precise,
Practical High-Speed Clock Recovery 263
Data
VCO Fc (s)
Phase / Frequeny error
Phase error PHASE
DETECT PHASE/
FREQ DETECT
εc
Ff (s)
εf PFLL
DLL
ELECTRONICALLY TUNABLE
DELAY DELAY
Data
Phase error PHASE
DETECT EDGE DETECT
Ff (s)
εf DLL
ELECTRONICALLY TUNABLE
DELAY
DELAY
DELAY FIXED DELAY
(a) (b)
Figure 5.4 Clock recovery schemes using a voltage controlled delay for: (a) a clock extracted using a PLL, (b) a clock extracted using a bandpass filter.
self-adjusting, phase-detector measures the residual phase error, and fine tunes it to zero via a voltage controlled delay (VCD). It is also possible to replace the PFLL in Fig. 5.4(a) with a bandpass filter clock extractor as shown in Fig. 5.4(b). This approach was used by Wennekers et al. [3], to achieve 10-Gb/s operation, where the clock was originally extracted with a dielectric resonator filter.
In this section we have illustrated several possible methods for incorporating a fre- quency detector into the design of clock recovery circuits. Because of the important role FDs play in aiding PLL frequency acquisition, we will now present several imple- mentations of FDs and PFDs.