4.6 PARASITIC-DELAY INSENSITIVE CLOCK RECOVERY SCHEMES
4.6.4 Analog Devices Transition-Density-Independent Circuit
A problem with all of the phase-detectors that we have discussed thus far, is that the dc value of the phase-error depends on the data transition density. As a result, the phase detector gain, and therefore, the loop gain, are proportional to the data-density. This causes variations in the dynamic response of the PLL, leading to pattern dependent jitter in the recovered clock. Data-density-dependency is an artifact of the phase-error going to zero when no transitions occur. If the phase-error is held in place during periods of no transition, then the phase-detector output will be the same for both dense and sparse data. A phase detector, based on the Hogge circuit, that is data-density- independent was designed at Analog Devices by DeVito et al. [43], and utilized in the circuit of Lee and Bulzacchelli [44, 45]. A block diagram of this circuit is shown in Fig. 4.66. The first two decision circuits of Fig. 4.66 are the same as in the Hogge circuit. When a data transition occurs, a pulsep1is generated. The width ofp1 is
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ε
CL
Phase Error Proportional
Plus Integral
- +
CHARGE-PUMP INTEGRATION CIRCUIT
X1 X2 X3 X4
ε dt - +
Figure 4.67 Conversion of phase detector pulses to voltages by an up-down-down-up sequence of integrating currents.
linearly related to the clock phase,
t
1
=T=2+t
d +t
: (4.125)
The remaining three decision circuits and EXOR gates produce pulsesp2,p3, andp4, when a data transition occurs, all of which have a fixed width ofT=2+td. In Hogge’s circuit an estimate oftwas obtained by subtractingp2fromp1, which generates a pulse of widtht. When no data transitions occur the phase-error pulses are missing, and the resulting dc phase error is modulated by the data density.
The approach adopted by DeVito is to convert the pulse width information directly into a voltage by integration. The pulses are used to control switches as shown in Fig. 4.67 that controls an up-down-down-up sequence of integrating currents on the load capacitor.
A timing diagram showing the resulting phase error on the load capacitor for an early, on-time, and late clock is shown in Fig. 4.68. The clever aspect of this design is that the integrated value of the phase-error on the load capacitor in steady-state operation is the same for both dense, and sparse data transitions. Another nice feature is that the integration cycle takes two clock periods to complete. Therefore, when the data is dense, up integrations from one transition will cancel down integrations from the previous transition, and the phase detector will have no ripple for adjacent transitions, reducing the eventual clock-jitter.
Limitations of Devito’s Phase Detector Although Devito’s circuit solves the problem of data density dependence, it is limited in application to low and moderate bit-rates.
We saw that cascading two decision circuits limited the performance of Hogge’s circuit at high-speeds. This problem is exacerbated in Devito’s circuit because 4 decision circuits are cascaded. Therefore the clock phase error in the last decision circuit will be 3 times worse than in the Hogge circuit. The approximate bit-rate limitation is then
248 Chapter 4
Early On-Time Late
Data Clock
Main X1 Ref X2
ε dt
dc = 0 dc > 0
dc < 0
Ref X3 Ref X4
Figure 4.68 Timing diagram for data-density-independent phase detector.
given by
B
T
fmax
60
: (4.126)
The designed application of Devito’s circuit was for a 52-MHz and a 155-MHz circuit.
Using GaAs HBTs the approach may be good for bit-rates of from 300-Mb/s to 1-Gb/s.
Problems with Hogge’s and Devito’s circuits are that they use serial connections of decision circuits to estimate the phase error. Therefore, the decision circuit delay alters the sampling phase of successive decisions. The serial decision circuit delay is in the critical path; as a result, these circuits can not be pipelined. Pipelining, or bit-interleaving is only possible when all sampling is done in parallel. Instead of using resampling with a chain of flip-flops, as in the circuits of Hogge and Devito, appropriate time skewing of the samples can be obtained by using a multi-phase clock.
The sampled data can be clocked to deskewing registers for further processing. Since at the front-end, all sampling is performed with matched circuit, all of which are sampling the original data, and not retimed data, the parasitic delays of the sampling circuits will track each other. Variations in parasitics delays due to changes in the environment will be automatically compensated, and won’t degrade the accuracy of the final clock-phase estimate.
Based on these considerations, the circuit of Alexander is a prime candidate for high- speed clock recovery, because the two front-end flip-flops, generating the data and phase-control information, are operating in parallel. In the following chapter, practical modifications to the circuit of Alexander will be presented that are applicable for mono- lithic clock recovery and data retiming at bit-rates nearfmax=4. In addition, a novel data-density independent phase detector circuit will be presented, which implements
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all of the desired features efficiently, and is ideally suited to self-adjusting, PLL-based, clock extraction at data rates in excess of 10-Gb/s.