7.5 COMPARISON OF BIPOLAR AND FET AMPLIFIERS
7.5.1 Optimization of a Bipolar Device for Low Noise
Each of the above equations can be optimized for minimum noise. Consider the bipolar device first, recall that
CTB= Cds+ Cje+ C + gmF; gm = Ic
VT:
The noise-current variance can be written as
hi2ni= 4 kT
RF I2fb+ 4kTrb(2Cds)2I3fb3+ 4 kTgm
2 I2fb
+ 4kT
1 2 + 1
A1
I3fb3(2)2(Cds+ Cje+ C + gmF)2
gm ; (7.177)
whereA1is the voltage gain of the first stage. We can define a capacitance C =4 Cds+ Cje+ C, which is the input capacitance of a bipolar device due to parasitic junctions and stray capacitances. We can separate the total capacitance into the sum of the junctions, the stray capacitance, and the base charge storage capacitancegmF. Rewriting 7.177 usingCgives,
hi2ni= 4kTI2fb
RF + (2 rbCds)2I3fb3 rb + gm
2 I2fb +
1 2 + 1
A1
I3fb3(2)2
"
C2
gm + 2C F + gmF2
#
: (7.179)
We wish to optimize this expression by choosing the transconductance that results in the minimum noise. Rewriting one more time to show explicitly the optimization with
370 Chapter 7
10-1 100 101 102 103 104 105
104 105 106 107 108 109 1010 1011
Spectral densisty of input current noise
pA^2 / Hz
frequency
total
Ib shot
Ic shot
Figure 7.27 Total input referred current noise spectral density showing shot noise contri- butions from the base and collector currents.
respect togm, we get
hi2ni= 4kT
I2fb
RF + rb(2Cds)2I3fb3+
1 + 2 A1
I3fb3(2)2C F
constant + 4kT
gm 2
I2fb +
1 + 2 A1
I3fb3(2)2F2
linear term + 4kT 1
2gm
1 + 2 A1
I3fb3(2)2C2 inverse term (7.181)
This optimization is illustrated graphically in Fig. 7.27. Increasing the bias current (and thusgm) increases the corner frequency where the collector current shot noise begins to increase. However, this also increases the low-frequency base-current shot noise. The optimization procedure adjusts the contribution of each of these terms until the total noise is minimized. At the optimalgm, the linear term will equal the inverse term. This occurs for
gmopt
fb
+ mfb3 fF2
= 1 gmoptmfb3(2C )2; (7.183)
where we have defined
fF 4= 1 2F (7.185)
Low-Noise Preamplifier 371
as the maximumftof the bipolar transistor, and
m =4 I3 I2
1 + 2 A1
: (7.186)
From (7.183) we obtain the transconductance that minimizes the noise as
gmopt= 2C fb
"
1
p1=m + fb2=fF2
#
; (7.188)
which is proportional to the data rate andC. The bias current required to achieve this transconductance is just
ICopt = gmoptVT: (7.190)
At low data-rates, or low,
gmopt = 2C fbpm; (7.192)
whereas for high data ratesgmoptincreases until it reaches the limit
gmopt = 2C fF: (7.194)
We can gain insight into this optimization process if we consider the relative magnitudes of the base charge-storage capacitance compared to the junction and stray capacitance
C. At low data rates, the optimum base-charge storage capacitance is
Cqbopt= gmoptF = C fbpm
fF ; (at low data rates): (7.196)
This base-charge storage capacitance increases with the data-rate until it is equal to the parasitic junction capacitanceCgiving
Cqbopt = gmoptF = C ; (at high data rates): (7.198)
The optimum noise variance can be found by substituting the optimalgm back into
the noise expression. Realizing that at the optimum the linear term is equivalent to the inverse term, the noise is just the constant term plus double the inverse term.
hi2nopti= 4kT
I2fb
RF
+ 4kT2CdsI3fb3 frb
+ 4kT
"
2C
1 + 2 A1
I3
"
fb2
s 1 m + fb2
fF2 + fb3 fF
##
(7.200)
372 Chapter 7
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
2 3 4 5 6 7 8 9 10 11
Input referred rms-noise current vs. bit-rate
Input rms-noise current (uA)
Bit-rate (Gb/s)
Ibias = 0.5mA
1.5mA
2.5mA 3.5mA
4.5mA note: an ideal low-pass noise filter at 1/2 the
bit-rate was used for this simulation.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Input reffered rms-noise-current vs. bias current
Input Stage Bias Current (mA)
Input rms-noise current (uA)
bit-rate = 2 Gb/s 4 Gb/s 5 Gb/s 8 Gb/s 10 Gb/s note: an ideal low-pass noise filter at 1/2 the
bit-rate was used for this simulation.
(a) (b)
Figure 7.28 Optimum noise for a bipolar device: (a) noise vs. bit-rate, (b) noise vs. bias current.
At low data rates, 7.200 gives
hi2nopti4kT
I2fb
RF
+ 4kT
2
4
2C
h1 + A21 iI3fb2
pm
3
5: (7.202)
At high data rates, 7.200 gives
hi2nopti4kT
2I3fb3
Cds
frb + 2 C [1 + 2=A1] fF
: (7.204)
At low data ratescontrols the noise because the base current term is important. At higher data ratesF (or the base-charge-storage capacitance) controls the noise. In each case we increaseIc as much as possible until limits controlled by eitherorF are reached.
The optimum noise as a function of the bit rate is shown in Fig. 7.28(a) for various bias currents. Fig. 7.28(b) plots the optimum noise for various bit rates as a function of bias current. It can be seen that the bias current has a shallow optimum. Moving the bias current slightly away from the optimal value doesn’t degrade the noise appreciably.
This shallow optimum comes about because as the bias current is increased, so also is the base charge storage capacitancegmF. We increase the bias current so as to maximize the transconductance-capacitance ratio (CTB=gm). At low current this ratio is dominated by junctions and strays sinceC is small. As the current is increased further, the ratio becomes dominated by the term (C =gm), which approachesF in
Low-Noise Preamplifier 373
0 1 2 3 4 5 6
2 3 4 5 6 7 8 9 10
Optimum bias current for low-noise for 4 bipolar transistors
Bit-Rate (Gb/s)
Bias Current (mA)
BJT1 HBT5
BJT2 HBT6
0 0.2 0.4 0.6 0.8 1 1.2
1 2 3 4 5 6 7 8 9 10 11
Input rms noise current vs. bit-rate (simulated and calculated)
Input rms noise current (uA)
Bit-rate (Gb/s)
(a) (b)
Figure 7.29 (a) Optimum bias current vs. bit-rate for various transistors. (b) Calculated and simulated rms current noise of HBT5 vs. bit-rate.
the limit. Therefore, transistors with the smallest forward transit times (highestft) will exhibit better noise performance, and they will be able to run at a higher current before the term (gmF) becomes comparable to the parasitic input capacitance. The optimum bias current for various devices is shown in Fig. 7.29(a) as a function of the bit rate. Faster transistors will have lower noise, and will operate at a higher optimal bias current. The rms current noise for the device labeled HBT5 in Fig. 7.29(a) is plotted in Fig. 7.29(b). Both the simulated and calculated results are given. The calculated result (dashed lines) is virtually coincident with the simulated value, showing that the results given thus far are, at least, in agreement with SPICE simulations.