4.6 PARASITIC-DELAY INSENSITIVE CLOCK RECOVERY SCHEMES
4.6.2 Alexander’s Clock Recovery and Data Retiming Circuit
Several clock recovery circuits for moderate bit rates have emerged recently [39, 40, 41, 42, 43, 44, 27], all of which are based on a phase-detector similar in concept to
238 Chapter 4
D Q
D Q Data - in
CENTER
TRANSITION
Data - out Clock - out
VCO
D Q
D Q
F(s)
PHASE / FREQUENCY LOGIC ε
(a)
(c)
(b)
Figure 4.59 Block diagram of Alexander‘s self-adjusting clock recovery and data retiming circuit.
(b) (c) (a)
T
On- Time (b) (c)
(a) T
Early (a) = (b)
(b) (c) (a)
T
Late (b) = (c)
Figure 4.60 Illustration of sampling points (a), (b), and (c) for early, on-time, and late clocks.
circuit described in 1975 by Alexander [38]. This clock recovery circuit is based on a digital approximation to an early-late technique, described in the previous section.
The basic circuit is shown in Fig. 4.59. The phase detector is designed so that during any particular clock interval there are three binary samples of the data signal available:
(a) is the previous data value, (b) is a sample of the data at the transition, and (c) is the current data value. The ordering of these three samples are illustrated in Fig. 4.60 for early, on-time, and late clocks respectively. The retimed data can be taken from either the (a) or (c), and is usually taken from (a) so as to get an additional squaring of the data pulse by passing through two decision circuits. Based on the binary outcome
Clock Recovery 239
Enable Control Frequency
ac bc
0 0 f0
0 1 f0
1 0 f0+f
1 1 f0;f
Table 4.4 Truth-table enumerating control possibilities for clock recovery using a bang- bang oscillator.
of the samples, we can devise a set of rules used to control the phase of the sampling clock6.
Ifa=b6=c, the clock is early)slow down the clock.
Ifa6=b=c, the clock is late)speed up the clock.
Ifa=b=c, no data transition occurred)do nothing.
Ifa=c6=b, shouldn’t happen in phase-lock)possible frequency error.
The digital logic block translates the above rules into signals that control the phase of a local oscillator. When the clock is on-time, the center sample (b) will randomly equal (a) or (c), causing the clock to randomly switch between, speeding up, and slowing down. On average, (b) will equal both (a) and (c) half of the time. It is interesting to note that this system, is an early example of a Fuzzy-Logic control system.
Discrete Frequency Adjustment Circuit Alexander describes two methods for clock recovery using his phase detector. The first assumes that a VCO exists that can operate at three discrete frequencies: f0,f0;f, andf0+f. Such an oscillator is often referred to as a bang-bang oscillator. From the list of control rules, we can see that the truth-table 4.4 provides the necessary control signals for the circuit. A simple circuit to implement this operation is shown in Fig. 4.61. When the enable signal is low, no data transition occurred, and the VCO remains at the center frequency. When a transition does occur, the enable goes high, and the frequency is shifted up or down slightly
6Although Alexander states the early-late conditions correctly in the text, he reverses the order in the itemized list, and in the truth-tables.
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(b)
(c) (a)
VCO Clock
enable control
−/+ ∆ f
Figure 4.61 Block diagram of a bang-bang VCO used for clock recovery.
depending on the polarity of the control signal. When the control signal is high, the clock was late, so the frequency is increased. A high control signal indicates an early clock, and the VCO frequency is reduced. The signalabcould also be used for the control signal, in which case the polarity is opposite of the circuit shown in Fig. 4.61.
The Hewlett-Packard 622-Mb/s Circuit A circuit based on Alexander’s phase detector was used in a 622-Mb/s clock recovery and data retiming IC designed by Lai and Walker of Hewlett Packard [39]. This circuit used a coarse-tune/fine-tune approach. The average of the phase-error signal is used in a narrowband feedback loop to adjust the nominal center frequency of the VCO, and the fine-tuning of the phase is accomplished using the discrete frequency adjustment. The same phase detector was used in a 1.5- Gb/s system designed by Walker et al. [8, 9], which used line-coding to achieve simultaneous frame- and bit-synchronization.
3-Level Phase Error Circuit Alexander also described how his phase detector could be used to produce a 3-level phase error for use in tuning an analog PLL. In this case the desired phase error can be obtained by subtracting the early from the late signal.
The truth-table for this situation is given in table 4.5. A circuit that implements this truth table is shown in Fig. 4.62. A lowpass filter is used to average the phase-error over several cycles. The net dc value will give an indication of the phase error, and this filtered signal is used to adjust the VCO. Alternatively these control signal can be used as the inputs of a charge-pump that converts pulse widths into voltage levels by controlling the charging-time of integration currents. Since the phase is adjusted according to the outputs of decision circuits, the clock is automatically adjusted to the proper phase. However, the sampling of the center point (b) varies randomly, so that in steady-state, the phase-error will have a strong ripple component leading to increased clock-jitter. Since this circuit uses concatenated decision circuits, the maximum data rate will be limited by the decision circuit delay. To insure proper circuit operation this
Clock Recovery 241
Late Early Phase-Error
ab bc
0 0 0
0 1 -1
1 0 1
1 1 0
Table 4.5 Truth-table describing the 3-level output phase-detector.
(b) (c) (a)
To VCO
Early Late
+ -
Figure 4.62 Phase detector for 3-level Alexander circuit.
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D Q1 Data - in
MAIN DECISION
VCO D Q2
F(s) ε
Data - out REFERENCE
DECISION
+ Σ - Phase Error
p1 p2
Data - in
DELAY
D Q
F(s)
ε
Data - out DECISION
+ Σ - Phase Error
T / 2
S R Q S R
Q
CLOCK RECOVERY
PLL or Bandpass Filter
ELECTRONICALLY TUNABLE
DELAY
(a) (b)
Figure 4.63 Block diagram of self-adjusting phase detector and decision circuit: (a) Hogge’s circuit, (b) Whitt’s circuit.
delay must not exceed the bit-interval. However, interleaving can be used to increase the throughput whentd >T.