Tài liệu Design Technologies docx

The MOS Transistorn+ n+ p-substrate Field-Oxyde SiO2 p+ stopper Polysilicon Gate Oxyde Drain Source Gate Bulk Contact CROSS-SECTION of NMOS Transistor... Levitan 1998The Basic Idea… » Vo

Design Technologies

Introduction to VLSI Design Introduction © Steven P Levitan 1998

Views / Abstractions / Hierarchies

D.Gajski, Silicon Compilation, Addison Wesley, 1988

Architectural Logic

Circuit

Physical

device

N-Channel Enhancement

mode MOS FET

– Four Terminal Device - substrate bias

The MOS Transistor

n+

n+

p-substrate

Field-Oxyde (SiO2)

p+ stopper

Polysilicon

Gate Oxyde

Drain Source

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor

MOS transistors Types and Symbols

D

S G

D

S G

G

S

S G

NMOS Enhancement NMOS Depletion

B

Introduction to VLSI Design Introduction © Steven P Levitan 1998

The Basic Idea…

» Voltage on the Gate controls the current

through the source/drain path

» N-Channel - N-Switches are ON when the

Gate is HIGH and OFF when the Gate is LOW

» P-Channel - P-Switches are OFF when the

Gate is HIGH and ON when the Gate is LOW

» (ON == Circuit between Source and Drain)

Transistors as Switches

G

S D

G

S D

Passes “good zeros”

Passes “good ones”

Introduction to VLSI Design Introduction © Steven P Levitan 1998

….The Rest of the Story

» Put them in series - both must be on to

complete the circuit

» Put them in parallel - either can be on to

complete the circuit

» Generate all sorts of Switching Functions

» NOT the same as Boolean Functions Its

RELAY logic - pin ball machines

Series Parallel Structures

N Channel: on=closed when gate is high

1 1

NMOS Transistors in Series/Parallel

NMOS Transistors pass a “strong” 0 but a “weak” 1

Series Parallel Structures(2)

P Channel: on=closed when gate is low

0 0

PMOS Transistors in Series/Parallel

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

Series Parallel Structures (3)

S

S’

Introduction to VLSI Design Introduction © Steven P Levitan 1998

From Switches to Boolean

Functions

Use the Switching Functions to provide paths

to Vdd or GND

» Vdd is the source of all Truth (Vdd = = 1)

» GND is the source of all Falsehood (GND == 0)

0

0 1

1

The Inverter

True to False / False to True Converter

Introduction to VLSI Design Introduction © Steven P Levitan 1998

…That’s it!

This is Non-Trivial: it defines the basis

for the logic abstraction which is

essential for all Boolean functions

» Provide a path to VDD for 1

» Provide a path to GND for 0

» For complex functions - provide complex

paths

Four Views

Logic Transistor Layout Physical

Cross-Section of CMOS

Technology

Magic Layout of Inverter

Introduction to VLSI Design Introduction © Steven P Levitan 1998

Magic “Palette” of Layers

Modern Interconnect

Introduction to VLSI Design Introduction © Steven P Levitan 1998

Chain of Inverters

Feedback loop

Which is which?

Introduction to VLSI Design Introduction © Steven P Levitan 1998

CMOS logic structures – Static (logic) structures

Complementary structures Pass structures

Pseudo-NMOS structures

– Dynamic (logic) structures

precharged latched

combinations

– Memory structures

static quasi-static dynamic

– I/O structures

Complementary Structures

» Big 2 x N transistors for N inputs

– Use the “dual” for N and P chains – Can/should be sized for maximum speed/minimum power-area

» Can use well known circuit minimization

techniques

– Fast – Low static power dissipation

Static CMOS Circuit

At every point in time (except during the switching

transients) each gate output is connected to either

The outputs of the gates assume at all times the value

(ignoring, once again, the transient effects during

switching periods)

This is in contrast to the dynamic circuit class, which

relies on temporary storage of signal values on the

capacitance of high impedance circuit nodes

Complementary CMOS Logic Style Construction (cont.)

Example Gate: NAND

Example Gate: NOR