Tài liệu Circuits & Electronics P23 pptx

6.002 CIRCUITS ANDELECTRONICS Energy, CMOS... MOSFET ON half the time.. So per gate is still... C Change VS depending on need.

6.002 CIRCUITS AND

ELECTRONICS

Energy, CMOS

S

V + –

1

R

1

f

T T

T = 1 + 2 = 1

f CV

P = S2

T1: closed

T2: open

open closed

ON L

S

R R

V P

+

=

2

O

v

S

V

ON

R

L

R

I

v

„

Review

Inverter —

O

v

I

S

V

L

R

ON

R

f

CV R

V

L

2

=

related to switching capacitor

independent of f

MOSFET ON half

the time

STATIC

P PDYNAMIC time constant

" RC

"

2 T

R

>>

>>

Square wave input

f

T = 1

Demo

Review

In standby mode, half

the gates in a chip can

be assumed to be on

So per gate is

still P STATIC

L

2 S

R 2

V

In standby mode,

f Æ 0 ,

so dynamic power is 0

CV R

V

L

2

=

Chip with 106 gates clocking at 100 MHz

V 5 V

, 10 100

f , K 10 R

F, f 1

problem!

1.25KWatts 2.5Watts

not bad +

• independent of f

• also standby power

(assume ½ MOSFETs

ON if f Æ 0)

• must get rid of this!

• α f

• αVS 2

reduce VS

5V Æ 1V 2.5V Æ 150mW

[ 1 25 milliwatts 2 5 watts ]

=

⎥

⎦

⎤

⎢

⎣

⎡

×

×

×

+

×

×

3

2

10 10

2

5 10

P

gates

Review

How to get rid of static power

Intuition:

O

v

S

V

ON

R

L

R

I

i

idea!

O

v

S

V

I

S

V

L

R

O

v

I

v low

off MOSFET

high

New Device PFET

• N-channel MOSFET (NFET)

D

S

G on when v off when vGS ≥ VTN

GS < VTN e.g VTN = 1V

• P-channel MOSFET (PFET)

on when vGS ≤ VTP off when vGS > VTP e.g VTP = -1V

S

D G

ON when less than 4V

5V

Consider this circuit:

S D G

D S G

O

v

I

v

+

–

S

V

PU = pull up

PD = pull down

works like an inverter!

Consider this circuit:

vI = 0V (input low)

V 5

vO

=

V 5

VS =

V 0

vI = + –

p

ON

R

vI = 5V (input high)

V 0

vO

=

V 5

VS =

V

5

vI = + –

n

ON

R

(our previous logic was called “NMOS”)

works like an inverter!

v

I

v

S

V

T

I

v

T

f = 1

From P = CVS2 f

no static power!

Let’s compute PDYNAMIC

S

V + –

p

ON

R

closed for

vI low closed for vI high

For our previous example —

1 , MHz 100

f , V 5 V

F, f 1

C = S = =

“keep all else same”

f CV

P = S 2

6 2

gate per

μwatts 5

2

=

chip gate

10 for μwatts

5

=

P

P

PIII?

~240 watts 1.2 GHz

8x10 6

PIV?

~1875 watts

3 GHz 25x10 6

PII?

~30 watts

600 MHz 2x10 6

PII?

~15 watts

300 MHz 2x10 6

Pentium?

~2.5 watts

100 MHz

10 6

f

Gates

gasp !

and use big heatsink

How to reduce power

A VS 5V Æ 3V Æ 1.8V Æ 1.5V

~PIV Æ 170 watts Æ better, but high

power supply

B Turn off clock when not in use.

C Change VS depending on need.

CMOS Logic

NAND:

Z

A B

0 0 1

0 1 1

1 0 1

1 1 0

S D G

V

V 5

S D G

V

V 5

A

S

V

B

Z

B A

B A

e.g.

In general, if we want to implement F

short when

A = 0 or B = 0,

open otherwise

short when

A · B is true, else open

A

B

short

when F

is true, else open

S

V

Z

short

when F

is true, else open

w