Tài liệu Circuits & Electronics P14 pptx

6.002 CIRCUITS ANDELECTRONICS State and Memory... A 1-bit memory elementMemory Abstraction Remembers input when store goes high.. Like a camera that records input d IN when the user pre

6.002 CIRCUITS AND

ELECTRONICS

State and Memory

+ –C

v

I

1 Recall

Reading: Sections 10.3, 10.5, and 10.7

Review

V

v I = I for t ≥ 0

( ) RC

t

I I

v

−

− +

= v 0 C ( )

( )

C

v 0

I

v

0

t

C

v

0

I

V

( )0

C

v

I

v

I

V

This lecture will dwell on the

memory property of capacitors.

For the RC circuit in the previous slide

Notice that the capacitor voltage for is

0

t ≥

0

t ≥

( ) RC

t

I I

v

−

− +

= v 0 C( )

V C

q =

for linear capacitors,

capacitor voltage V

is also state variable state variable, actually

State : summary of past inputs relevant

to predicting the future

State

( )

t

I C

I

v

−

− +

1

Back to our simple RC circuit

( ) ( )

f

v C = C 0 , I

State

Summarizes the past input relevant

to predicting future behavior

We are often interested in circuit

response for

zero state v C (0) = 0 zero input v I (t) = 0

zero input response or ZIR

( ) RC

t

C

v

−

RC

t

I I

C V V e v

−

−

=

Correspondingly,

zero state response or ZSR

2

3

State

Why memory?

Or, why is combinational logic insufficient?

One application of STATE

DIGITAL MEMORY

Examples

Consider adding 6 numbers on your

calculator

2 + 9 + 6 + 5 + 3 + 8

M+

A 1-bit memory element

Memory Abstraction

Remembers input when store goes high.

Like a camera that records input (d IN) when the

user presses the shutter release button.

The recorded value is visible at d OUT.

IN

d

OUT

d store M

IN

d store

OUT

The 6.004 view

The NEC View

☺

$

¥

A First attempt

Building a memory element …

store

storage node

C

*

Stored value leaks away

store pulse width >> R ON C

Building a memory element …

C R t C

L

e v

−

⋅

= 5

5

ln OH L

V C

R

T = −

2 from

v C

t T

5V

V OH

v C store = 1

C

*

v C store = 0

C

*

R L

Input resistance R IN

B Second attempt buffer

R IN store

buffer

C

*

5

ln OH IN

V C

R

T = −

L

IN R

R >>

Better, but still not perfect

Demo

Building a memory element …

Does this work?

C Third attempt buffer + refresh

store

C

*

store

Building a memory element …

No External value can influence storage node

D Fourth attempt buffer + decoupled

refresh

store

C

*

store

Building a memory element …

A Memory Array

Decoder

Address

IN

d

OUT

d

S M

IN

d

OUT

d

S M

IN

d

OUT

d

S M

IN

d

OUT

d

S M

A

B

C

D

0 0

1 0

0 1

1 1

IN store

OUT

a0a1 2

A

B

C

D

store

4-bit memory

Address

IN OUT

Truth table for decoder

Agarwal’s top 10 list on memory

10 I have no recollection, Senator

9 I forgot the homework was due today

8 Adlibbing ZSR

7 I think, therefore I am

6 I think that was right

5 I forgot the rest …

≡