TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_IT
Trang 1TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ
8
1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
B
7
ECNREV
DATE
D
A
C
THE INFORMATION CONTAINED HEREIN IS THE
2 ALL CAPACITANCE VALUES ARE IN MICROFARADS
5 6
D
B
1 2
APPDCKDESCRIPTION OF REVISION
05/29/2009 48
06/15/2009 46
10/01/2009 45
05/29/2009 43
05/29/2009 42
05/29/2009 41
39 FireWire LLC/PHY (FW643) K19_MLB
06/15/2009 40
08/20/2009 39
37 Ethernet PHY (Caesar II/IV) T27_REF
10/06/2009 37
10/07/2009 36
08/26/2009 35
34 SecureDigital Card Reader T27_REF
06/15/2009 34
33 X16/ALS/CAMERA CONNECTOR K18_COMMS
06/15/2009 33
32 FSB/DDR3/FRAMEBUF Vref Margining K17_REF
06/15/2009 32
MASTER 31
MASTER 30
MASTER 29
06/15/2009 28
06/23/2009 27
06/15/2009 26
25 eXtended Debug Port (XDP) K17_REF
06/15/2009 25
06/15/2009 24
06/15/2009 23
06/15/2009 22
06/15/2009 21
10/07/2009 20
06/15/2009 19
08/24/2009 18
17 PCH SATA/PCIE/CLK/LPC/SPI K17_REF
06/15/2009 17
16 CPU Non-GFX Decoupling (2 of 2) K17_REF
06/15/2009 16
15 CPU Non-GFX Decoupling (1 of 2) K17_REF
06/15/2009 15
06/15/2009 14
06/15/2009 13
06/15/2009 12
06/15/2009 11
06/15/2009 10
06/11/2009 9
MASTER 8
MASTER 7
05/28/2009 5
MASTER 4
06/30/2009 3
06/30/2009 2
06/10/2009 99
90
LCD Backlight Support K19_MLB
05/29/2009 98
89
07/29/2009 97
88
06/15/2009 96
87
1V8 / 1V55 FB Power Supply K18_POWER
06/26/2009 95
86
DisplayPort Connector K17_REF
06/15/2009 94
85
Muxed Graphics Support K17_REF
06/15/2009 93
84
LVDS Display Connector K19_MLB
05/29/2009 90
83
GPU (GT216) CORE SUPPLY K18_POWER
07/14/2009 89
82
NV GT216 VIDEO INTERFACES K17_REF
06/15/2009 88
81
GT216 GPIOS & STRAPS K17_REF
06/15/2009 87
80
NV GT216 GPIO/MIO/MISC K17_REF
06/15/2009 86
79
GDDR3 Frame Buffer B (Top) K17_REF
06/15/2009 85
78
GDDR3 Frame Buffer A (Top) K17_REF
06/15/2009 84
77
NV GT216 FRAME BUFFER I/F K17_REF
06/15/2009 82
76
NV GT216 CORE/FB POWER K17_REF
06/15/2009 81
75
06/15/2009 80
74
06/15/2009 79
73
06/10/2009 78
72
06/29/2009 77
71
CPUVTT (1.05V) Power Supply K18_POWER
07/14/2009 76
70
GFX IMVP VCore Regulator K18_POWER
07/08/2009 75
69
CPU IMVP VCore Regulator K18_POWER
06/29/2009 74
68
07/14/2009 73
67
5V / 3.3V Power Supply K18_POWER
07/13/2009 72
66
PBus Supply & Battery Charger K18_POWER
06/30/2009 70
65
DC-In & Battery Connectors K18_POWER
06/30/2009 69
64
AUDIO: JACK TRANSLATORS K18_AUDIO
07/29/2009 68
63
07/29/2009 67
62
07/29/2009 66
61
AUDIO: HEADPHONE FILTER K18_AUDIO
07/29/2009 65
60
AUDIO: LINE INPUT FILTER K18_AUDIO
07/29/2009 63
59
AUDIO: CODEC/REGULATOR K18_AUDIO
09/21/2009 62
58
06/15/2009 61
57
DEBUG SENSORS AND ADC K18_SENSORS
07/07/2009 60
56
Sudden Motion Sensor (SMS) K19_MLB
05/29/2009 59
55
05/29/2009 58
54
05/29/2009 57
53
05/29/2009 56
52
06/18/2009 55
51
07/02/2009 54
50
Current & Voltage Sensing K18_SENSORS
06/29/2009 53
49
K18 SMBus Connections K18_SENSORS
06/18/2009 52
48
LPC+SPI Debug Connector K17_MLB
06/23/2009 51
Sync
06/29/2009 50
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R PAGE TITLE
J4501
SATAConnODD
P8 40
SATA
P8 40
HDConn
IR Bluetooth
PG 25 U2600
Trang 3II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
PGOOD
VR_ON
DELAY
DELAY RC RC
R7020
LT3470A
SMC
EG_RAIL2_ENEG_RAIL1_EN
F7040
K17 POWER SYSTEM ARCHITECTURE
R6905
(PAGE 63)U6990
U5000
SMC PWRGDNCP303LSN
SMC_ONOFF_LSMC_TPAD_RST_L
PM_PCH_PWRGD
RC
Q7055
SMCALL_SYS_PWRGD
P5VS3_PGOODP1V8S0_PGOODPP3V3_S0_PWRCTL
PP1V05_S0PP1V5_S0
S0PGOOD_PWROK
SLP_S3_L(P93) SLP_S4_L(P94)
SMC_ONOFF_LRSMRST_PWRGD
(PAGE 9~14)
VCCCPUPWRGDSM_DRAMPWROK
(PAGE 17~22)U1800
(P64)
RSMRST_OUT(P15) 99ms DLY IMVP_VR_ON(P16)
U1800
PM_SLP_S4_L PM_SLP_S5_L
RSMRST_IN(P13) PWRGD(P12)
GPU VCOREISL6263C
SMC_GPU_ISENSE
PGOOD EN
VOUT VIN
1.5V
VOUT2
VINPP1V1_S0GPU
A
PPVTT_S0_DDR_LDOPP1V8_S0GPU
(R/H)
(PAGE 85) U9500
Q9806PM_SLP_S5_L
APP001BKLT_EN
(L/H)
VOUT1 EN1
PPVOUT_S0_LCDBKLT
Q7870
PP3V3_S3
VIN EN
OUT PP3V3_S0_GPU
PP3V3_ENETP1V5_EXP_S0_EN
P3V3S3_EN
PP1V8_S0 EN
(PAGE 66)DDRREG_EN
8A FUSE
PBUS SUPPLY/
VOUT VIN
XP2-5
SYNC_DATE=06/30/2009SYNC_MASTER=K17_REF
Power Block Diagram
3 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
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R PAGE TITLE
Trang 5TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
BOM OPTIONSBOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
PART NUMBER ALTERNATE FOR
TABLE_ALT_HEAD
TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM
TABLE_ALT_ITEM TABLE_ALT_ITEM
QTY
QTY
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
1826-4393
1826-4393
152S1102 152S1088 ALL Mag layer alt to Vishay
353S2805 353S2603 ALL Fairchild wafer option
Sanyo alt to Kemet
ALL128S0264 128S0257
128S0303 128S0282
ALL155S0329 MAG LAYERS ALT TO MURATA
157S0058
ALL152S0518
152S0896 MAG LAYERS ALT TO CYNTEC
138S0602 Murata alt to Samsung
333S0533 4 IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_SAMSUNG
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B
J6780 (MIC CONN)
J6950 (BIL CABLE CONN)
J5800 (IPD FLEX CONN)J5650 (LEFT FAN CONN)
J6950 (MAIN BATT CONN)
J6995 (BAT LED CONN)
J5713 (KEY BOARD CONN)
FUNC_TEST
J6781 & J6782 (SPEAKERS CONN)
J5660 (RIGHT FAN CONN)Functional Test Points
I1042 I1043 I1044
I1050 I1051
I1052 I1053
I1054
I1055 I1056
I1057 I1058
I1059
I1060 I1061
I1062 I1063
I1064
I1065 I1066
I1086
I1088 I1089
I1090
I1092 I1093 I1094
I1095 I1096 I1097 I1098
I1099 I1100 I1101
I1102 I1103
I1104 I1105
I1106 I1107
I1108 I1109 I1110 I1111 I1112 I1113 I1114 I1115
I1116 I1117
I1118 I1119 I1120
I1121 I1122
I1123 I1124 I1125
I1126 I1127
I1128 I1129 I1130
I1131 I1132
I1134
I1135 I1136
I1137
I1140
I1141 I1142
I1143
I1145
I1146
I1149 I1150
I1151 I1152
I1156 I1160 I1161 I1273
I1288 I1292
I1297
I1436 I1437 I1438 I1439 I1440 I1441 I1442
I1443 I1444 I1445 I1446 I1447 I1448 I1449 I1450
I1451 I1452
I1453 I1454 I1455
I606 I607
I610
I611 I612
I613
I614 I615 I616 I617 I618 I620 I621 I623 I624 I625
I626 I627
I636 I637 I638 I639 I640
I709 I714
I720 I722
I723 I724
I725 I726 I727
I728 I729
I730
I731 I732
I733 I734
I735
I737
I738 I739
I740 I741 I742 I743 I744 I751 I752
I756 I760
I761 I762 I763 I764 I765
I766 I767
I768 I769
I770
I771 I772
TRUE PP5V_S3
TRUE WS_KBD_ONOFF_L
SYS_LED_ANODE_RTRUE
MAKE_BASE=TRUE
TRUE
TRUE MAKE_BASE=TRUE
TRUENC_PCIE_CLK100M_PE4NNC_PCIE_CLK100M_PE4P
NC_NV_RB_LMAKE_BASE=TRUE
TRUENC_NV_RB_L
TP_NV_WR_RE_L<1 0>
NC_PCIE_PE5_R2D_CPTRUE
MAKE_BASE=TRUE
NC_CLINK_DATANC_CLINK_CLK
NC_CLINK_DATATRUE
NC_CLINK_CLKTRUE
MAKE_BASE=TRUE
TRUENC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_SSD2_R2D_CNNC_SATA_SSD2_R2D_CP
NC_PCI_CLK33M_OUT3MAKE_BASE=TRUE
TRUE
NC_PCH_NV_RCOMPMAKE_BASE=TRUE
TRUE
NC_NV_DQ<15 0>
TRUE MAKE_BASE=TRUE
SMC_TRST_LTRUE
NC_PCI_GNT1_L
WS_KBD12TRUE
WS_KBD11TRUE
TRUE WS_KBD10
NC_TP_CPU_RSVD<2 1>
MAKE_BASE=TRUE TRUE
SMC_TMSTRUE TRUESMC_TDOTRUESMC_TDITRUESMC_TCKSMC_RX_L TRUE
TRUE WS_KBD7
LPC_FRAME_LTRUE
TRUE WS_KBD9
TRUE PP1V5_S3
PP3V3_S3TRUE
TRUE PP3V3_S3
TRUEAP_RESET_CONN_L
FAN_LT_PWMTRUE
SD_CD_LTRUE
PP5V_S3_IR_RTRUE
TRUEPCIE_WAKE_LTRUEAP_CLKREQ_Q_LTRUEPCIE_CLK100M_AP_CONN_P
TRUE WS_KBD16_NUM
WS_KBD21TRUE
TRUE WS_KBD22TRUE WS_KBD23
TRUE WS_KBD2
TRUE WS_KBD4
SMC_RESET_L TRUE
SPI_ALT_CS_LTRUE
WS_KBD15_CAPTRUE
WS_KBD6TRUE
TRUE WS_KBD13
TRUE USB2_LT1_NUSB2_LT1_PTRUE
SPI_ALT_MOSITRUE
BKLT_ENTRUEWS_KBD1
TRUEPP3V42_G3HTRUE
TRUE USB_LT2_P
WS_KBD18TRUE
PCIE_AP_D2R_NTRUE
PCIE_AP_R2D_PTRUE
Z2_DEBUG3TRUE
TRUE PP1V2_ENET
TRUE PPVTTDDR_S3TRUE PPVP_FW
TRUE PPVCORE_GPUTRUE PPDCIN_G3H
TRUE PP3V42_G3HTRUE PP3V3_S5_AVREF_SMCTRUEPP3V3_S5
PP1V05_S0GPUTRUE
PP1V05_S0TRUE
TRUE PP18V5_S3
TP_PCI_C_BE_L<3 0>
TRUE SMC_LID_R
SATA_HDD_D2R_C_PTRUE
SATA_HDD_R2D_PTRUE
NC_PCIE_PE5_D2RPTRUE
TRUE MAKE_BASE=TRUE
NC_PCIE_PE7_D2RNNC_PCIE_PE7_D2RPNC_PCIE_PE6_D2RN
NC_PCIE_PE7_R2D_CPNC_PCIE_PE7_R2D_CN
PP5V_S3_RTUSB_B_FTRUE
PP5V_S0_HDD_FLTTRUE
NC_CRT_IG_DDC_CLK
NC_PCH_LVDS_VBG
TRUE MAKE_BASE=TRUE
NC_CRT_IG_BLUE
Z2_BOOST_ENTRUE
NC_CRT_IG_HSYNCNC_CRT_IG_VSYNC
NC_LVDS_IG_CTRL_DATA
MAKE_BASE=TRUE TRUE WS_KBD5
SATA_ODD_R2D_NTRUE
SATA_HDD_R2D_NTRUE
LED_RETURN_3TRUE
LVDS_DDC_CLKTRUE
TRUE MAKE_BASE=TRUENC_TP_CPU_RSVD<27 26>
TRUE MAKE_BASE=TRUENC_TP_CPU_RSVD<58 45>
TRUE WS_KBD14TRUE USB_LT2_N
TRUEPP18V5_S3
LPC_AD<0 3>
TRUE
TP_ISSP_SDATA_P1_0TRUE
SATA_HDD_D2R_C_NTRUE
SMBUS_SMC_BSA_SDATRUE
PP18V5_DCIN_FUSETRUE
ADAPTER_SENSETRUE
PPVBAT_G3H_CONNTRUE
SMBUS_SMC_A_S3_SDATRUE
PP5V_SW_ODD
PSOC_F_CS_LTRUE
Z2_MISOTRUE
WS_KBD20TRUE
TP_ISSP_SCLK_P1_1TRUE
LPCPLUS_GPIOTRUE
LED_RETURN_5TRUE
WS_KBD3TRUE
LVDS_DDC_DATATRUE
LED_RETURN_2TRUE
TRUE LED_RETURN_4
TRUE LED_RETURN_6
TRUE SMC_ODD_DETECT
SATA_ODD_D2R_C_PTRUE
SATA_ODD_D2R_C_NTRUE
WS_KBD19TRUE
TRUE IR_RX_OUT
WS_LEFT_SHIFT_KBDTRUE
TRUE WS_CONTROL_KBD
LCD_BKLT_PWMTRUE
LVDS_CONN_B_DATA_N<2>
TRUE
PP3V3_SW_LCDTRUE
SMBUS_SMC_BSA_SDATRUE
SPI_ALT_MISOTRUE
PM_SYSRST_L TRUE
PM_CLKRUN_L TRUE
TRUE LPC_SERIRQ
LPC_CLK33M_LPCPLUSTRUE
LPCPLUS_RESET_LTRUE
TRUENC_SMC_BS_ALRT_L
TRUE WS_KBD17
SMC_TX_L TRUESPIROM_USE_MLBTRUE
NC_LVDS_IG_CTRL_CLK
TRUE PPVOUT_S0_LCDBKLT
KBDLED_ANODETRUE
TRUE SMC_KDBLED_PRESENT_L
SMC_BIL_BUTTON_LTRUE
TRUE NC_SMC_FAN_2_TACHTRUE NC_SMC_FAN_2_CTL
NC_FW2_TPBPTRUE
NC_FW2_TPBIASTRUE
NC_FW2_TPAPTRUE
NC_FW0_TPBPTRUE
NC_ESTARLDO_ENTRUE
NC_ALS_GAINTRUE
TRUE NC_FW643_AVREG
TRUE MAKE_BASE=TRUENC_DP_IG_C_HPDTRUE
MAKE_BASE=TRUENC_DP_IG_C_CTRL_DATATRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLKMAKE_BASE=TRUE
TRUENC_DP_IG_C_CTRL_CLK
NC_DP_IG_C_MLP<3 0>
MAKE_BASE=TRUE TRUE
NC_DP_IG_D_HPDTRUE
MAKE_BASE=TRUENC_DP_IG_D_HPD
NC_DP_IG_D_CTRL_DATATRUE
MAKE_BASE=TRUENC_DP_IG_D_CTRL_DATA
NC_DP_IG_D_CTRL_CLKTRUE
MAKE_BASE=TRUENC_DP_IG_D_CTRL_CLK
NC_SDVO_TVCLKINNNC_SDVO_TVCLKINN
MAKE_BASE=TRUE TRUE NC_GPU_GSTATE<1>
NC_GPU_GSTATE<0>
MAKE_BASE=TRUE TRUE NC_GPU_MIOA_D<9 0>TP_GPU_MIOA_D<9 0>
TRUE NC_GPU_MIOA_DEMAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWMTRUE
MAKE_BASE=TRUENC_LVDS_IG_B_CLKPTRUE
MAKE_BASE=TRUETP_LVDS_IG_B_CLKP
NC_LVDS_IG_B_CLKNTRUE
MAKE_BASE=TRUE
NC_PCI_GNT3_LNC_PCI_GNT2_L
TRUENC_PCI_PAR
NC_PCI_PME_LMAKE_BASE=TRUE
TRUENC_PCI_PME_L
NC_NV_CLETRUE
MAKE_BASE=TRUENC_NV_CLE
TRUE NC_NV_WE_CK_L<1 0>
MAKE_BASE=TRUETP_NV_WE_CK_L<1 0>
NC_PCIE_CLK100M_PE6NNC_PCIE_CLK100M_PE5P
MAKE_BASE=TRUENC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_SATA_C_D2RPNC_PSOC_P1_3
NC_SATA_C_R2D_CPNC_SATA_C_R2D_CN
NC_SATA_D_D2RN
TRUE NC_SATA_SSD2_R2D_CPMAKE_BASE=TRUE
MAKE_BASE=TRUENC_SATA_SSD2_R2D_CN
NC_HDA_SDIN3
TRUE
TRUE NC_LVDS_IG_CTRL_CLKMAKE_BASE=TRUE
MAKE_BASE=TRUENC_CRT_IG_DDC_CLKTRUE
NC_CRT_IG_GREENTRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE TRUE NC_TP_CPU_RSVD<24 15>
NC_TP_CPU_RSVD<43 32>
MAKE_BASE=TRUE TRUE
MAKE_BASE=TRUE TRUE NC_TP_CPU_RSVD<65 62>
TRUE MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7P
NC_DP_IG_D_AUXN
NC_SDVO_STALLN
NC_PCH_NC1NC_PCH_NC2
NC_PCH_NC3NC_PCH_NC4NC_PCH_NC5NC_PCH_TP19NC_PCH_TP18
TP_DP_IG_C_MLP<3 0>
NC_DP_IG_C_HPD
NC_SMC_FAN_3_CTLTRUE
TRUE NC_SMC_FAN_3_TACH
TRUE MAKE_BASE=TRUE
TRUEPCH_VSS_NCTF<12>
TRUE
TRUE PCH_VSS_NCTF<15>TRUE PCH_VSS_NCTF<17>TRUE PCH_VSS_NCTF<19>TRUE PCH_VSS_NCTF<19>TRUE PCH_VSS_NCTF<21>TRUE PCH_VSS_NCTF<25>TRUE PCH_VSS_NCTF<27>TRUE PCH_VSS_NCTF<29>
NC_PCH_TP1
NC_PCH_TP4NC_PCH_TP5NC_PCH_TP6
MAKE_BASE=TRUE TRUE
NC_PCIE_CLK100M_PE6NMAKE_BASE=TRUE
TRUE
NC_PSOC_P1_3MAKE_BASE=TRUE
TRUE MAKE_BASE=TRUE
TRUENC_SATA_SSD2_D2RNNC_SATA_D_R2D_CPTRUEZ2_RESET
TRUE LVDS_CONN_A_DATA_P<1>
TRUE LVDS_CONN_A_DATA_N<0>
TRUESMBUS_SMC_A_S3_SDATRUESMBUS_SMC_A_S3_SCLTRUEUSB_CAMERA_CONN_PTRUEUSB_CAMERA_CONN_NTRUECONN_USB2_BT_PCONN_USB2_BT_NTRUE
PP5V_S3_RTUSB_A_FTRUE
PP3V3_WLANTRUE
SYS_LED_ANODETRUE
TRUE PPBUS_G3H
TRUEZ2_CS_L
TRUE PP3V3_FW_FWPHY
TRUE PPVCORE_S0_GFXTRUE PPVCORE_S0_CPU
TRUE PP3V3_S0TRUE PP3V3_ENETTRUE PP1V2_S0
PM_SLP_S3_LTRUE
TRUE PP1V05_S5
MAKE_BASE=TRUE
NC_PCIE_PE5_D2RNTRUE
SMBUS_SMC_BSA_SCLTRUE
SMBUS_SMC_BSA_SCLTRUE
LVDS_CONN_A_CLK_F_PTRUE
TRUE SPKRCONN_S_OUT_P
TRUE SPKRCONN_R_OUT_P
TRUE SPKRCONN_L_OUT_P
SPKRCONN_R_OUT_NTRUE
SMC_MD1 TRUE TRUE SMC_NMI SMC_ONOFF_L TRUE
TRUE PP0V75_S0_DDRVTTTRUEPCIE_AP_R2D_N
TRUE PP5V_S0
PP5V_S0TRUE
NC_SATA_C_D2RN
PP5V_S3_ALSCAMERA_FTRUE
TRUESD_CMDTRUESD_CLK
TRUESD_WP
Z2_CLKINTRUE
Z2_SCLKTRUE TRUEZ2_KEY_ACT_L
TRUEPICKB_LTRUEPSOC_MISOPSOC_MOSITRUE
GNDTRUE
GNDTRUE
GNDTRUE
GNDTRUE
GNDTRUE
GNDTRUE
Trang 7II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
Chipset "VCore" Rails
Power Aliases
SYNC_DATE=MASTERSYNC_MASTER=MASTER
PP3V3_S5
MAKE_BASE=TRUE VOLTAGE=3.3V
PP3V3_S3
PP3V3_S3PP3V3_S3
PP3V3_S3
PP3V3_S5
PP3V3_S5PP3V3_S5
PP3V3_S5
PP3V3_S5
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
PP1V5_S3RS0MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V
MAKE_BASE=TRUE VOLTAGE=18.5V
PPDCIN_G3HMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
PP1V2_ENET
PP1V2_ENETMIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM
PP1V05_S0
PP1V05_S0
MAKE_BASE=TRUE VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MMPP1V05_S0
MAKE_BASE=TRUE
PP5V_S3MIN_NECK_WIDTH=0.2 mm
PP3V3_ENETMIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE VOLTAGE=1.0V MIN_NECK_WIDTH=0.2 MMPP1V0_FW_FWPHY
PPVP_FW
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM VOLTAGE=12.8V
PP3V3_S0GPU
VOLTAGE=3.3V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.8V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MMPP1V8_GPUIFPX
VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MMPP1V8R1V55_S0GPU_ISNS
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8VPP1V8R1V55_S0GPU_ISNS_R
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUEPP1V05_S0GPU
VOLTAGE=1.05V
PPVCORE_S0_GFX
VOLTAGE=1.05V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.25V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MMPPVCORE_S0_CPU_VCAP0
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE VOLTAGE=1.25VPPVCORE_S0_CPU_VCAP1
PPVCORE_S0_CPU_VCAP2
VOLTAGE=1.25V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
PPVTTDDR_S3
VOLTAGE=0.75V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.25V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUEPPVCORE_GPU
VOLTAGE=1.0V
MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.2V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.09 MMPP1V2_S0
PP3V3_FW_FWPHYMIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V MAKE_BASE=TRUE
PP0V75_S0_DDRVTT
VOLTAGE=0.75V MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE MIN_LINE_WIDTH=2 mm
PP1V8_S0PP1V8_S0PP1V8_S0
PP1V8_S0PP1V8_S0
PP1V8_S0PP1V8_S0
PP1V5_S3RS0
PP1V5_S3RS0
PP1V5_S3RS0PP3V42_G3H
PP1V0_FW_FWPHY
PP1V0_FW_FWPHY
PP3V3_S0GPUPP3V3_S0GPUPP3V3_S0GPUPP3V3_S0GPUPP3V3_S0GPUPP3V3_S0GPU
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8R1V55_S0GPU_ISNSPP1V8R1V55_S0GPU_ISNSPP1V8R1V55_S0GPU_ISNSPP1V8R1V55_S0GPU_ISNS
PP1V8R1V55_S0GPU_ISNS
PP1V8R1V55_S0GPU_ISNS_RPP1V8R1V55_S0GPU_ISNS_R
PP1V05_S0GPUPP1V05_S0GPUPP1V05_S0GPUPP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PPVCORE_GPUPPVCORE_GPU
PPVCORE_S0_CPU
PPVCORE_S0_GFXPPVCORE_S0_GFX
PP0V75_S0_DDRVTT
PP5V_S0PP5V_S0PP5V_S0
PP5V_S0
PP5V_S0PP5V_S0PP5V_S0PP5V_S0PP5V_S0
PPVTTDDR_S3
PP0V75_S0_DDRVTT
PP1V05_S0PP1V05_S0
PP1V05_S0PP1V05_S0
PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0
PPBUS_CPU_IMVP_ISNS
PP5V_S3
PP5V_S3PP5V_S3PP5V_S3PP5V_S3PP5V_S3PP5V_S3
PP3V3_S5
PP3V3_S5
PP1V8_S0
PP5V_S0PP5V_S0
PP5V_S3PP5V_S3
PP3V3_S0
PP5V_S5
PP5V_S3
PP5V_S3PP5V_S3
VOLTAGE=5VPP5V_S0
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 mm
PP5V_S0PP5V_S0
PP3V42_G3H
PP3V3_S0PP3V42_G3H
PP5V_S3
MAKE_BASE=TRUE VOLTAGE=5VPP5V_S5MIN_NECK_WIDTH=0.2 MM
PPBUS_G3H
PPBUS_G3HPPBUS_G3H
PP3V42_G3HPP3V42_G3H
PP1V05_S0
PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S5
PP3V3_S3
PP3V3_S3
PP1V05_S5
PP0V75_S0_DDRVTTPP0V75_S0_DDRVTT
PP1V05_S0PP1V05_S0
PP3V42_G3H
PP3V42_G3H
VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MMPP1V05_S5
MAKE_BASE=TRUEPP1V05_S5
PP3V3_S0
PP3V42_G3HPP3V42_G3HPP3V42_G3H
MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V MAKE_BASE=TRUE
PP3V42_G3HMIN_NECK_WIDTH=0.2 MMPPDCIN_G3H
PPBUS_CPU_IMVP_ISNSVOLTAGE=12.8V
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 mm
PP3V3_S3
PP3V3_S5PPBUS_G3H
PP3V3_S0
PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3
PP1V5_S3RS0
PP3V3_S5PP3V3_S5PPBUS_G3H
MAKE_BASE=TRUE VOLTAGE=1.5V
PP1V5_S3MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm
PP3V3_S0
PPBUS_G3HMIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE VOLTAGE=12.8V MIN_LINE_WIDTH=0.6 mm
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0PP3V3_S0
MAKE_BASE=TRUE
PP3V3_S0MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V
PP3V3_S0PP3V3_S0
Trang 8D
R PAGE TITLE
Tall EMI pogo pins
Short (IO Row) EMI pogo pins
Left Speaker Holes
Keyboard / IPD Conn Protect
GMUX ALIASES
402 MF-LF10
R0900
10
MF-LF 402
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0901
1
SM1.4DIA-SHORT-EMI-MLB-M97-M98SH0912
1
SM1.4DIA-SHORT-EMI-MLB-M97-M98SH0910
GND_CHASSIS_AUDIO_JACK
GNDGNDGNDGNDGND
FW_PLUG_DET_LMAKE_BASE=TRUE MAKE_BASE=TRUEFW643_WAKE_L
MAKE_BASE=TRUEPEG_CLKREQ_L
MAKE_BASE=TRUELVDS_IG_BKL_ON
MAKE_BASE=TRUEPEG_R2D_C_N<15 0>
PEG_R2D_C_P<15 0>
MAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_D2R_P<15 0>
MAKE_BASE=TRUEPEG_D2R_N<15 0>
GFX_VID<0 6>
MAKE_BASE=TRUEMEMVTT_ENMAKE_BASE=TRUE
MAKE_BASE=TRUETP_ISSP_SDATA_P1_0
TP_ISSP_SCLK_P1_1MAKE_BASE=TRUE
NO_TEST=TRUE MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARD_P
NC_PCIE_CLK100M_EXCARD_N
NO_TEST=TRUE MAKE_BASE=TRUE
NO_TEST=TRUENC_PCIE_EXCARD_R2D_C_NMAKE_BASE=TRUE
DP_IG_ML_P<3 0>
MAKE_BASE=TRUE
PM_ENET_ENMAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKNMAKE_BASE=TRUE
MAKE_BASE=TRUENC_LVDS_IG_A_DATAN<3>
NO_TEST=TRUENC_LVDS_IG_B_DATAP<3>
NO_TEST=TRUE MAKE_BASE=TRUE
TP_LVDS_IG_BKL_PWMMAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<3>
NO_TEST=TRUE MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3>
NO_TEST=TRUE MAKE_BASE=TRUE
GPU_FB_A_VREF_DIVMAKE_BASE=TRUE
GPU_FB_B_VREF_DIVMAKE_BASE=TRUE
MAKE_BASE=TRUETP_CPU_VTT_SELECT
MAKE_BASE=TRUELCD_BKLT_EN
MAKE_BASE=TRUEEG_RESET_L
NC_PCIE_EXCARD_R2D_C_P
NO_TEST=TRUE MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_N
NO_TEST=TRUE MAKE_BASE=TRUE
NO_TEST=TRUE MAKE_BASE=TRUE
NC_SATA_EXTA_R2D_C_P
MAKE_BASE=TRUETP_SMC_EXCARD_PWR_EN
NO_TEST=TRUE MAKE_BASE=TRUE
NC_SATA_EXTA_D2R_N
NO_TEST=TRUENC_PCIE_EXCARD_D2R_PMAKE_BASE=TRUE
MAKE_BASE=TRUEDP_IG_AUX_CH_N
DP_IG_DDC_CLKMAKE_BASE=TRUE
NC_SATA_EXTA_R2D_C_NFW643_WAKE_L
NC_LVDS_IG_B_DATAP<3>
NC_LVDS_IG_B_DATAN<3>
DP_IG_AUX_CH_PDP_IG_B_ML_N<3 0>
DP_IG_B_ML_P<3 0>
LVDS_IG_BKL_ON
TP_SMC_EXCARD_PWR_EN
NC_PCIE_EXCARD_D2R_PNC_PCIE_EXCARD_R2D_C_NNC_PCIE_EXCARD_R2D_C_PNC_PCIE_CLK100M_EXCARD_N
FW_PLUG_DET_L
NC_PCIE_EXCARD_D2R_N
DP_IG_DDC_CLK
GNDGNDGND
GND
NC_SATA_EXTA_D2R_P
NO_TEST=TRUE MAKE_BASE=TRUE
NC_SATA_EXTA_R2D_C_N
TP_ISSP_SDATA_P1_0
DP_IG_AUX_CH_N
DP_IG_AUX_CH_PMAKE_BASE=TRUEEG_RESET_L
GND
PEX_CLKREQ_LMAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_LVDS_IG_BKL_PWMTP_LVDS_IG_B_CLKP
NC_LVDS_IG_A_DATAP<3>
NO_TEST=TRUE
NC_USB_HUB2_OCS3MAKE_BASE=TRUE
NC_USB_HUB1_OCS4NC_USB_HUB2_OCS3
USB_SDCARD_NUSB_SDCARD_PUSB_SDCARD_N
PP3V3_S3
USB_EXTC_NUSB_EXTC_PNC_SATA_EXTA_R2D_C_P
NC_SATA_EXTA_D2R_PNC_SATA_EXTA_D2R_N
VOLTAGE=0V MIN_LINE_WIDTH=0.6 mmGND
Trang 9IN IN IN IN
IN IN IN
OUT
OUT OUT OUT OUT OUT OUT OUT
IN IN IN IN IN
IN
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
IN
IN IN IN IN
IN IN IN IN IN IN
IN IN IN IN IN
OUT
OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT
OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT
OUT
IN
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
PEG_RX3 PEG_RX2 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX11 PEG_RX10
PEG_RX13 PEG_RX12
PEG_RX15 PEG_RX14
PEG_TX5 PEG_TX4 PEG_TX6
PEG_TX8 PEG_TX7 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
DMI_RX2
DMI_RX0 DMI_RX1
DMI_RX3 DMI_TX0*
DMI_TX1*
DMI_TX3*
DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3
FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 FDI_FSYNC0 FDI_FSYNC1
FDI_LSYNC0 FDI_INT
FDI_LSYNC1
PEG_ICOMPI PEG_ICOMPO PEG_RBIAS PEG_RCOMPO DMI_RX3*
RSVD33 RSVD32
RSVD_NCTF5 RSVD_NCTF6 RSVD_NCTF8 RSVD_NCTF7 RSVD27
RSVD24 RSVD26 RSVD23 RSVD22 RSVD21 RSVD20 RSVD19 RSVD18 RSVD17 RSVD16 RSVD15 RSVD_TP0 CFG17 CFG16 CFG15 CFG14 CFG13
CFG11 CFG12 CFG10 CFG9 CFG8 CFG7 CFG6 CFG5
CFG3 CFG4 CFG2 CFG1 CFG0
DC_TEST_A5
DC_TEST_A69 DC_TEST_A68 DC_TEST_A71 DC_TEST_C3 DC_TEST_C69 DC_TEST_C71 DC_TEST_E1 DC_TEST_E71 DC_TEST_BR1 DC_TEST_BR71
DC_TEST_BT3 DC_TEST_BT1 DC_TEST_BT69
DC_TEST_BV1 DC_TEST_BT71 DC_TEST_BV3
DC_TEST_BV68 DC_TEST_BV5
DC_TEST_BV71 DC_TEST_BV69
RSVD64 RSVD65
RSVD62 RSVD63 RSVD_TP1 RSVD_TP2
RSVD57 RSVD58 RSVD56
RSVD54 RSVD55
RSVD52 RSVD53 RSVD51 RSVD50 RSVD49 RSVD48
RSVD46 RSVD47 RSVD45 RSVD_NCTF1 RSVD_NCTF2
RSVD39 RSVD_NCTF3 RSVD38 RSVD34
RSVD_NCTF4
RSVD35 (SYM 5 OF 11)
BI BI
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic WF: RSVD nets with arrows have offpage marks on CRB schematic.
CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed
and level-shifted forNOTE: HPD must be inverted
(Auburndale only):
CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port EnabledCFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled
(IPU)(IPU)
(IPU)(IPU)
(IPU)
(IPU)
(IPU)
(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)
(IPU)(IPU)
R10121
2 1/16W 1%
49.9
402 MF-LF
J6 J8
K9 K8
J2 J4
G17 H17
M15 K15
G13 J13
J11 F10
AC7 AC9 AB5 AA1 AB2
K1 L2
N5 N7
N2 M4
R2 P1
N9 N10
R8 R7
U6 U7
W10 W8
B12 A13 B11 D12
F40 G40
J38 G38
A24 B23
B21 D22
B19 A20
B18 D19
B16 A17
D15
B14
G34 H34
M34 P34
J28 G28
G25 H25
K24 H24
B28 D29
A27 B26
B25 D26
L40 N40
N38 L38
D33 B32
N28 L28
M25 N26
N24 M24
F21 G21
L20
J20
N32 M32
B39 D40
B37 A38
H32 G32
A34 B33
D36 B35
J30 L30
B30 A31
AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7
AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2
A5 A68 A69 A71
BR1 BR71 BT1 BT3 BT69 BT71 BV1 BV3 BV5 BV68 BV69 BV71
C3 C69 C71 E1 E71
T4 T2 U1 V2 AV71 AW70 AY69 BB69 D8 B7 A10 B9
W66 W64 AC69 AC71 AA71 AA69 R66 R64
AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67
AV4 AU2 BE69 BE71
BV8 BV6
BT5 BR5
F1 E3
C5 A6
AU1
AN7 AP2
51 99
51 99
SYNC_DATE=06/15/2009SYNC_MASTER=K17_REF
TP_CPU_TEST_C3
TP_CPU_TEST_A5TP_CPU_TEST_A68
CPU_TEST_C71_A71CPU_TEST_C69_A69
FDI_LSYNC<1>
FDI_LSYNC<0>
FDI_INTFDI_FSYNC<1>
CPU_CFG<11>
CPU_CFG<10>
CPU_TEST_BV1_BT1CPU_TEST_BT71_BT69CPU_TEST_BV3_BT3TP_CPU_TEST_BV5
TP_CPU_RSVD<17>
TP_CPU_RSVD<16>
TP_CPU_TEST_BV68CPU_TEST_BV71_BV69
CPU_THERMD_PCPU_THERMD_N
Trang 10IN IN
IN
IN OUT
IN IN
IN IN
OUT IN OUT
OUT OUT IN
OUT OUT OUT IN
OUT OUT OUT OUT
IN
IN
BCLK_ITP BCLK_ITP*
COMP0
PROC_DETECT
PROCHOT*
PECI CATERR*
RSTIN*
TAPPWRGOOD VTTPWRGOOD
VCCPWRGOOD_0
SM_DRAMPWROK
VCCPWRGOOD_1 PM_SYNC RESET_OBS*
TDI_M TDO TDI
BCLK*
BCLK
TRST*
TMS TCK
PM_EXT_TS0*
SM_RCOMP1 SM_RCOMP0
PEG_CLK*
DPLL_REF_SSCLK DPLL_REF_SSCLK*
REVISION
D
R PAGE TITLE
B
(IPU)
(IPU)
(IPU)(IPU)
(IPU)(IPU)
(IPU)(IPU)
(IPD)
(IPD)
(IPD)
(IPU)(IPU)
(IPU)(IPU)
68
R11021
2 5%
68
MF-LF 402
R11011
2 MF-LF
402 1%
MF-LF 402 1%
R11621
2 1%
MF-LF 402
R1161
1
2
MF-LF 5%
J69 J67 J62 K65 K62 J64 K69 M69
N61
AE66 AD69 AC70 AD71
W71
Y2 W4
N19
L21 J21
AV66 AV64
M17
U71 U69
M71
N67
N70
G3 AM5
BJ12 BV33 BP39 BV40
Y70
T67
T69
P71 T71
T70
N17
N65 P69
Y67 AM7
CPU_COMP3CPU_COMP2
XDP_DBRESET_LJTAG_CPU_TDO
XDP_CPUPWRGD
PM_SYNCFSB_CPURST_L
CPU_COMP0
CPU_PROCHOT_LCPU_PECI
PM_THRMTRIP_LCPU_CATERR_L
CPU_PWRGD
CPUVTTS0_PGOOD
CPU_SM_RCOMP2CPU_SM_RCOMP1
PM_EXT_TS_L<1>
GFX_CLK120M_DPLLSS_PFSB_CLK133M_ITP_N
FSB_CLK133M_CPU_NFSB_CLK133M_ITP_P
PCIE_CLK100M_CPU_P
XDP_PRDY_LXDP_PREQ_LCPU_COMP1
Trang 11BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI
BI BI BI BI BI BI
BI BI
BI BI BI BI BI BI
BI BI
BI BI BI BI BI BI
BI BI
BI BI BI BI BI BI
BI BI
BI BI BI BI BI BI
BI BI
BI BI BI BI BI BI
BI BI
OUT
OUT OUT
OUT OUT
OUT
BI BI
BI
BI BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT OUT
OUT
OUT OUT
OUT OUT OUT
OUT OUT OUT
OUT OUT
OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
BI BI BI BI BI
BI BI
BI
BI
BI BI
BI
BI BI
BI BI
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
SA_RAS*
SA_WE*
SA_CAS*
SA_BS2 SA_BS1 SA_BS0
SA_DQ62 SA_DQ63
SA_DQ60 SA_DQ61 SA_DQ59 SA_DQ58 SA_DQ57
SA_DQ54
SA_DQ56 SA_DQ55 SA_DQ53 SA_DQ52 SA_DQ51 SA_DQ50 SA_DQ49 SA_DQ48 SA_DQ47 SA_DQ46
SA_DQ44 SA_DQ45
SA_DQ41 SA_DQ42 SA_DQ43
SA_DQ40 SA_DQ39 SA_DQ37 SA_DQ36 SA_DQ38
SA_DQ35 SA_DQ34 SA_DQ32 SA_DQ31
SA_DQ33
SA_DQ30 SA_DQ29 SA_DQ28 SA_DQ27 SA_DQ26
SA_DQ24 SA_DQ25 SA_DQ23 SA_DQ22 SA_DQ21
SA_DQ19 SA_DQ20 SA_DQ18 SA_DQ17 SA_DQ16
SA_DQ13 SA_DQ15 SA_DQ14 SA_DQ12 SA_DQ11 SA_DQ10 SA_DQ9 SA_DQ8 SA_DQ7
SA_DQ5 SA_DQ6
SA_DQ3 SA_DQ4
SA_DQ1 SA_DQ2 SA_DQ0
SA_MA15 SA_MA14 SA_MA13 SA_MA12 SA_MA11 SA_MA10 SA_MA9
SA_MA7 SA_MA8 SA_MA6 SA_MA5 SA_MA4 SA_MA3 SA_MA2 SA_MA1 SA_MA0 SA_DQS7 SA_DQS6
SA_DQS4 SA_DQS5 SA_DQS3
SA_DQS1 SA_DQS2 SA_DQS0 SA_DQS7*
SB_DQ4
SB_CK1 SB_DQ5
SB_BS0 SB_BS1 SB_BS2
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
BK43
BM34 BP35
BK36 BH36 BF20
BK24 BH40 BJ47
BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59
AT8 AT6
BK5 BH13 BF9 BF6 BK7 BN8 BN11 BN9 BG17 BK15 BB5
BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21 BB9
BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47 AV7
BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57 AV6
BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66 BE6
BJ66 BF65 AY64 BC70
BE8 BF11 BE11
AY7 AY5
BJ5 BJ7
BL13 BN13
BN21 BL21
BK44 BH44
BH51 BK51
BM60 BP58
BE64 BE62
BT36 BP33
BH34 BH30 BJ28 BF40 BN28 BN25
BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28
BF43 BL47
BL38 BF38
BU46
BU33 BV34
BV38 BU39 BT26
BT24 BP46 BT43
BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67
BA2 AW2
BR6 BR8 BJ4 BK2 BU9 BV10 BR10 BT12 BT15 BV15 BD1
BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19 BE4
BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54 AY1
BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60 BC2
BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67 BF2
BK70 BK67 BD71 BD69
BH2 BG4 BG1
BD4 BE2
BN4 BM3
BV13 BU12
BT17 BT19
BT50 BT52
BU56 BV55
BV62 BU63
BJ69 BG69
BT34 BP30
BU42 BU26 BT29 BT45 BV26 BU23
BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27
BV45 BU49
BT40 BT41
Trang 12OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT
OUT OUT
IN
OUT OUT
VCAP0_15 VCAP0_17
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5
VCC_7 VCC_6
VCC_9 VCC_10
VCC_12 VCC_11
VCC_14 VCC_13
VCC_15 VCC_17 VCC_16
VCC_18 VCC_19 VCC_20 VCC_21 VCC_22
VCC_25 VCC_24 VCC_23
VCC_26 VCC_27
VCC_29 VCC_30 VCC_28
VCC_32 VCC_31
VCC_34 VCC_33
VCC_35 VCC_37 VCC_36
VCC_38 VCC_40 VCC_39
VCC_42 VCC_41
VCC_43 VCC_44 VCC_45 VCC_46 VCC_47
VCC_50 VCC_49
VCC_51 VCC_52 VCC_53
VCC_55 VCC_54 VCC_56
VCC_58 VCC_57
VCC_60 VCC_59
VCC_62 VCC_61 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78
VCC_81
VCC_79 VCC_80
VCC_83 VCC_82
VCC_84 VCC_85 VCC_86 VCC_87 VCC_89 VCC_88
VCAP0_1 VCAP0_2
VCAP0_4 VCAP0_3 VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9
VCAP0_12
VCAP0_10 VCAP0_11
VCAP0_14
VCAP0_16
VCAP0_19 VCAP0_18 VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27
VCAP1_2 VCAP1_1
VCAP1_5
VCAP1_3 VCAP1_4
VCAP1_7 VCAP1_6 VCAP1_8
VCAP1_10 VCAP1_9
VCAP1_13
VCAP1_11 VCAP1_12
VCAP1_15 VCAP1_14
VCAP1_18 VCAP1_17 VCAP1_16
VCAP1_20 VCAP1_19
VCAP1_23
VCAP1_21 VCAP1_22 VCAP1_24 VCAP1_25 VCAP1_27 VCAP1_26
VID2 VID3 VID4 PSI*
VTT0_9
VTT0_22
VTT0_24 VTT0_23
VTT0_26 VTT0_25
VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_36 VTT0_35
VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59
VTT0_62
VTT0_60 VTT0_61
VTT0_63 VTT0_64 VTT0_65
VTT0_67 VTT0_66 VTT0_68
VTT0_70 VTT0_69
VTT0_72 VTT0_71
VTT0_73
VTT0_4
VTT0_6 VTT0_5 VTT0_7 VTT0_8 VTT0_10 VTT0_11 VTT0_13 VTT0_12
VTT0_16 VTT0_15 VTT0_14
VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21
VID5 VID6 VTT_SELECT1 PROC_DPRSLPVR
VTT0_1 VTT0_2 VTT0_3 VID1
VID0
VCCPLL1 VCCPLL2
VCCPLL4 VCCPLL3
VCCPLL5
VDDQ_CK1 VDDQ_CK2
B
NOTE: VCAP1 is sourced by CPU
but provide bypass caps on PCB
Clarksfield: 1.1V(Controlled by VTT_SELECT pin)Arrandale: 1.05V
but provide bypass caps on PCB
Do not connect to power supply,
Do not connect to power supply,
NOTE: VCAP0 is sourced by CPU
1001%
MF-LF 402
1001%
1/16W
R13001
2
PLACE_NEAR=U1000.N13:25.4MM 1/16W
10
MF-LF 402 1%
1/16W10
AN53 AN50 AL57 AL53 AL50 AK57 AK53 AK50
BD48 BB55 BB51 BB48 AY57 AY53 AY50
BD44
AW46 AW42 AW39 AU44 AU41 AU37 AR44 AR41 AR37 AN46 BD41
AN42 AN39 AL46 AL42 AL39 AK46 AK42 AK39
BD37 BB44 BB41 BB37 AY46 AY42 AY39
AF57
AF41 AD55 AD51 AD48 AD44 AD41 AB55 AB51 AB48 AB44 AF55
AB41 AA55 AA51 AA48 AA44 AA41 W55 W51 W48 W44 AF53
W41 U55 U51 U48 U44 U41 R55 R51 R48 R44 AF51
R41 P60 N55 N51 N48 N44 N42 M60 M51 M44 AF50
L55 K60 K51 K44 J55 H60 H51 H44 G60 G55 AF48
G51 G44 F55 E60 E57 E53 E50 E46 E42 D59 AF46
D57 D55 D54 D52 D50 D48 D47 D45 D43 B60 AF44
B56 B53 B49 B46 B42 A57 A54 A50 A47 A43
F64
W39 W37 U37 R39 R37
BB14 BB12
A61 D61 D62 A62 B63 D64 D66
F63
R12
BF60
AW33 AW14 AW12 AU60 AU59 AU12 AR60 AR59 AR12 AN60 BF59
AN59 AN35 AN33 AN17 AN15 AN14 AN12 AM10 AL60 AL59 BD60
AL17 AL15 AL14 AL12 AK35 AK33 AF39 AF37 AF35 AF33 BD59
AF32 AF30 AD39 AD37 AD35 AD33 AD32 AD30 W35 W33 BB60
W32 W30 W28 W26 W24 W23 U35 U33 U32 U30 BB59
U28 U26 U24 U23 R35 R33 R32 R30 R28 R26 AY60
R24 R23 AY10 AN9
AW60 AW35 AN1
N13
SYNC_DATE=06/15/2009SYNC_MASTER=K17_REF
PP1V05_S0
PP1V05_S0
CPU_VTTSENSE_PCPU_VTTSENSE_NPPVCORE_S0_CPU_VCAP0
PP1V8_S0CPU_VCCSENSE_N
PPVCORE_S0_CPUPPVCORE_S0_CPU
PPVCORE_S0_CPU_VCAP1
CPU_VCCSENSE_P
PP1V5_S3_CPU_VCCDDR_CLK
MIN_NECK_WIDTH=0.2mmVOLTAGE=1.5V
Trang 13VTT1_7
VTT1_9 VTT1_10 VTT1_8 VTT1_5
VAXG3 VAXG2 VAXG1
VSSAXG_SENSE VAXG_SENSE
VCAP2_19
VCAP2_17 VCAP2_18 VCAP2_16
VCAP2_14 VCAP2_15
VCAP2_12 VCAP2_13 VCAP2_11 VCAP2_10 VCAP2_9 VCAP2_8
VCAP2_6 VCAP2_7 VCAP2_5 VCAP2_4 VCAP2_3
VCAP2_1 VCAP2_2 VTT1_11
VTT1_6 VTT1_4 VTT1_3 VTT1_2 VTT1_1
VAXG37 VAXG36
VAXG33 VAXG34 VAXG32 VAXG31 VAXG30
VAXG27 VAXG29 VAXG28
VAXG25 VAXG26
VAXG23 VAXG24 VAXG22
VAXG20 VAXG21 VAXG19
VAXG17 VAXG18
VAXG14
VAXG16 VAXG15 VAXG13 VAXG12 VAXG11 VAXG10 VAXG9 VAXG8 VAXG7 VAXG6 VAXG5 VAXG4
VTT1_21 VTT1_20
VTT1_18 VTT1_19 VTT1_17 VTT1_16 VTT1_15 VTT1_14 VTT1_13 VTT1_12 VTT0_DDR9 VTT0_DDR8 VTT0_DDR7 VTT0_DDR6 VTT0_DDR5 VTT0_DDR4 VTT0_DDR3 VTT0_DDR2 VTT0_DDR1 VTT0_DDR
VDDQ36 VDDQ35 VDDQ34 VDDQ33
VDDQ31 VDDQ32 VDDQ30 VDDQ29 VDDQ28 VDDQ27 VDDQ26
VDDQ24 VDDQ25 VDDQ23
VDDQ21 VDDQ22 VDDQ20 VDDQ19 VDDQ18 VDDQ17 VDDQ16 VDDQ15
VDDQ13 VDDQ14 VDDQ12 VDDQ11 VDDQ10 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2
GFX_IMON
VDDQ1
GFX_DPRSLPVR GFX_VR_EN GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0 (SYM 7 OF 11)
IN OUT
OUT OUT OUT OUT OUT OUT
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
AF71 AG67 AG70 AH71 AN71 AM67 AM70 AH69
AN32
AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10 AN30
AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15 AN28
AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17
AN26 AN24 AN23 AN21 AN19 AL32
AF12
AK62
AB60 AB59 AA60 AA59 W60 W59 U60 U59 R60 R59
AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59
BU40
BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24 BU35
BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28 BU28
BB26 BB24 BB23 BB21 BB19 BB17 BB15
BN38 BM25 BL30 BJ38 BH32 BH28 AF10
AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15
W21
R19 R17
AD15 AD14 AD12 AB12 AA12 W17 W15 W14 W19
W12 R15
U21 U19 U17 U15 U14 U12 R21
8 91 PLACE_NEAR=U1000.AF10:25.4MM
402 1%
1001/16W
R14011
2
MF-LF 402 1/16W4.7K5%
100
402 MF-LF
PP1V05_S0PP1V1R1V05_S0_CPU_VTT0_DDRPP1V5_S3RS0
Trang 14VSS11
VSS16
VSS110 VSS111 VSS113 VSS112
VSS114 VSS116 VSS115
VSS118 VSS117
VSS119
VSS121 VSS120
VSS122
VSS124 VSS123
VSS125 VSS126 VSS127 VSS128 VSS129
VSS131 VSS130
VSS133 VSS132
VSS134
VSS136 VSS135
VSS137 VSS138 VSS139
VSS141 VSS140 VSS142 VSS143 VSS144
VSS147
VSS145 VSS146
VSS149 VSS148
VSS150
VSS1 VSS2 VSS3 VSS5 VSS4
VSS6 VSS7 VSS8
VSS10 VSS9
VSS13 VSS12
VSS14 VSS15
VSS17 VSS18 VSS19 VSS20 VSS21
VSS23 VSS22
VSS25 VSS24
VSS26 VSS28 VSS27
VSS29 VSS30 VSS31
VSS33 VSS32 VSS34 VSS35 VSS36
VSS39
VSS37 VSS38
VSS41 VSS40
VSS43 VSS42
VSS44
VSS46 VSS45
VSS47
VSS49 VSS48
VSS51 VSS50
VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS64 VSS63
VSS66 VSS65 VSS67
VSS69 VSS68
VSS71 VSS70
VSS72 VSS73 VSS74 VSS75
VSS76
VSS80
VSS78 VSS79
VSS82 VSS81
VSS85
VSS83 VSS84
VSS87 VSS86
VSS90
VSS88 VSS89
VSS92 VSS91 VSS93
VSS95 VSS94 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106
VSS108 VSS107 VSS109 (SYM 9 OF 11)
VSS215 VSS216 VSS214 VSS213 VSS212
VSS210 VSS211
VSS207 VSS208 VSS209
VSS205 VSS206 VSS204 VSS203 VSS202
VSS200 VSS201 VSS199
VSS197 VSS198
VSS195 VSS196 VSS194
VSS192 VSS193
VSS190 VSS191 VSS189
VSS187 VSS188
VSS185 VSS184
VSS186
VSS182 VSS183 VSS181 VSS180 VSS179
VSS177 VSS178 VSS176 VSS175 VSS174
VSS172 VSS173 VSS171
VSS169 VSS170
VSS166 VSS167 VSS168
VSS164 VSS165 VSS163 VSS162 VSS161
VSS159 VSS160 VSS158
VSS156 VSS157
VSS154 VSS155 VSS153 VSS152 VSS151
VSS227 VSS226
VSS228 VSS230 VSS229
VSS231
VSS239 VSS240
VSS232 VSS233 VSS234 VSS235 VSS236
VSS238 VSS237
VSS241
VSS250 VSS251 VSS249 VSS247
VSS242 VSS243
VSS246 VSS245 VSS244
VSS248
VSS261 VSS260 VSS259
VSS253 VSS252
VSS254 VSS256 VSS255
VSS257 VSS258
VSS270 VSS271 VSS268
VSS264 VSS263 VSS262
VSS265 VSS266 VSS267
VSS269
VSS272
VSS280 VSS281
VSS273 VSS274 VSS276 VSS275
VSS277 VSS278 VSS279
VSS282
VSS292
VSS290 VSS291 VSS288
VSS284 VSS283
VSS286 VSS285
VSS287 VSS289
VSS294 VSS293
VSS296 VSS295
VSS297 VSS298 VSS299 VSS300
VSS217 VSS218 VSS220 VSS219
VSS222 VSS221 VSS223
VSS225 VSS224
(SYM 10 OF 11)
VSS358
VSS363 VSS301
VSS429 VSS428 VSS427 VSS426
VSS423
VSS425 VSS424
VSS421 VSS422 VSS420
VSS418 VSS419
VSS416 VSS417
VSS414 VSS413
VSS415
VSS411 VSS412
VSS408 VSS409 VSS410
VSS406 VSS407 VSS405
VSS403 VSS404
VSS400
VSS402 VSS401
VSS398 VSS399 VSS397 VSS396 VSS395
VSS393 VSS394 VSS392 VSS391 VSS390
VSS388 VSS389 VSS387
VSS385 VSS386
VSS383 VSS384 VSS382
VSS380 VSS381
VSS377
VSS379 VSS378
VSS375 VSS376
VSS372 VSS373 VSS374
VSS371 VSS370
VSS367
VSS369 VSS368
VSS366 VSS365 VSS364 VSS362
VSS360 VSS361
VSS357
VSS359
VSS355 VSS356
VSS352 VSS353 VSS354
VSS351 VSS350
VSS347
VSS349 VSS348
VSS345 VSS346
VSS342
VSS344 VSS343
VSS340 VSS341 VSS339
VSS337 VSS338
VSS334 VSS335 VSS336
VSS332 VSS333
VSS330 VSS331 VSS329
VSS327 VSS328 VSS326 VSS325 VSS324
VSS322 VSS323 VSS321
VSS319 VSS320 VSS318 VSS317 VSS316
VSS314 VSS315 VSS313 VSS312 VSS311
VSS309 VSS310 VSS308 VSS307 VSS306 VSS305 VSS304 VSS303 VSS302
VSS432 VSS433 VSS431 VSS430 (SYM 11 OF 11)
REVISION
D
R PAGE TITLE
AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35 BU14
AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17 BU11
AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46 BU7
AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23 BP42
AR21
BN64 BN6 BM70 BM51 BU58
BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20 BU55
BK63 BK60 BK53 BK34 BK10 BJ64 BJ21 BJ9 BJ1 BH70 BU51
BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30 BU48
BF13 BF8 BE70 BE65 BE9 BE1 BD57 BD53 BD50 BD46 BU44
BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42 BU37
BB39 BB7 BB1 BA70 AY71 AY66
AY62 AY59 AY55 AY51
BU32
AY48 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26 BU25
AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4
BN71 E68 AH28 AH41 A66 AH26 BN1 A64 AH24 AH39 E5 AH23 C68 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30
K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B40
SYNC_DATE=06/15/2009SYNC_MASTER=K17_REF
CPU Grounds
<E4LABEL>
<SCH_NUM>
Trang 15OUT OUT OUT OUT OUT OUT OUT OUT OUT
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEMBOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
VID[2:0] = Reserved (111)VID[5:3] = GPU Gain Setting (See below)
NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
18
90A70A
20A30A
001
Intel recommends all option straps should be provided in layout
CPU Power On Configuration (POC) Straps
Equivalent Gain
4530
1512.85710
PSI# = Reserved (0)DPRSLPVR = 1 - IMVP-6.5 compliant controllerVID[6] = Reserved (0)
000
111110101100011010
50A60A
3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402
CPU Gain Setting
4x 470uF 4.5mOhm, 3x 62uF B2, 10x 22uF 0603, 25x 1uF 0402
CPU VCore HF and Bulk Decoupling
402
1KCPUPOC3U
2
1
R1606
MF-LF 5%
402
1KCPUPOC5U
2
1
R1616
MF-LF 402
1KCPUPOC5D
402 2
2
1R1613
MF-LF 5%
402
1KCPUPOC3D
20%
603 X5R-CERM 6.3V22UF
Place near U1000 on bottom side
NO STUFF
10%
1UF
X5R 1
Place near inductors on bottom side
2
C1606
10%
X5R 10%
1UF
X5R 1
2
C1605
X5R 1
2
C1611
10%
X5R 1
1UF
X5R 1
2
C1624
10%
X5R 10%
1UF
16V 402
2
C1620
402 10%
402 1
2
1UF
C1619
X5R 10%
1UF
16V 402 1
2
C1618
X5R 10%
1UF
16V 402 1
2
C1616
402 10%
1UF
X5R 1
2
C1615
16V 10%
1UF
X5R 1
10V 402 10%
2
1C1674
Place on bottom side of U1000
10V 402 10%
402 10V 2
1C1686
Place on bottom side of U1000
10%
X5R1UF
402 10V
2
1C1673
Place on bottom side of U1000
10V 4021UFX5R
402 10V
2
1C1672
Place on bottom side of U1000
10V 4021UFX5R 2
1C1671
Place on bottom side of U1000
10V 4021UFX5R
402 10V 2
1C1683
Place on bottom side of U1000
10%
X5R1UF
402 10V
2
1C1670
Place on bottom side of U1000
10V 4021UFX5R
402 10V
2
1C1669
Place on bottom side of U1000
10V 4021UFX5R
402 10V
2
1C1668
Place on bottom side of U1000
10V 4021UFX5R
402 10V
2
1C1667
Place on bottom side of U1000
10V 4021UFX5R 2
1C1666
Place on bottom side of U1000
10V 4021UFX5R
2
1C1643
6.3V X5R-CERM 603 20%
Place near inductors on bottom side
402 10V 2
1C1678
Place on bottom side of U1000
10%
X5R1UF
402 10V
2
1C1665
Place on bottom side of U1000
10V 4021UFX5R
402 10V
2
1C1664
Place on bottom side of U1000
10V 4021UFX5R
402 10V
2
1C1697
Place on bottom side of U1000
10V 4021UFX5R 2
1C1696
Place on bottom side of U1000
10V 402 10%
1UF
2 1 6.3V X5R-CERM 603 20%
Place near inductors on bottom side
2 1
L1695
0603
30-OHM-5A
2 1
6.3V22UF
603 20%
X5R-CERM
C1626
NO STUFFPlace near U1000 on bottom side
2 1
Place near U1000 on bottom side
603 20%
22UFX5R-CERM 6.3V
X5R-CERM22UF6.3V
2
1C1698
Place near U1000 on bottom side
603 20%
22UFX5R-CERM 6.3V 2
1C1694
Place near U1000 on bottom side
20%
6.3V 603 X5R-CERM22UF
C1693
2 1Place near U1000 on bottom side
60322UFX5R-CERM 6.3V 20%
NO STUFF
2 1Place near U1000 on bottom side
6.3V 603 20%
C1692
22UFX5R-CERM
62UF
20%
11V ELEC CASE-B2 2
62UF
20%
CASE-B2 2 1
20%
62UF
11V CASE-B2 2
1C16A2
1
11V ELEC 20%
CASE-B2
62UF
C16A4
603 20%
C1645
2 1 6.3V22UF
Place near inductors on bottom side
NO STUFF
X5R-CERM 2
1C1637
6.3V X5R-CERM 60322UF
Place near inductors on bottom side
NO STUFF
20%
X5R-CERM 2
1C1638
603
22UF20%
Place near inductors on bottom side
Place on bottom side of U1000
1UF
16V 402 1
6.3V X5R-CERM 603
22UF20%
NO STUFF
C1628
Place on bottom side of U1000
X5R 1
Place near inductors on bottom side
X5R-CERM22UF
6.3V22UF
NO STUFF
2
1C1648
6.3V X5R-CERM 603 20%
6.3V22UFX5R-CERM
1C1649
2.0V 20%
D2T-SM POLY-TANT
2
1C1653
6.3VPlace on bottom side of U1000
X5R-CERM 603
22UF20%
2
1C1654
Place on bottom side of U1000
X5R-CERM 603
22UF20%
1C1655
Place on bottom side of U1000
X5R-CERM 603
22UF20%
1C1656
Place on bottom side of U1000
X5R-CERM 603 20%
6.3V22UF
2
1C1663
603
10UF20%
6.3VPlace on bottom side of U1000
2
1C1662
603
10UF20%
6.3VPlace on bottom side of U1000
2
1C1661
603
10UF20%
6.3VPlace on bottom side of U1000
2
1C1660
603
10UF20%
6.3VPlace on bottom side of U1000
2
1C1659
603
10UF6.3V 20%
Place on bottom side of U1000
2
1C1658
X5R10UF6.3V 20%
Place on bottom side of U1000
2
1C1657
603
10UF6.3V 20%
Place on bottom side of U1000
X5R
1C1688
POLY-TANT 2.0V 20%
C1690
SYNC_MASTER=K17_REFCPU Non-GFX Decoupling (1 of 2)
SYNC_DATE=06/15/2009
CPUPOC3U,CPUPOC4U,CPUPOC5UCPUPOC_IMAX_70_90
CPUPOC3U,CPUPOC4D,CPUPOC5UCPUPOC_IMAX_50_60
CPUPOC3U,CPUPOC4U,CPUPOC5DCPUPOC_IMAX_60_70
Trang 16D
R PAGE TITLE
NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines
Memory (CPU VCCDDR) DECOUPLING
PLL (CPU VCCSFR) DECOUPLING
DDR Clock (CPU VDDQ_CK) DECOUPLING
NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs DG recommends 2x 22uF at SO_DIMM not provided Decoupling caps at SO-DIMMs on CSA 29 and CSA 31
10V 402
1UF10%
402 10V
C1744
1
2 10V 402
1UF10%
X5R
C1743
1
21UFX5R 10%
402 10V
C1742
1
2 10V 402
1UF10%
X5R
C1741
1
21UF10%
X5R
C1740
1
2 X5R
1UF10%
C1739
1
21UFX5R 10%
402 10V
C1738
1
2 10V 402
1UF10%
X5R
C1737
1
21UFX5R 10%
402 10V
C1736
1
2 10V 402
1UF10%
402 10V
C1753
1
2 10V 402
1UF10%
X5R
C1752
1
21UF10%
X5R
C1751
1
2 X5R
1UF10%
C1750
1
21UFX5R 10%
402 10V
C1749
1
2 402 10V1UF10%
C1748
1
21UFX5R 10%
402 10V
C1747
1
2 402 10V1UF10%
2
C1700
1UF10V 402
C1728
1
21UF
X5R 10%
402 10V
C1727
1
2 10V 402
1UF10%
X5R
C1726
1
21UF10%
402
C1725
1
2 X5R
1UF10%
402 10V
C1724
1
2
X5R-CERM 603 10%
6.3V4.7UF
C1733
1
2 805 CERM-X5R22uF6.3V 20%
C1732
1
2
10V 402 10%
SYNC_MASTER=K17_REFCPU Non-GFX Decoupling (2 of 2)
Trang 17IN IN OUT OUT IN IN OUT OUT
IN IN
IN IN
IN IN
OUT OUT
OUT OUT
OUT OUT
OUT
IN OUT
OUT OUT IN OUT OUT IN
OUT OUT
OUT OUT IN
OUT OUT
IN IN
IN IN
IN IN
IN IN
IN
IN
IN OUT
OUT
OUT BI
OUT BI
IN IN OUT OUT
FWH4/LFRAME*
SATA1GP/GPIO19
INTVRMEN
SATAICOMPI SATAICOMPO
SATA0TXN SATA0RXN
SATA0TXP SATA0RXP
SATA1TXP SATA1RXP SATA1RXN SATA1TXN
SATA2TXN SATA2RXN
SATA2TXP SATA2RXP
SATA5TXN SATA5RXN SATA4TXN SATA4RXN SATA3TXN SATA3RXN
SATA5TXP SATA5RXP SATA4TXP SATA4RXP SATA3TXP SATA3RXP
FWH1/LAD1
LDRQ0*
LDRQ1*/GPIO23 SERIRQ
FWH3/LAD3 FWH2/LAD2 FWH0/LAD0
SPI_CS0*
SPI_CLK
JTAG_TDO JTAG_RST*
JTAG_TDI JTAG_TMS JTAG_TCK HDA_DOCK_RST*/GPIO13 HDA_DOCK_EN*/GPIO33 HDA_SDO
HDA_SDIN2 HDA_SDIN3 HDA_SDIN1 HDA_SDIN0 HDA_RST*
CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_BCLK_N CLKIN_BCLK_P
CLKIN_DOT_96N CLKIN_DOT_96P
CLKIN_PCILOOPBACK
XTAL25_IN XTAL25_OUT
CLKOUT_PEG_A_P CLKOUT_PEG_A_N PEG_A_CLKRQ*/GPIO47
CL_RST1*
CL_DATA1 CL_CLK1 SML1DATA/GPIO75 SML1CLK/GPIO58 SML1ALERT*/GPIO74 SML0DATA SML0CLK SML0ALERT*/GPIO60 SMBDATA
CLKOUTFLEX1/GPIO65 CLKOUTFLEX0/GPIO64 XCLK_RCOMP
CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67
CLKOUT_PCIE0N CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE2N PCIECLKRQ1*/GPIO18
PCIECLKRQ2*/GPIO20 CLKOUT_PCIE2P
CLKOUT_PCIE3P CLKOUT_PCIE3N
PCIECLKRQ3*/GPIO25 CLKOUT_PCIE4N
PCIECLKRQ4*/GPIO26 CLKOUT_PCIE4P
CLKOUT_PCIE5P CLKOUT_PCIE5N
PCIECLKRQ5*/GPIO44
CLKOUT_PEG_B_P CLKOUT_PEG_B_N
PEG_B_CLKRQ*/GPIO56
PETP8 PETN8 PERP8 PERN8 PETP7 PETN7 PERP7 PERN7 PETP6
PERP6 PETN6
PETP5 PERN6
PERP5 PERN5 PETN5
PETP4 PETN4 PERP4 PERN4 PETP3 PETN3 PERP3 PERN3 PETP2
PERP2 PETN2
PETP1 PERN2
PERP1 PERN1
SMBALERT*/GPIO11
CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P
REFCLK14IN
CLKOUT_PCIE1P PCIECLKRQ0*/GPIO73
OUT OUT IN IN
IN
IN
OUT OUT
OUT
IN IN
OUT OUT
IN
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
All 4 CLKOUTFLEX outputs support
(IPD)
(IPU)
Unused(IPD)
(IPD)
(IPD)
eSATASSD
ODDHDD
(IPD)
(IPD)
(IPD) (IPD)
(IPU)
(IPU)
(IPD) (IPD) (IPD)
R18001
2 1/16W
1M
402 5%
R18021
2
20K
402 5%
1UF
10%
C18021 2
1%
402 MF-LF
MF-LF 402
R1820
1
2
IBEX_PEAK_MFCBGA
OMIT
U1800
D33 B33 C32 A32 C34
A30
H32 J30
C30 G30 F30 E32 F32
B29
D29
A16 A14
J4
M3
K1 J2 K3
A34 F34 C14
B13 D13
Y9
AK7 AK6 AK11 AK9
V1
AH6 AH5 AH9 AH8 AF11 AF9 AF7 AF6 AH3 AH1 AF3 AF1 AD9 AD8 AD6 AD5 AD3 AD1 AB3 AB1
AF15 AF16
T3
AB9
BA2 AV3 AY3
AV1 AY1
AP3 AP1
AW24 BA24
F18 E18
J42
AH13 AH12
AN4 AN2
AT1 AT3
AK48 AK47
AM43 AM45
AM47 AM48
AH42 AH41
AM51 AM53
AJ50 AJ52
AD43 AD45
AK53 AK51
T45 P43
J14 C6 G8
M14 E10 G12
AF38
AH51 AH53
90.9
R18901
2
MF-LF 5%
1/16W
R1812
402 MF-LF 5%
40210K
MF-LF 1/16W 5%
R1852 1 2 1/16W MF-LF 40210K
5%
R1851 1 2 1/16W MF-LF 40210K
5%
10K
402 MF-LF 1/16W 5%
10K
402 MF-LF 1/16W 5%
R1897 1 2 5% 1/16W MF-LF 40210K
10K
1/16W 5%
51
MF-LF 5%
R18281
2
XDP_PCH
402 1/16W 5%
51
R1827
1
2 402
XDP_PCH
51
MF-LF 5%
R18251
2
402 MF-LF 1/16W 5%
2.2K
PCH SATA/PCIE/CLK/LPC/SPI
SYNC_DATE=08/24/2009SYNC_MASTER=K17_REF
NC_PCIE_PE6_D2RN
PP1V05_S0
PCH_INTRUDER_L
SATA_ODD_D2R_NSATA_ODD_D2R_P
TP_SPI_CS1_L
SPI_MISOHDA_SDOUT_R
HDA_RST_LHDA_RST_R_L
HDA_SDOUTHDA_SDOUT_R
HDA_SYNCHDA_SYNC_R
HDA_BIT_CLKHDA_BIT_CLK_R
NC_SATA_C_D2RN
TP_LPC_DREQ0_L
PCH_SML0ALERT_LSML_PCH_0_CLKSML_PCH_0_DATA
PCH_SML1ALERT_L
PCIE_CLK100M_FW_PPCIE_CLK100M_FW_N
PCIE_CLK100M_ENET_NNC_PCIE_PE8_D2RPNC_PCIE_PE7_R2D_CP
SMBUS_PCH_CLKSMBUS_PCH_DATA
PCH_CLK33M_PCIIN
PCH_CLK25M_XTALINPCH_CLK25M_XTALOUT
HDA_BIT_CLK_R
NC_SATA_SSD2_D2RP
PCIE_CLK100M_AP_NPCIE_CLK100M_ENET_P
SMC_WAKE_SCI_L
NC_PCIE_PE6_R2D_CPNC_PCIE_PE6_D2RP
FW_CLKREQ_L
NC_PCIE_CLK100M_PE4NNC_PCIE_EXCARD_D2R_P
NC_PCIE_CLK100M_PE5N
NC_SATA_SSD2_R2D_CNNC_SATA_SSD2_D2RN
NC_PCIE_CLK100M_PEBP
PCH_INTVRMEN_L
NC_PCIE_CLK100M_EXCARD_PNC_PCIE_PE8_D2RN
PCH_CLK100M_SATA_N
NC_PCIE_EXCARD_R2D_C_P
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE7_D2RNNC_PCIE_PE7_D2RPNC_PCIE_PE7_R2D_CN
NC_PCIE_PE8_R2D_CP
NC_PCIE_CLK100M_PE4PNC_PCIE_CLK100M_EXCARD_N
LPC_SERIRQ
SATA_HDD_R2D_C_P
SML_PCH_1_CLKSML_PCH_1_DATA
NC_SATA_EXTA_D2R_NNC_SATA_D_R2D_CN
PCH_CLK32K_RTCX2PCH_CLK32K_RTCX1
SPI_DESCRIPTOR_OVERRIDE_LENET_ENERGY_DET
JTAG_PCH_TCKJTAG_PCH_TMS
SATARDRVR_A_EN
PCH_SPKRHDA_SYNC_R
FSB_CLK133M_PCH_PFSB_CLK133M_PCH_NPCIE_CLK100M_PCH_PPCIE_CLK100M_PCH_N
PCIE_CLK100M_CPU_NPEG_CLK100M_PPEG_CLK100M_NPEG_CLKREQ_LNC_SATA_C_D2RP
SATARDRVR_B_ENSATARDRVR_A_EN
AP_CLKREQ_L
PCH_SML1ALERT_L
MLB_RAM_VENDOR
JTAG_PCH_TDOJTAG_PCH_TCKJTAG_PCH_TMS
PCH_SRTCRST_L
SATARDRVR_B_EN
AP_CLKREQ_L
BRCRYPT_PWR_ENNC_PCIE_CLK100M_PE5PEXCARD_CLKREQ_L
BRCRYPT_RESETSMC_WAKE_SCI_L
EXCARD_CLKREQ_LFW_CLKREQ_LENET_CLKREQ_L
NC_PCIE_EXCARD_R2D_C_NNC_PCIE_EXCARD_D2R_NPCIE_FW_D2R_P
RTC_RESET_L
ENET_ENERGY_DET
SATA_HDD_D2R_PSATA_HDD_D2R_N
PCIE_FW_D2R_NPCIE_AP_R2D_C_PPCIE_AP_R2D_C_NPCIE_AP_D2R_PPCIE_AP_D2R_NPCIE_ENET_R2D_C_PPCIE_ENET_R2D_C_NPCIE_ENET_D2R_PPCIE_ENET_D2R_N
RTC_RESET_L
HDA_SDIN0PCH_SRTCRST_L
MLB_RAM_SIZE
PP3V42_G3H
SPI_DESCRIPTOR_OVERRIDE_LPP3V3_S5
JTAG_PCH_TDIJTAG_PCH_TDOTP_JTAG_PCH_TRST_L
PP3V3_S3
SPI_MOSI_RSPI_CLK_R
Trang 18IN IN
IN
OUT OUT OUT OUT OUT
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
OUT OUT
OUT OUT
OUT OUT OUT OUT OUT
OUT OUT
OUT
OUT
OUT OUT
OUT OUT
OUT OUT
OUT
OUT OUT OUT OUT BI
BI BI IN OUT OUT
OUT BI
OUT OUT
OUT OUT OUT
OUT
IN BI
OUT OUT OUT OUT
BI OUT
OUT IN
IN IN IN
IN IN
FDI_RXN0
DMI3RXN
RI*
BATLOW*/GPIO72 ACPRESENT/GPIO31 PWRBTN*
SUS_PWR_ACK/GPIO30 RSMRST*
LAN_RST*
DRAMPWROK MEPWROK PWROK SYS_PWROK SYS_RESET*
SLP_M*
SLP_S4*
SLP_S3*
SUSCLK/GPIO62 SLP_S5*/GPIO63
CLKRUN*/GPIO32
SUS_STAT*/GPIO61
WAKE*
DMI_ZCOMP DMI_IRCOMP
FDI_FSYNC1 FDI_FSYNC0
FDI_LSYNC0 FDI_LSYNC1
DMI3TXP DMI2TXP
DMI0TXP DMI1TXP DMI3TXN DMI2TXN DMI1TXN DMI0TXN DMI3RXP DMI2RXP
DMI0RXP DMI1RXP
FDI_INT FDI_RXP7 FDI_RXP6 FDI_RXP5 FDI_RXP4
FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP0 FDI_RXN7 FDI_RXN6 FDI_RXN5 FDI_RXN4 FDI_RXN3 FDI_RXN2 FDI_RXN1 DMI2RXN
DMI1RXN DMI0RXN
SLP_LAN*
PMSYNCH TP23
CRT_DDC_CLK CRT_DDC_DATA CRT_RED CRT_GREEN CRT_BLUE
DDPD_3N DDPD_3P DDPD_2P DDPD_2N DDPD_1P DDPD_1N
DDPD_0N DDPD_0P DDPD_HPD
DDPD_CTRLDATA DDPD_CTRLCLK DDPC_3P
DDPC_2P DDPC_3N DDPC_2N DDPC_1P DDPC_1N
DDPC_0N DDPC_0P DDPC_HPD
DDPC_CTRLDATA DDPC_CTRLCLK
DDPB_3N DDPB_2P DDPB_3P DDPB_2N DDPB_1P
DDPB_0P DDPB_1N DDPB_0N DDPB_HPD
SDVO_CTRLDATA SDVO_CTRLCLK
LVDSB_DATA3 LVDSB_DATA2 LVDSB_DATA1 LVDSB_DATA0 LVDSB_DATA3*
LVDSB_DATA2*
LVDSB_CLK LVDSB_CLK*
LVDSA_DATA3
LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3*
LVDSA_DATA1*
LVDSA_DATA0*
LVDSA_CLK LVDSA_CLK*
LVD_VREFH
LVD_IBG LVD_VBG
L_CTRL_DATA L_CTRL_CLK L_DDC_DATA L_DDC_CLK L_BKLTCTL
L_BKLTEN L_VDD_EN
LVD_VREFL
SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP
DDPB_AUXP DDPB_AUXN
DDPC_AUXN DDPC_AUXP
DDPD_AUXN DDPD_AUXP
LVDSB_DATA1*
LVDSB_DATA0*
LVDSA_DATA0 LVDSA_DATA2*
B
(IPU)
(IPD) (IPD)
(IPU)
(IPD)
(IPD) (IPU) (IPD)
0.5% recommended, Intel okaywith 5% when CRTDAC not used
U1800
P7 A6
D9
BF13 BH13 BJ14
BJ12 BG14
BA18 BD16 BJ16 BA16 BE14 BA14 BC12 BB18 BC16 BG16 AW16 BD14 BB14 BD12
A10 K5
BJ10 P5
B17
F14 C16
F6
K8 P12 H7 E4
M1
P8 F3
M6 T6
N2 J12
U1800
AA52
V51 V53 AB53
BG44 BJ44 AU38
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
BE44 BD44
Y49 AB49
AV40
BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
BC46 BD46
U50 U52
AT38
Y48 T48
AB46 V48
AB48 Y45 T47
AP39 AP41
AT43 AT42
AV51 AV53
BB48 BB47
BA50 BA52
AY49 AY48
AV48 AV47
AP47 AP48
AY51 AY53
AT48 AT49
AU50 AU52
AT51 AT53
T51 T53
BF45 BH45
BJ48 BG48
BJ46 BG46
NC_CRT_IG_HSYNCNC_CRT_IG_DDC_DATANC_CRT_IG_DDC_CLK
NC_CRT_IG_GREENNC_CRT_IG_BLUE
NC_DP_IG_D_AUXPNC_DP_IG_D_AUXNNC_DP_IG_C_AUXP
DP_IG_AUX_CH_NDP_IG_AUX_CH_P
NC_SDVO_INTPNC_SDVO_INTNLVDS_IG_PANEL_PWR
LVDS_IG_DDC_DATANC_LVDS_IG_CTRL_CLKNC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG
DP_IG_DDC_CLKDP_IG_DDC_DATA
DP_IG_HPDDP_IG_B_ML_N<0>
NC_CRT_IG_VSYNC
LPC_PWRDWN_LMAKE_BASE=TRUELPC_PWRDWN_L
PCH_LVDS_IBG
PM_BATLOW_LSMC_ADAPTER_EN
PM_SUS_PWR_ACKPM_PWRBTN_LPM_RSMRST_LPM_MEM_PWRGDPM_SYSRST_L
NC_CRT_IG_RED
PM_CLKRUN_LPM_SUS_PWR_ACKPP3V3_S0
PM_BATLOW_LPCIE_WAKE_LPP3V3_S5
Trang 19BI BI
BI BI
OUT OUT OUT
IN
OC7*/GPIO14 OC6*/GPIO10 OC5*/GPIO9 OC4*/GPIO43 OC3*/GPIO42 OC1*/GPIO40 OC0*/GPIO59 USBRBIAS USBRBIAS*
USBP13N USBP12N USBP11N USBP10N USBP9N USBP8N USBP7N USBP6N USBP5N USBP4N USBP3N USBP2N USBP1N USBP0N
USBP13P USBP12P USBP11P USBP10P
USBP8P USBP9P
USBP7P USBP6P USBP5P USBP4P USBP3P USBP2P USBP1P USBP0P
NV_DQ13/NV_IO13 NV_DQ14/NV_IO14
NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12
NV_DQ8/NV_IO8 NV_DQ9/NV_IO9 NV_DQ7/NV_IO7 NV_DQ6/NV_IO6 NV_DQ5/NV_IO5
NV_DQ3/NV_IO3 NV_DQ4/NV_IO4
NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ0/NV_IO0
NV_DQS0 NV_DQS1
AD20
AD28 AD29
SERR*
PERR*
GNT1*/GPIO51 REQ1*/GPIO50
PIRQG*/GPIO4 PIRQH*/GPIO5 PCIRST*
AD0 AD1
AD4 AD5 AD6 AD7 AD8
AD10 AD11 AD12 AD13 AD14
AD24 AD25 AD26
PLOCK*
PME*
REQ2*/GPIO52 REQ3*/GPIO54
STOP*
TRDY*
AD15 AD16 AD17 AD18 AD19
CLKOUT_PCI1
CLKOUT_PCI3 CLKOUT_PCI0
IN IN IN
IN
BI BI
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
R20621
2
5%
1/16W 402
E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C44
C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 A38
M47 H36
C36 J34 A40 D45 E36 H48
J50 G42 H47 G34
N52 P53 P46 P51 P48
F46 C46
F48 K45 F36 H53
A42
BD3
AY9 BD1 AP15 BD8
AY6
AP7
BD6 BB7 BC8 BJ8 BJ6 BG6
AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6
AV9 BG8
AV7 AU2
AV11 BF5
AY8 AY5
N16 J16 F16 L16 E14 G16 F12 T15
H44
K6
E50
G38 H51 B37 A44
B41 K53 A36 A48
D49
D5 M7
F51 A46 B45 M53
E44
D41 C48
H18 J18
A22 C22 G24 H24 L24 M24 A24 C24
A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22
D25 B25
27
10K
402 1/16W 5%
10K
1/16W 5%
R2081 1 2 5% 1/16W MF-LF 40210K
USB_HUB_SOFT_RESET_LPCH_GPIO41
PCH_GPIO59
NC_USB_12NNC_USB_9N
NC_PCI_PME_L
PCI_REQ3_LJTAG_GMUX_TDI
NC_PCI_GNT3_L
PCI_DEVSEL_LPCI_FRAME_L
MIKEY_MIC_LOAD_DET
PCI_PERR_L
PCI_STOP_L
LPC_CLK33M_LPCPLUS_RPCI_TRDY_L
NC_PCI_AD<2>
NC_NV_WE_CK_L<0>
NC_NV_CLENC_NV_ALE
PCI_INTB_LPCI_INTA_L
PCI_REQ0_LPCI_INTD_L
PCI_SERR_L
PCI_IRDY_L
PLT_RESET_LLPC_CLK33M_SMC_R
PCH_CLK33M_PCIOUTPCI_PLOCK_L
PM_LATRIGGER_LPCH_GPIO59PP3V3_S5
NC_PCI_AD<12>
AUD_I2C_INT_L
JTAG_GMUX_TMS
PCH_GPIO2PCI_REQ3_L
NC_USB_6P
NC_USB_10P
NC_USB_12PNC_USB_10N
NC_USB_6NNC_USB_4NNC_USB_3N
NC_USB_7N
PCH_USB_RBIASNC_USB_13N
NC_USB_5PNC_USB_5NNC_USB_4PNC_USB_3PNC_USB_1P
NC_USB_13PNC_USB_11N
Trang 20OUT OUT
NC_1 NC_2
TP8
TP19 TP18 TP17
TP15 TP16 TP14 TP13 TP12 TP11
TP9 TP10
INIT3_3V*
TP24 VSS_NCTF31
VSS_NCTF30
VSS_NCTF28 VSS_NCTF29
VSS_NCTF25 VSS_NCTF26 VSS_NCTF27
VSS_NCTF24 VSS_NCTF23 VSS_NCTF22 VSS_NCTF21 VSS_NCTF20 VSS_NCTF19 VSS_NCTF18 VSS_NCTF17 VSS_NCTF16 VSS_NCTF15 VSS_NCTF14 VSS_NCTF13 VSS_NCTF12
VSS_NCTF10 VSS_NCTF11
VSS_NCTF8 VSS_NCTF9 VSS_NCTF7 VSS_NCTF6 VSS_NCTF5
VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF1 GPIO57 SATA5GP/GPIO49 SDATAOUT1/GPIO48 PCIECLKRQ7*/GPIO46
SDATAOUT0/GPIO39 PCIECLKRQ6*/GPIO45 SLOAD/GPIO38 SATA3GP/GPIO37 SATA2GP/GPIO36 SATACLKREQ*/GPIO35 STP_PCI*/GPIO34
GPIO27 GPIO28 MEM_LED/GPIO24
TACH0/GPIO17 SCLOCK/GPIO22 SATA4GP/GPIO16 GPIO15 LAN_PHY_PWR_CTRL/GPIO12 GPIO8
TACH3/GPIO7
TACH1/GPIO1 TACH2/GPIO6 BMBUSY*/GPIO0
THRMTRIP*
PROCPWRGD RCIN*
PECI CLKOUT_BCLK0_P/CLKOUT_PCIE8P CLKOUT_BCLK0_N/CLKOUT_PCIE8N
A20GATE CLKOUT_PCIE7N CLKOUT_PCIE6P CLKOUT_PCIE6N
TP3
CLKOUT_PCIE7P (6 OF 10)
BI OUT
OUT
BI OUT OUT OUT OUT
OUT IN
OUT
OUT OUT
REVISION
D
R PAGE TITLE
B
(IPD)
(IPU*) (IPU*) IPU* = Only on TACH function.
(IPU*) (IPD) (IPU*)
56
R2161
MF-LF 402 5%
AM3 AM1
AH45 AH46 AF48 AF47
T7
AB12 V13
F8 F10
P6
K9
H10
AB45 AB38 AB42 AB41 T39
H3 F1
BG10
BE10 T1
AB7 AB13 AA2
AA4
V6 Y7
P3
AB6 V3 M11 F38
C38 D37 J32
BD10
BA22
N18
AJ24 AK41
AK42
M32 N32
M30 N30
H12
AA23 AW22
C10
BB22 AY45
AY46
AV43 AV45
AF13
M18 A4
A49
BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 A5
BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 A50
E53
A52 A53 B2 B4 B52 B53
R2116 10K 1 2
2.2K
MF-LF 1/16W
2 1
MF-LF 1/16W10K
10K
1/16W 5%
10K
1/16W 5%
MF-LF10K
402 1/16W
1/16W10K
PCH MISC
SMC_IG_THROTTLE_LPP3V3_S0
PCH_FCIM_EN_LSMC_RUNTIME_SCI_LGMUX_INT
MXM_GOOD
MXM_GOOD
WOL_ENAP_PWR_ENJTAG_GMUX_TCKODD_PWR_EN_L
FW_PWR_ENSDCARD_RESET
LPCPLUS_GPIO
ISOLATE_CPU_MEM_L
JTAG_GMUX_TDOJTAG_GMUX_TCK
WOL_ENAP_PWR_EN
ME_TEMP_ALERT_L
PCH_GPIO24ODD_PWR_EN_LAUD_IPHS_SWITCH_EN
PCH_FCIM_EN_L
NC_PCIE_CLK100M_PE7P
NC_PCIE_CLK100M_PE6NNC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
FSB_CLK133M_CPU_NFSB_CLK133M_CPU_P
CPU_PECIPCH_GPIO15
PCH_GPIO24PCH_VRM_EN
NC_PCH_NC5NC_PCH_NC3NC_PCH_TP17
NC_PCH_TP1
NC_PCH_TP4NC_PCH_TP3NC_PCH_TP2PCH_THRMTRIP_L
NC_PCH_NC2NC_PCH_NC1NC_PCH_TP19
PCH_GPIO15
CPU_PWRGD
SMC_RUNTIME_SCI_LGMUX_INT
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<27>
LPCPLUS_GPIOAUD_IPHS_SWITCH_ENPP3V3_S5
Trang 21VCCIO55 VCCIO54 VCCIO53 VCCIO52 VCCIO51 VCCIO50 VCCIO49 VCCIO48 VCCIO47 VCCIO46 VCCIO45 VCCIO44 VCCIO43 VCCIO42 VCCIO41 VCCIO40 VCCIO39 VCCIO38 VCCIO37 VCCIO36 VCCIO35 VCCIO34 VCCIO33 VCCIO32 VCCIO31 VCCIO29 VCCIO28 VCCIO27 VCCIO26 VCCIO25
VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4
VCC3_3_2 VCC3_3_4 VCC3_3_3
VCCPNAND1 VCCPNAND2 VCCPNAND3 VCCPNAND4 VCCPNAND5 VCCPNAND6 VCCPNAND7 VCCPNAND8 VCCPNAND9
VCCME3_3_1 VCCME3_3_2 VCCME3_3_3 VCCME3_3_4
VCC3_3_1
VCCVRM1
VSSA_LVDS
VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15
VCCDMI1 VCCDMI2 VCCIO30
VCCSUS3_3_29
VCCME3
V5REF V5REF_SUS
VCC3_3_8 VCC3_3_9
VCC3_3_11 VCC3_3_10
VCC3_3_12 VCC3_3_13
VCC3_3_14
VCCSATAPLL1 VCCSATAPLL2
VCCVRM4
VCCME13 VCCME14 VCCME15 VCCME16
VCCSUSHDA VCCRTC
V_CPU_IO1 V_CPU_IO2
VCCACLK1 VCCACLK2
VCCLAN1 VCCLAN2
VCCME1 DCPSUSBYP
VCCME2
VCCME6 VCCME5 VCCME4
VCCME7 VCCME8 VCCME9
VCCME11 VCCME10
DCPRTC VCCME12
VCCVRM3
VCCADPLLA1 VCCADPLLA2
VCCADPLLB2 VCCADPLLB1
VCC3_3_5 VCCSUS3_3_31
VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO9
VCCIO56 VCCIO21
VCCIO22 VCCIO23 VCCIO2 VCCIO3 VCCIO4
VCCIO5 VCCIO6 VCCIO7 VCCIO8
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
85 mA S0, 22 mA M-on
69 mA
3062 mA (VCCIO[1-56] total)
5 mA (if GPIO27 is low)
40 mA (if GPIO27 is low)
357 mA < 1 mA S0-S5
PCH output, for decoupling only
PCH output, for decoupling only
OMIT
U1800
AN35
AB34 AB35 AD35
AE50 AE52
AH38
BJ24
AB24
AH26 AH28 AH30 AH31 AJ30 AJ31
AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31
AT16 AU16
BJ18
AM23
AK24
AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 AN30 AN31
AM8 AM9 AP11 AP9
AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
AP43 AP45 AT46 AT45
AT22
AT24
AF53 AF51
AH39
IBEX_PEAK_MFCBGA
AT18 AU18
M36 N36 P36 U35
AD13
V15 V16 Y16
J38 L38
AP51 AP53
BB51 BB53
BD51 BD53
AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22 AF34
AD22
AH23 AJ35 AH35
AH34 AF32
V24
V23
V26 Y24 Y26
AH22
AF23 AF24
AD38
Y39 Y41 Y42
AA34 Y34 Y35 AA35
AD39 AD41 AF43 AF41 AF42 V39 V41 V42
A12
AK3 AK1
V28
M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 U28
F26 E28 E26 C28 C26 B27 A28 A26 U23
P18
U26
U19 U20 U22
U24 P28 P26 N28 N26 M28
CERM PLACE_NEAR=U1800.Y22:2.54MM
C22251 2 402-HF
1%
0.2
1/6W MF
PP3V3_S0
MIN_NECK_WIDTH=0.2 mmPPVOUT_G3_PCH_DCPRTC
VOLTAGE=X.XV MIN_LINE_WIDTH=0.2 mm
PP3V3_S0
PP1V8_S0
PP1V05_S0_PCH_VCCADPLLB
PP3V3_S0PP1V8_S0
PP3V3_S0_PCH_VCCA_DAC
PP3V3_S0
PP1V8_S0_PCH_VCCTX_LVDS
PP1V05_S0PP1V8_S0PP3V3_S0PP3V3_S5
PP1V05_S0_PCH_VCCADPLLAPP1V05_S0
PP3V3_S0
PPVOUT_S5_PCH_DCPSUSMIN_LINE_WIDTH=0.2 mm VOLTAGE=X.XV
Trang 22VSS VSS
(8 OF 10)
VSS VSS
AA32
AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AB11
AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AB15
AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AB23
AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AB30
AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AB31
AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47
AB32 AB39 AB43 AB47 AA20
AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AA22
AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 AM19
Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AA24
AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AA26
AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AA28
AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28
AA30
AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AA31
AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26
H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45
PCH Grounds
SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009
<E4LABEL>
<SCH_NUM>
Trang 23NC
NC
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
BB: C2419 removed from DGBB: C2417 removed from DGWF: C2413 not in DG or CRB
(PCH PCI 3.3V PWR)
PCH VCCFDIPLL Filter
(PCH PCIe PLL PWR)PCH VCCAPLLEXP Filter
WF: C2311 not in DG or CRB
(PCH FDI PLL PWR)
(PCH SATA PLL PWR)PCH VCCSATAPLL Filter
PCH VCCACLK Filter(PCH Misc PLL PWR)
(PCH PCIe/DMI 3.3V PWR)
PCH VCC3_3 BYPASS
(PCH 1.05V ME Core PWR)PCH VCCME BYPASS
(PCH ME 3.3V PWR)
(PCH SUSPEND PCI 3.3V PWR)PCH VCCSUS3_3 BYPASS
(PCH 1.05V CORE PWR)(PCH NAND 1.8V/3.3V PWR)
PCH VCCPNAND BYPASS
PCH VCCSUSHDA BYPASS(PCH HD Audio 3.3V/1.5V PWR)
(PCH SATA 1.05V PWR)
PCH VCCIO BYPASS(PCH PCIE 1.05V PWR)
(PCH 1.1V/1.05V CPU I/O PWR)PCH V_CPU_IO BYPASS
(PCH 1.05V LAN Core PWR)PCH VCCLAN BYPASS
(PCH DMI 1.05V PWR)PCH VCCIO BYPASS
1UFX5R PLACE_NEAR=U1800.K49:2.54MM
C24011
2
NO STUFF
6.3V 10%
402 CERM1UF
2
5%
1/16W 402 MF-LF100
R24012
1
BAT54DW-X-GSOT-363
D2400
1
6 5
1/16W 402 5%
MF-LF10
16V 4020.1UF
2
16V 4020.1UF
CERM1UFOMIT
2
6.3V 10%
4021UFOMIT
402 CERM1UF
2
X5R
0.1UF10%
C2426
1
2
0.1UFX5R 10%
2
0.1UF
X5R 10%
C2436
1
2
0.1UFX5R 10%
2
0.1UFX5R
2
0.1UF
X5R 10%
2
16V 4020.1UF
2
1UFCERM 402 10%
6.3V
2
16V 4020.1UF
PLACE_NEAR=U1800.AT18:2.54MM
C2452
1
2 16V 4020.1UF
PLACE_NEAR=U1800.AT18:2.54MM
C24501 2
6.3V 10%
402 CERM1UF
PLACE_NEAR=U1800.V39:2.54MM
C2469
1
2 6.3V
X5R-CERM 603
22UF20%
PLACE_NEAR=U1800.V39:2.54MM
C24671 2 6.3V
X5R-CERM 603
22UF20%
PLACE_NEAR=U1800.AD38:2.54MM
C24661 2
NO STUFF
1UF10%
6.3V 402 CERM
2
6.3V 10%
402 CERM1UF
PLACE_NEAR=U1800.AH35:2.54MM
C2477
1
2 6.3V 10%
402 CERM1UF
PLACE_NEAR=U1800.AH23:2.54MM
C2476
1
2 6.3V 10%
402 CERM1UF
2
6.3V 10%
402 CERM1UF
2
6.3V 10%
402 CERM1UF
2
PLACE_NEAR=U1800.AN20:2.54MM
6.3V 10%
402 CERM1UF
C2494
1
2 6.3V 10%
402 CERM1UF
PLACE_NEAR=U1800.AN20:2.54MM
C2493
1
2 6.3V 10%
402 CERM1UF
PLACE_NEAR=U1800.AN20:2.54MM
C2492
1
2 402 6.3V 10%
CERM1UF
PLACE_NEAR=U1800.AN20:2.54MM
C2491
1
210UF
603
PLACE_NEAR=U1800.AN20:2.54MM
C24901 2
402 6.3V 10%
CERM1UF
2
6.3V 10%
402 CERM1UF
PLACE_NEAR=U1800.AD38:2.54MM
C2468
1
2 6.3V
X5R-CERM 603
22UF20%
PLACE_NEAR=U1800.AD38:2.54MM
C24651 2
10%
402
1UF6.3V
PLACE_NEAR=U1800.AB24:2.54MM
C24701 2
402 CERM1UF
PLACE_NEAR=U1800.A12:2.54MM
C24201 2
PLACE_NEAR=U1800.F24:2.54MM
4021UFX5R 10%
C24001
2
SYNC_DATE=06/15/2009SYNC_MASTER=K17_REF
PCH Non-GFX Decoupling
PP5V_S5
PP5V_S0
PP5V_S0_PCH_V5REFMIN_LINE_WIDTH=0.3MM VOLTAGE=5V MIN_NECK_WIDTH=0.25MM
PP1V05_S0PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0PP1V05_S0
GND
PP1V8_S0
PP3V3_S0PP3V42_G3H
PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S5
PP3V3_S5
PP1V05_S0PP3V3_S0
PP1V05_S0_PCH_VCCA_CLK
VOLTAGE=1.05V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
PP1V05_S0_PCH_VCCAPLL_SATA
VOLTAGE=1.05V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
PP1V05_S0_PCH_VCCAPLL_FDI
VOLTAGE=1.05V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MMPP1V05_S0_PCH_VCCAPLL_EXP
PP5V_S5_PCH_V5REFSUSMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V
Trang 24D
R PAGE TITLE
B
(PCH DPLLA PWR)PCH VCCADPLLA Filter
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F actor Schematic Check List Rev 1.1 (doc #395914) table 3.26
VCAP2 (CPU BSC Package) DECOUPLING
PLACEMENT_NOTE (C2524-C2539):
PLACEMENT_NOTE (C2500-C2506):
3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402
GFX (CPU VCCAXG) DECOUPLING
402
0.01UF20%
PLACE_NEAR=U1800.BB51:2.54MM1UF
6.3V 10%
PLACE_NEAR=U1800.BB51:2.54MM
C25601 2
NO STUFF
PLACE_NEAR=U1800.BD51:2.54MM
402 6.3V1UF10%
C2566
1
2 PLACE_NEAR=U1800.BD51:2.54MM
220UF
POLY-TANT CASE-B2-SM1 20%
2.5V
C25651 2
MF-LF 402 1/16W
4020.01UF
C2552
1
2 PLACE_NEAR=U1800.AE50:2.54MM
20%
6.3V X5R10UF
C25501 2
Place on bottom side of U1000
22UF20%
603 X5R-CERM 6.3V
1UF10%
402 10V
C2513
1
2Place on bottom side of U1000
X5R 10%
1UF
402 10V
402 10V
C2511
1
2Place on bottom side of U1000
10V 402
1UF10%
POLY-TANT 2.0V
330UF
C2505
1
2 3
330UF
D2T-SM2 2.0V 20%
POLY-TANT
C2506
1
2 3
603 X5R-CERM PLACE_NEAR=U1800.AP43:2.54MM
22UF20%
6.3V
C25701 2
6.3V X5R-CERMPlace on bottom side of U1000
X5R1UF10V
C2535
1
2 402 10%
X5R1UF
C2534
1
2 402 10%
X5R1UF10V
C2533
1
2 402 10%
X5R1UF10V
C2532
1
2 402 10%
X5R1UF10V
C2531
1
2 402 10%
X5R1UF
C2530
1
2 402 10%
X5R1UF10V
C2529
1
2 402 10%
X5R1UF10V
X5R
C2527
1
2Place on bottom side of U1000
402 10%
X5R1UF
C2526
1
2Place on bottom side of U1000
402 10V1UF
C2525
1
2Place on bottom side of U1000
402 10%
X5R1UF10V
C2524
1
2
402 10V1UF
C2539
1
2 402 10V1UF
C2538
1
2 402 10%
X5R1UF10V
C2537
1
2 402 10%
X5R1UF10V
Place on bottom side of U1000
C2502
1
2
SYNC_DATE=06/15/2009SYNC_MASTER=K17_REF
CPU/PCH GFX Decoupling
PPVCORE_S0_CPU_VCAP2PPVCORE_S0_GFX
PP3V3_S0
PP1V8_S0
PP3V3_S0_PCH_VCCA_DAC_FMIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM VOLTAGE=3.3V
PP1V8_S0_PCH_VCCTX_LVDS
VOLTAGE=1.8V MIN_NECK_WIDTH=0.2 MM
PP1V05_S0
PP3V3_S0_PCH_VCCA_DACMIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
VOLTAGE=1.05V MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MMPP1V05_S0_PCH_VCCADPLLA_F
VOLTAGE=1.05V MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MMPP1V05_S0_PCH_VCCADPLLB_F
PP1V05_S0_PCH_VCCADPLLBMIN_LINE_WIDTH=0.4 MM
Trang 25OUT BI
OUT IN
IN IN
IN IN
IN IN
IN IN
IN IN
OUT
IN
IN
IN OUT OUT
IN IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN IN IN
IN IN
IN IN
IN IN
IN
IN IN
IN IN
TABLE_5_ITEM
TABLE_5_HEAD
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V
OBSFN_D0OBSFN_D1
PCH GPIO21PCH GPIO19
PCH GPIO36PCH GPIO37
PCH GPIO16PCH GPIO49
PCH GPIO0
OBSFN_D1
OBSDATA_D0
RESET#/HOOK6DBR#/HOOK7
TRSTn
XDP_PRESENT#
TDITCK1
OBSDATA_B3
PWRGD/HOOK0HOOK1
HOOK3
SDASCL
OBSDATA_A0OBSFN_A0
OBSFN_B1
OBSDATA_A0OBSDATA_A1
OBSFN_B0OBSDATA_A2
OBSFN_A0OBSFN_A1
OBSDATA_B3
PWRGD/HOOK0HOOK1VCC_OBS_ABOBSDATA_B2
HOOK3
TCK1TCK0
OBSDATA_B0OBSDATA_B1
OBSDATA_D2OBSDATA_D1
SDASCL
OBSDATA_C1
OBSDATA_C3OBSDATA_C2
OBSFN_C1OBSFN_C0
ITPCLK/HOOK4ITPCLK#/HOOK5OBSDATA_D3
XDP_PRESENT#
TDO
TDITMS
OBSDATA_C1
ITPCLK/HOOK4OBSDATA_C0
HOOK2VCC_OBS_AB
OBSDATA_A2OBSDATA_A3
OBSFN_B0OBSFN_B1
OBSDATA_B0OBSDATA_B1
J2600
F-ST-SM
LTH-030-01-G-D-NOPEGS
CRITICALOMIT
XDP_CONN_PCH
9 8 7
60 6
59 58 57 56 55 54 53 52 51 50 5
49 48 47 46 45 44 43 42 41 40 4
39 38 37 36 35 34 33 32 31 30 3
29 28 27 26 25 24 23 22 21 20 2
19 18 17 16 15 14 13 12 11 10 1
R2611
PLACE_NEAR=U1000.N70:1.00MM
5%
MF-LF 402
R2690
MF-LF 402
0
5%
XDP_NORMAL&XDP_CPU
2 1
R2610
1/16W 5%
XDP
MF-LF 402
1K
2 1
R2695
5%
0
402 1/16W
XDP_CPU
2 1
R2696
MF-LF 402 5%
XDP_GMCH
0
2 1
R2692
MF-LF 402
6 7 8
4 3 2 1
RP2600
1/16W 5%
0
XDP_CPU_BPM
8 7 6 5
1 2 3 4
RP2601
SM-LF
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.
1/16W 5%
eXtended Debug Port (XDP)
TP_XDP_HOOK3
SMBUS_PCH_DATASMBUS_PCH_CLK
TP_XDPPCH_OBSFN_A<0>
TP_XDPPCH_OBSFN_A<1>
USB_HUB_SOFT_RESET_LPCH_GPIO59
PCH_GPIO42PCH_GPIO41
TP_XDPPCH_OBSFN_B<1>
TP_XDPPCH_OBSFN_B<0>
PCH_GPIO43PCH_GPIO9
PCH_GPIO10PM_LATRIGGER_L
ALL_SYS_PWRGDPM_PWRBTN_L
TP_XDPPCH_HOOK2TP_XDPPCH_HOOK3
SMBUS_PCH_DATASMBUS_PCH_CLK
JTAG_PCH_TCK
TP_XDPPCH_HOOK4ME_TEMP_ALERT_LAUD_IPHS_SWITCH_ENJTAG_GMUX_TCKSDCARD_RESETTP_XDPPCH_OBSFN_D<1>
TP_XDPPCH_OBSFN_D<0>
SATARDRVR_A_ENSATARDRVR_B_EN
FW_CLKREQ_LAP_CLKREQ_L
SMC_IG_THROTTLE_LISOLATE_CPU_MEM_L
JTAG_PCH_TDIJTAG_PCH_TMSTP_XDPPCH_TRST_LJTAG_PCH_TDOXDP_DBRESET_LXDPPCH_PLTRST_LTP_XDPPCH_HOOK5
XDP_TCK
XDP_OBSDATA_A<2>
XDP_PWRGD
XDP_TDOXDP_OBSDATA_A<1>
XDP_TDOXDP_TDI
FSB_CLK133M_ITP_N
XDP_DBRESET_L
XDP_TDIXDP_TMS
Trang 26BI IN
OUT OUT
OUT OUT OUT OUT
OUT
CPU0*
CPU0
REF_FS USB
CPU1 CPU1*
SRC1*
SRC1 SRC0*/SATA*
SRC0/SATA 27M_NSS 27M_SS DOT96*
XOUT XIN
SCLK SDATA CK_PWRGD/PWRDWN*
PAD
OUT OUT
Muxed Graphics implementations
or connected to logic for Must be strapped appropriately
(IPD)
PCH USB Clock 96MHz
Unused 48MHzPCH REFCLK 14.31818MHz
Unused BCLK 133MHzPCH BCLK 133MHz
BYPASS=U2790::5 mm
10V 402 CERM0.1UF
C27901 2
68
SC70-5 74HC1G00GWDG
U2790
3 2 1 4 5
PLACE_NEAR=Y2730.1:2 mm:NO_VIA
5%
50V CERM 402
18pF
C27301 2
C27001 2
PLACE_NEAR=L2710.2:2 mm:NO_VIA
20%
6.3V X5R
10UF
C27101 2
16 25
23 22
20 19
3 4
30
32 31
11 10 13 14
PLACE_NEAR=U2700.17:2 mm
0.1UF
402 16V
Clock (CK505)
PCH_CLK14P3M_REFCLK
PCH_CLK96M_DOT_PPCH_CLK96M_DOT_N
PCH_CLK100M_SATA_NPCIE_CLK100M_PCH_PPCIE_CLK100M_PCH_N
MIN_LINE_WIDTH=0.3 mmPP3V3_S0_CK505_F
VOLTAGE=3.3V
VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 mmPP1V05_S0
FSB_CLK133M_PCH_NFSB_CLK133M_PCH_PTP_CK505_CPU1NTP_CK505_USB
CK505_CKPWRGD
CK505_CLK14P3M_XINCK505_CLK14P3M_XOUTSMBUS_PCH_CLKSMBUS_PCH_DATA
CK505_27MHZ_EN_L
TP_CK505_CLK27M_SSCK505_CLK27MPCH_CLK100M_SATA_P
Trang 27OUT
IN
IN
OUT OUT
OUT
IN
NCNC
OUT IN
OUT
OUT
OUT OUT
OUT IN
IN
OUT OUT
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
PCH S0 PWRGD
Caesar II (ENET) 25MHz Crystal
Ethernet WAKE# Isolation
C2810
12pF
50V 402 5%
CERM
C2811
SM-2CRITICAL
MF-LF 402
R28111
2
1/16W 402
05%
R2883
5%
402 MF-LF33
402 50V12pF
C2815
402 CERM12pF
MF-LF0
R2871
402 20%
CERM0.1UF10V
SC70-HF
U2850
3 2 1 4 5
C2820
27pF
402 CERM 5%
1/16W 402
R2820
10M
MF-LF 5%
XDP
1/16W 402 MF-LF 5%
R2889
402 MF-LF
05%
R2888
34 0
5%
MF-LF 402
R2884
0.1UF
402 10V CERM
C28801 2
MC74VHC1G08SC70-HF
U2880
3 2 1
4 5
1/16W 5%
0
R2882
17 93 5%
1/16W 402
402 1/16W
1/16W0
5%
MF-LF 402
R2893
5%
402 1/16W
PCA9557D_RESET_L
XDPPCH_PLTRST_L
MAKE_BASE=TRUEPLT_RST_BUF_L
MAKE_BASE=TRUE
LPC_CLK33M_GMUX_RMAKE_BASE=TRUELPC_CLK33M_GMUX_R
MAKE_BASE=TRUE
BCM5764_CLK25M_XTALI
PP3V3_ENET
LPC_CLK33M_GMUXLPC_CLK33M_LPCPLUS_R
Trang 28A6 A7 A11
A5
DQ33
VDD A10/AP
VDD
VSS
SA1 VTT
VSS
DQS4*
DQS4 VSS
DQ35
VSS CK0*
SA0
VSS DQ58 DQ59 DM7
VSS
DQ57 DQ56
DQ50 DQ51 VSS
DQS6*
DQS6 VSS DQ49 DQ48
DQ43 VSS
DM5 VSS DQ42
SDA SCL VTT
VSS EVENT*
DQ62 VSS
DQ63
DQS7*
DQS7
DQ60 DQ61 VSS
VSS DQ55 DQ54
DM6 VSS
DQ53 VSS DQ52
DQ47 VSS
DQS5 VSS DQ46 DQ41
VSS DQ40 DQ34 VSS DQ32 TEST VDD
VDD S1*
A13 CAS*
WE*
BA0 VDD
VDD CK0 A1 A3 VDD
VDD A8 A9 A12/BC*
VDD BA2 NC VDD CKE0
VSS DQS5*
VSS DQ44 DQ45
DQ39 DQ38 VSS
VSS DM4
VSS
DQ37 DQ36 VREFCA
VDD ODT1 NC
S0*
ODT0
BA1 RAS*
VDD
CK1*
VDD
VDD A0 CK1
A2 VDD A4 VDD
VDD A14 A15
CKE1 VDD
BI IN
BI BI
BI BI
BI BI
IN
BI IN
BI
BI BI
IN
BI BI
BI BI
BI BI
BI BI
DQ16
DM3 DQ26 DQ27
DQ4
DQ31 DQ30 DQS3 DQS3*
DQ29 DQ28 DQ23 DQ22 DM2 DQ21 DQ20 DQ15 DQ14 RESET*
DM1 DQ13 DQ12 DQ7 DQ6 DQS0 DQS0*
DQ5
DQ24 DQ25
DQ19 DQ18 DQS2 DQS2*
DQ17 DQ11 DQ10 DQS1 DQS1*
DQ8 DQ9
DM0
DQ0 DQ1 VREFDQ
DQ3 DQ2 VSS VSS
BI BI
BI
BI BI
BI
BI BI
BI BI
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
IN
BI BI
IN
BI BI
IN
BI BI
BI BI
BI
BI BI
BI BI
BI
IN
BI BI
BI BI
BI BI
BI BI
OUT BI IN
IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI
IN BI
BI BI
BI BI
BI BI
BI BI
IN
BI BI
BI BI
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
BOM options provided by this page:
107
84 83
119
80 78
96 95
92 91
90 86
89 85
109
108 79
115
101 103
102 104
141 143
130 132
140 142
147 149
157 159
146 148
158 160
163 165
175 177
164 166
174 176
181 183
191 193
180 182
192 194
137 135
154 152
171 169
188 186
198
77
122 116
144 145
150 151
172 173
178 179
184 185
C29311
2 2.2UF 20%
402-LF CERM
C29301
33 35
22 24
34 36
39 41
51 53
15
40 42
50 52
57 59
67 69
56 58 17
68 70
4 6
16 18
21 23
12 10
29 27
47 45
64 62
54 55
8
60 61
C29361
2 CERM 2.2UF 6.3V 20%
402-LF
C29351
10K
R29411
2 402
5%
1/16W 10K
R29401
2 6.3V
402-LF CERM 20%
2.2UF
C29401
2
603 6.3V X5R
C2914
1
402 20%
C2920
1
402 20%
Trang 29II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
CPU CHANNEL B DQS 6 -> DIMM B DQS 6 CPU CHANNEL A DQS 5 -> DIMM A DQS 5
CPU CHANNEL A DQS 2 -> DIMM A DQS 2
CPU CHANNEL A DQS 3 -> DIMM A DQS 3
CPU CHANNEL A DQS 6 -> DIMM A DQS 6
CPU CHANNEL A DQS 7 -> DIMM A DQS 7
CPU CHANNEL A DQS 4 -> DIMM A DQS 4
CPU CHANNEL A DQS 1 -> DIMM A DQS 1
CPU CHANNEL B DQS 7 -> DIMM B DQS 7
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
CPU CHANNEL B DQS 1 -> DIMM B DQS 1
CPU CHANNEL B DQS 2 -> DIMM B DQS 2 CPU CHANNEL A DQS 0 -> DIMM A DQS 0
CPU CHANNEL B DQS 5 -> DIMM B DQS 5 CPU CHANNEL B DQS 4 -> DIMM B DQS 4 CPU CHANNEL B DQS 3 -> DIMM B DQS 3
SYNC_DATE=MASTERSYNC_MASTER=MASTER
DDR3 Byte/Bit Swaps
=MEM_A_DQ<20>
=MEM_A_DQ<22>
MAKE_BASE=TRUEMEM_B_DQ<16>
MAKE_BASE=TRUEMEM_B_DQ<29>
MAKE_BASE=TRUEMEM_B_DM<4>
MAKE_BASE=TRUEMEM_B_DQ<24>
MAKE_BASE=TRUEMEM_B_DQS_N<3>
MEM_B_DQS_N<0>
MAKE_BASE=TRUEMEM_B_DQS_P<0>
MAKE_BASE=TRUEMEM_B_DM<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<23>
MAKE_BASE=TRUEMEM_B_DQ<22>
MEM_B_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<19>
MEM_B_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<12>
MEM_B_DQ<9>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQS_N<2>
MAKE_BASE=TRUEMEM_B_DQ<15>
MEM_B_DM<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQS_P<2>
MEM_B_DM<2>
MAKE_BASE=TRUE
=MEM_B_DQ<18>
MAKE_BASE=TRUEMEM_B_DQ<21>
MAKE_BASE=TRUEMEM_B_DQ<20>
=MEM_B_DQS_P<2>
MAKE_BASE=TRUEMEM_B_DQ<14>
MAKE_BASE=TRUEMEM_B_DQ<1>
MAKE_BASE=TRUEMEM_B_DQS_N<1>
=MEM_B_DM<1>
=MEM_B_DM<2>
MEM_B_DQ<4>
MAKE_BASE=TRUEMEM_B_DQ<3>
MAKE_BASE=TRUEMEM_B_DQ<2>
MAKE_BASE=TRUEMEM_B_DQ<6>
MAKE_BASE=TRUEMEM_B_DQ<58>
MAKE_BASE=TRUEMEM_B_DQ<57> =MEM_B_DQ<60>
MAKE_BASE=TRUEMEM_B_DQ<59> =MEM_B_DQ<59>
MAKE_BASE=TRUEMEM_B_DQ<61> =MEM_B_DQ<57>
MAKE_BASE=TRUEMEM_B_DQ<60> =MEM_B_DQ<56>
MAKE_BASE=TRUEMEM_B_DQ<63> MAKE_BASE=TRUE =MEM_B_DQ<63>
MAKE_BASE=TRUEMEM_B_DQ<62> =MEM_B_DQ<62>
MAKE_BASE=TRUEMEM_B_DQS_N<7> =MEM_B_DQS_N<7>
MAKE_BASE=TRUEMEM_B_DQS_P<7> =MEM_B_DQS_P<7>
MAKE_BASE=TRUEMEM_B_DQ<48> MAKE_BASE=TRUEMEM_B_DQ<49> MAKE_BASE=TRUE =MEM_B_DQ<48>
MEM_B_DQ<50> MAKE_BASE=TRUE =MEM_B_DQ<51>
MEM_B_DQ<51> MAKE_BASE=TRUE =MEM_B_DQ<49>
MEM_B_DQ<52> MAKE_BASE=TRUE =MEM_B_DQ<53>
MEM_B_DQ<53> MAKE_BASE=TRUEMEM_B_DQ<54> =MEM_B_DQ<55>
=MEM_B_DM<6>
MAKE_BASE=TRUEMEM_B_DQ<55> =MEM_B_DQ<50>
MAKE_BASE=TRUEMEM_B_DQS_P<6> =MEM_B_DQS_P<6>
MAKE_BASE=TRUEMEM_B_DQ<43>
MEM_B_DQ<44>
MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_B_DQ<46>
MAKE_BASE=TRUE
=MEM_B_DQ<47>
MAKE_BASE=TRUEMEM_B_DQS_P<5> =MEM_B_DQS_P<5>
=MEM_B_DQS_N<5>
MAKE_BASE=TRUEMEM_B_DQ<32> MAKE_BASE=TRUE =MEM_B_DQ<36>
MEM_B_DQ<33>
MAKE_BASE=TRUEMEM_B_DQ<36> =MEM_B_DQ<32>
MAKE_BASE=TRUEMEM_B_DQ<35>
MAKE_BASE=TRUEMEM_B_DQ<34>
MAKE_BASE=TRUEMEM_B_DQS_N<4> =MEM_B_DQS_N<4>
MAKE_BASE=TRUEMEM_B_DQ<25>
=MEM_B_DQ<25>
MAKE_BASE=TRUEMEM_B_DQ<27>
=MEM_B_DQ<30>
MAKE_BASE=TRUEMEM_B_DQ<26>
MAKE_BASE=TRUEMEM_A_DQS_N<0>
MEM_A_DQ<5>
MAKE_BASE=TRUE
MEM_A_DQ<6>
MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_A_DQ<7>
MEM_A_DQ<2>
MAKE_BASE=TRUE
MEM_A_DQ<14>
MAKE_BASE=TRUEMEM_A_DQ<13>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<8>
MEM_A_DQS_P<5>
MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_A_DQS_N<5>
MEM_A_DQ<33>
MAKE_BASE=TRUEMEM_A_DQ<32>
MAKE_BASE=TRUE
MEM_A_DQS_P<4>
MAKE_BASE=TRUEMEM_A_DM<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<49>
MAKE_BASE=TRUEMEM_A_DQ<51>
MEM_A_DQ<50>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<54>
MAKE_BASE=TRUEMEM_A_DQ<52>
MEM_A_DQ<55>
MAKE_BASE=TRUE MAKE_BASE=TRUEMEM_A_DM<6>
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<40>
MAKE_BASE=TRUEMEM_A_DQ<63>
MEM_A_DQ<59>
MAKE_BASE=TRUEMEM_A_DQ<58>
MAKE_BASE=TRUEMEM_A_DQ<56>
MEM_A_DQ<62>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQS_P<7>
MEM_A_DQ<53>
MAKE_BASE=TRUE
MEM_A_DQS_N<0>
MAKE_BASE=TRUEMEM_B_DQ<28>
MEM_A_DQS_P<2>
MAKE_BASE=TRUEMEM_A_DM<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<22>
=MEM_B_DM<4>
=MEM_B_DQ<29>
MAKE_BASE=TRUEMEM_B_DQ<30>
MAKE_BASE=TRUEMEM_A_DQ<43>
MEM_A_DQ<25>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<45>
MAKE_BASE=TRUEMEM_B_DQ<13>
MAKE_BASE=TRUEMEM_B_DQ<5>
MEM_A_DQ<39>
MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<24>
Trang 30BI
BI BI
OUT BI IN
IN
IN
IN IN
IN IN
IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI
IN
BI BI
BI BI
BI BI
BI BI
IN
BI BI
BI BI
BI BI
VDD A12/BC*
VSS
DQ42 DQ43
DQ48 DQ49 VSS
VSS DQ41 DQS4*
DM5
VDD CKE1
A15 A14 VDD A11 A7 A6 VDD
A4 A2
CK1
A0 VDD
VDD CK1*
VDD RAS*
BA1
ODT0 S0*
NC ODT1 VDD
VREFCA VDD
DQ36 DQ37 VSS
DM4 VSS
VSS DQ38 DQ39
DQ45 DQ44 VSS
DQS5*
VSS
CKE0 VDD NC BA2
CK0
VDD BA0
WE*
A13 S1*
VDD
VDD TEST
DQ33 DQ32
VSS
DQ34
DQ40 VSS
DQ46 VSS DQS5
VSS DQ47
DQ52 VSS DQ53
VSS DM6 DQ54 DQ55 VSS
VSS DQ61 DQ60
DQS7 DQS7*
DQ63
VSS DQ62
EVENT*
VSS
VTT SCL SDA
VSS
DQS6 DQS6*
VSS
DQ51 DQ50
A10/AP VDD CK0*
DQ35 VSS DQS4 VSS CAS*
VDD
DM7 VSS DQ56
DQ58 VSS
DQ59 VSS VDDSPD
BI BI
BI BI
IN
BI IN
BI
BI
BI BI
IN
BI BI
BI BI
BI BI
BI
BI
BI
DQ2 DQ3
VREFDQ
DQ1 DQ0
DM0
DQ9 DQ8
DQS1*
DQS1 DQ10 DQ11
DQ17
DQS2*
DQS2
DQ18 DQ19
DQ25 DQ24
DQ5
DQS0*
DQS0
DQ6 DQ7 DQ12 DQ13 DM1 RESET*
DQ14 DQ15 DQ20 DQ21
DM2
DQ22 DQ23 DQ28 DQ29 DQS3*
DQS3 DQ30 DQ31 DQ4
DQ27 DQ26 DM3
DQ16
VSS
VSS VSS VSS VSS VSS
VSS VSS
VSS VSS
KEY
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS
VSS
IN
BI BI
BI BI
BI
BI
BI BI
BI
BI BI
BI BI
IN IN
IN
BI
IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
IN
BI BI
IN
BI BI
IN
BI
BI BI
BI BI
BI BI
BI BI
BI IN
BI
BI BI
"Expansion" (bottom) slot
Signal aliases required by this page:
C31311
2.2UF
C31301
2
5%
MF-LF 402 10K 1/16WR31411
2 MF-LF
402 5%
10K
R31401
2 2.2UF 6.3V 402-LF CERM 20%
C31401
2
603 6.3V X5R
0.1UF
CERM 10V
C3115
1
402 20%
C3120
1
402 20%
107
84 83
119
80 78
96 95
92 91
90 86
89 85
109
108 79
115
101 103
102 104
141 143
130 132
140 142
147 149
157 159
146 148
158 160
163 165
175 177
164 166
174 176
181 183
191 193
180 182
192 194
137 135
154 152
171 169
188 186
198
77
122 116
144 145
150 151
172 173
178 179
184 185
33 35
22 24
34 36
39 41
51 53
15
40 42
50 52
57 59
67 69
56 58 17
68 70
4 6
16 18
21 23
12 10
29 27
47 45
64 62
54 55
8
60 61
C31361
2 2.2UF 6.3V 20%
402-LF
C31351
Trang 31IN IN
IN OUT
OUT
D
S G
D
D
S G
D
D
S G
OUT IN
IN
D
S G
D
S G
IN
G D
S
OUT
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
1V5 S0 "PGOOD" for CPU
MEMVTT Clamp
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
75mA max load @ 0.75V
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition Rails will power-up as if from S3, but MEM_RESET_L will not properly assert Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
402 MF-LF
SOT563
Q3210
3
5 4
402 MF-LF
402 MF-LFCPUMEM_S0
CPUMEM_S0
R32501
2
MF-LF 5%
33.2K
402 1/16W
4
MF-LF 5%
0.001UFC32201 2
Trang 32OUT OUT
OUT
V+
V+
V+
V+
V+
V+
V-IN
RESET*
A0 A1 A2
SCL SDA
P0 P1 P2
P5 P6 P7
P3 P4
THRM
VCC
GND PAD
NC
NC
IN BI
VDD
VOUTD VOUTC VOUTB VOUTA SCL
SDA A0 A1 GND
IN BI
REVISION
D
R PAGE TITLE
6 D GPU Frame Buffer (1.8V, 70% VRef)
0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)
A
MEM B VREF DQ
0.300V - 1.200V (+/- 450mV)
C 3 MEM A VREF CA
4 C
Power aliases required by this page:
BOM options provided by this page:
VREFMRGN - Stuffs VREF Margining
VREFMRGN_NOT - Bypasses VREF Margining
Signal aliases required by this page:
10mA max load
Required zero ohm resistors when no VREF margining circuit stuffed
RST* on ’platform reset’ so that systemwatchdog will disable margining
NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles
Addr=0x30(WR)/0x31(RD)
both at the same time!
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
(OD)Addr=0x98(WR)/0x99(RD)
8 77 VREFMRGN
402 MF-LF
C33021 2
22.6KVREFMRGN
402 MF-LF PLACE_NEAR=R7320.2:1mm
R3314
402 MF-LF 5%
402 MF-LF
U3302
C3
C2
C1 C4 B1
B4
VREFMRGN
UCSPMAX4253U3303
A3
A2
A1 A4 B1
B4
MAX4253UCSP
B4
UCSPMAX4253
B4
VREFMRGN
UCSPMAX4253U3304
A3
A2
A1 A4 B1
B4
VREFMRGN
UCSPMAX4253U3304
C3
C2
C1 C4 B1
B4
PLACE_NEAR=J2900.126:2.54mm
402 MF-LF200
VREFMRGN
R3309
PLACE_NEAR=J3100.126:2.54mm200
MF-LF 402 1%
OMIT
R3318
NONE 402 NONE
SHORTNONE
1/16W PLACE_NEAR=J3100.1:2.54mm
R3305
133
PLACE_NEAR=R3305.2:1mmVREFMRGN
MF-LF 402
R3306
5%
1/16W 402
MF-LF 402 1%
1/16W
R3310
402 MF-LF 5%
VREFMRGNCRITICAL
U3301
3 4 5
6 7 9 10 11 12 13 14 15
1 2
VREFMRGN
0.1UFCERM 402 20%
C33041 2
133
MF-LF 402 1%
3
6 7
8 1 2 4 5
VREFMRGN
0.1UF
CERM 402 10V
C33051 2
VREFMRGN
402 CERM 20%
0.1UF
C33031 2
FSB/DDR3/FRAMEBUF Vref Margining
VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mmPP3V3_S3_VREFMRGN_CTRL
SMBUS_PCH_CLKSMBUS_PCH_DATA
SMBUS_PCH_CLKSMBUS_PCH_DATA
VREFMRGN_SODIMMB_DQ
MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75VPP0V75_S3_MEM_VREFDQ_A
MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MIN_LINE_WIDTH=0.3 mmPP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_AMIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75VPPVTTDDR_S3
PP0V75_S3_MEM_VREFCA_BMIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V
DDRREG_FB
GPU_FB_A_VREF_DIV
GPU_FB_B_VREF_DIVVREFMRGN_FRAMEBUF_BUF
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN_DQ_SODIMMB_BUF
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN_CA_SODIMMB_BUFVREFMRGN_FRAMEBUF_EN
VREFMRGN_SODIMMA_DQ
VREFMRGN_MEMVREG_FBVREF
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_SODIMMS_CAPP3V3_S3
VREFMRGN_MEMVREG_BUFVREFMRGN_CA_SODIMMB_EN
Trang 33BI
IN BI
D
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
3V S3 WLAN FET
TPCP8102 P-TYPE 20-30 MOHM @2.5V
402 CERM 20%
33 73 MF-LF
2
TPCP8102
23V1K-SM
CRITICALQ3450
X5R
0.1UFC3450
10V 805
R3455
10V 402
0.1uF
CERM PLACEMENT_NOTE=Place close to J3401.
5%
402 110K 1/16WR34531
5%
62K 1/16W 402NOSTUFFR34541
2 10%
U3401
2
1 3
5 4
SSM6N15FEAPE SOT563Q34016
2 1
L340612
6 18 27
F-ST-SM500913-0302
CRITICAL
J3401
1
101112131415161718192
202122232425262728293
30
3132
3334
456789
SOT563 SSM6N15FEAPE
Q3401
3
5 4
16V 402 10%
CERM
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
0.01UFC3432
12
XW3452
SYNC_DATE=06/15/2009SYNC_MASTER=K18_COMMS
X16/ALS/CAMERA CONNECTOR
MIN_NECK_WIDTH=0.2 mmPP5V_S3_ALSCAMERA_F
SMBUS_SMC_A_S3_SCLSMBUS_SMC_A_S3_SDA
USB_CAMERA_CONN_NUSB_CAMERA_CONN_P
PP3V3_S3
PCIE_CLK100M_AP_CONN_NPCIE_CLK100M_AP_CONN_P
Trang 34CARD_DETECT_SW CARD_DETECT_GND
DAT6 DAT7
DAT1
CD/DAT3 DAT2
DAT4 DAT5
VSS VSS CLK CMD DAT0
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
BI BI
D4 D2
SD_WP SD_CMD PDMOD
MS_BS
GND
NCNCNCNCNC
NCNCNCNCNCNCNC
D
S G
D
S G
B
(IPD)
(IPD) (IPU) (IPD) (IPD) (IPD) (IPU)
(IPU)
(IPU) (IPU) (IPD) (IPD)
NC = DISABLE (DEFAULT)
Keep this net short!
10K LOW = POWER SAVING MODE ENABLE10K HIGH = REMOTE WAKE UP ENABLEPDMOD: POWER DOWN MODES
R3553
1/16W 5%
0
402BCM57765
R3555
603 1/10W5%
MF-LF
0BCM57765
2
1
R3502
402 MF-LF 5%
0GL137
2 1
R3554
MF-LF
BCM577650
1/16W
16
6 3
4
20 19 18 17
13 12 11 10 9 8 7 2 5
1
14 15
10UFGL137
2
1C3501
20%
CERM 402
10V
BYPASS=U3500.15:16:5 mm
0.1UFGL137
2 1
1
C3506
10V0.1UF
CERM 20%
603 CERM1 6.3V
2
1C3508
0.1UF
402 CERM 20%
10V
BYPASS=U3500.11:12:5 mmGL137
2
1C3502
10V0.1UF
402 CERM 20%
BYPASS=U3500.26:27:5 mmGL137
2
1C3503
10V0.1UF
402 CERM 20%
BYPASS=U3500.35:34:5 mmGL137
0.1UF
BYPASS=U3500.6:5:5 mmGL137
C3511
50V33PF
402 CERM 5%
GL137
2 1
Y3500
CRITICAL
8X4.5X1.4-SM
12.000M-100PPMGL137
2 1
C3512
5%
CERM 402
33PF
50VGL137
45
42
44 31
1 14
23 10
2
24 33
46 47 48
22
38 32 30 28 29 37 43 40
402 CERM 20%
715GL137
2
1
R3507
402 MF-LF 5%
10KGL137
GL137
2 1
2 1
R3504
0
1/16W 5%
402-1 CERM 5%
4 5
3
Q3500
SOT563
SSM6N15FEAPEGL137
1 2
R3550
MF-LF 1/16W 5%
0BCM57765
402
2 1
VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM
SD_CD_L
MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
PP3V3_S3_CARDREADER_AVDDMIN_LINE_WIDTH=0.40MM
MIN_LINE_WIDTH=0.30 MM VOLTAGE=3.3V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.20 MMPP3V3_SW_SD_PWR
SD_D<0>
USB_SDCARD_P
GL137_CLK12M_X2GL137_RREFGL137_CLK12M_X1
SD_CD_LMAKE_BASE=TRUE
SD_CMDMAKE_BASE=TRUE
GL137_GPIO1
SDCARD_PLT_RST
SDCARD_PLT_RST_LSDCARD_RESET
SD_WPMAKE_BASE=TRUE
GL137_TESTMODGL137_RESET_LGL137_GPIO2
SD_CLKSDCONN_CLK
Trang 35G D
S G
RESET*
XTAL1/CLKIN XTAL2 SUSP_IND/LOCAL_PWR/NON_REM0
USBDN1_DM/PRT_DIS_M1 USBDN1_DP/PRT_DIS_P1 USBDN2_DM/PRT_DIS_M2
PRTPWR2 PRTPWR3
VBUS_DET RBIAS
OCS3*
OCS4*
SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 USBDN4_DP/PRT_DIS_P4 TEST
SCL/SMBCLK/CFG_SEL0
USBDN3_DP/PRT_DIS_P3 USBDN3_DM/PRT_DOS_M3 USBDN2_DP/PRT_DIS_P2 VDDA33
BI BI BI
BI BI
BI BI BI BI BI
IN
SCL GND
VCC
IN IN
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
TABLE_5_HEAD
TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM
0 0 All ports are removable
1 1 Port 1, 2, and 3 are non removable
1 0 Port 1 and 2 are non removableNON_REM1 NON_REM0 DESCRIPTION
IPUIPU
0 1 SMBUS Slave Config
1 1 EEPROM SupportedSEL1 SEL0 DESCRIPTION
R36411
2
2N7002DW-X-GSOT-363
Q36403
54
402 5%
Q36406
21
CERM50V4025%
NOSTUFF
100PF
C3641
12
402
0.47UF
10%
6.3V CERM-X5R
C3640
1
2
16V0.1UFX5R
C3634
12
10K
5%
1/16W 402
2
CERM40250V5%
1/16W402MF-LF
R3665
1
MF-LF5%
1/16W
10K
NOSTUFFR36941
2
1/16W4025%
CRITICAL
4025%
CERM
C3620
12
6.3V60310UF20%
C3618
12
0.01UF402CERM16V
C3642
12
100PFCERM40250V5%
C3643
12
0.01UF10%
40216VCERM
C3636
12
6.3V
C3644
12
40250V5%
CERM100PF
C3637
12
10K5%
U3600
25
13 17 19 21
12 16 18 20
35
26
24 22 28 11
1 2 3 4 6 7 8 9
30 31 27
402MF-LF5%
X7R-CERM0.1UF
C3624
12
1UFX5R10%
C3627
12
1/16W
10K
MF-LF 402 5%
2
0.1UFX7R-CERM10%
40216V
C3628
12
1UF40216V
C3630
12
0.1UF16VX7R-CERM40210%
C3645
12
6036.3V10UFX5R
C3638
12
0.1UF16V402X7R-CERM10%
C3646
12
402X7R-CERM16V0.1UF
C3647
12
0.1UFX7R-CERM16V402
C3639
12
X7R-CERM16V40210%
0.1UF
C3625
12
402CERM16V0.01UF
C3626
12
40216VCERM
0.01UF10%
C3629
12
19
100K
5%
1/16W 402
HUB1_NONREM0_1
10K5%
1/16W402
USBHUB_2061
TP_USB_HUB1_PRTPWR1USB_HUB1_CFG_SEL1
USB_HUB1_SMBCLKUSB_HUB1_TEST
USB_EXTC_PUSB_EXTC_NUSB_HUB1_SMBDATA
NC_USB_HUB1_OCS4USB_EXTB_OC_L
USB_HUB1_RBIASUSB_HUB1_VBUS_DET
NC_USB_HUB1_PRTPWR3NC_USB_HUB1_PRTPWR2
USB_IR_N
USB_HUB1_LOCAL_PWRUSB_HUB1_XTAL2USB_HUB1_XTAL1
USB_HUB_RESET_L
USB_HUB1_UP_PUSB_HUB1_UP_N
NC_USB_HUB1_OCS2
NC_USB_HUB1_PRTPWR4TP_USB_HUB1_OCS1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM VOLTAGE=3.3VPPUSB_HUB1_VDDPLL3V3
PP3V3_S3
MIN_LINE_WIDTH=0.4MM VOLTAGE=1.8VPPUSB_HUB1_VDD1V8
MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8VPPUSB_HUB1_VDD1V8PLL
USB_CAMERA_NUSB_CAMERA_P
USB_HUB_RESET
P3V3S3_EN_RC
PP3V3_S5PP3V3_S3
Trang 36BI IN
BI
BI BI BI BI BI BI BI BI
IN
SCL GND
RESET*
XTAL1/CLKIN XTAL2 SUSP_IND/LOCAL_PWR/NON_REM0
USBDN1_DM/PRT_DIS_M1 USBDN1_DP/PRT_DIS_P1 USBDN2_DM/PRT_DIS_M2
PRTPWR2 PRTPWR3
VBUS_DET RBIAS
OCS3*
OCS4*
SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 USBDN4_DP/PRT_DIS_P4 TEST
SCL/SMBCLK/CFG_SEL0
USBDN3_DP/PRT_DIS_P3 USBDN3_DM/PRT_DOS_M3 USBDN2_DP/PRT_DIS_P2 VDDA33
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
REVISION
D
R PAGE TITLE
IPUIPU
NON_REM1 NON_REM0 DESCRIPTION
0 1 Port 1 is non removable
1 0 Port 1 and 2 are non removable
1 1 Port 1, 2, and 3 are non removable
0 0 All ports are removable
External A
USB HUB-2
402CERM50V5%
18PF
CRITICAL
C3720
12402
0.1UF
C3734
12
100PF402CERM50V5%
C3737
12
100PF50V5%
402CERM
C3743
12
X7R-CERM
0.1UF10%
40216V
C3739
12
402X7R-CERM16V0.1UF10%
C3745
1
2 16VX7R-CERM
0.1UF40210%
C3746
1
40210%
X7R-CERM0.1UF
C3747
12
0.1UF10%
40216VX7R-CERM
C3725
12X7R-CERM0.1UF40210%
C3723
12
0.1UFX7R-CERM16V402
C3724
12
0.1UF10%
40216VX7R-CERM
C3728
12
CERM10%
4020.01UF
C3736
12
0.01UFCERM16V402
C3742
12
10%
0.01UF402CERM16V
C3729
120.01UF402CERM16V
C3726
12
19 93
35
10UF6.3VX5R20%
C3718
12
NOSTUFF
1/16W10K5%
10K1/16W
NOSTUFFR37941
2
10K
402 MF-LF 5%
10K
R3766
1
21/16W
5%
402
10KMF-LF
SOT23-5
AT24C02BU3714
2 1 3 4
C3730
12X5R
1UF16V40210%
C3727
12
10UF60320%
6.3V
C3738
12
10UF6.3VX5R20%
C3744
12
12K
1/16W 1%
U3700
25
13 17 19 21
12 16 18 20
35
26
24 22 28 11
1 2 3 4 6 7 8 9
30 31 27
SYNC_DATE=10/06/2009 SYNC_MASTER=K23F
PP3V3_S3MIN_LINE_WIDTH=0.4MM
PPUSB_HUB2_VDDPLL3V3
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V
PPUSB_HUB2_VDDA3V3
TP_USB_HUB2_OCS1NC_USB_HUB2_PRTPWR4
NC_USB_HUB2_OCS2
USB_HUB2_UP_NUSB_HUB2_UP_P
USB_HUB_RESET_LUSB_HUB2_XTAL1
USB_HUB2_XTAL2USB_HUB2_LOCAL_PWR
USB_BT_NUSB_BT_PUSB_TPAD_N
NC_USB_HUB2_PRTPWR2NC_USB_HUB2_PRTPWR3
USB_HUB2_VBUS_DETUSB_HUB2_RBIAS
NC_USB_HUB2_OCS3USB_EXTA_OC_L
USB_HUB2_SMBDATA
USB_EXTA_NUSB_EXTA_PUSB_HUB2_TEST
USB_HUB2_SMBCLK
USB_SDCARD_PUSB_SDCARD_NUSB_TPAD_PPP3V3_S3
WP_HUB2PP3V3_S3
Trang 37IN IN
IN OUT OUT
IN
IN OUT
BI BI BI BI BI
NC
BI
BI BI BI BI BI BI BI
OUT
IN IN
RDAC
VDDC UART_MODE SCLK
LOW_PWR LINKLED*
CLKREQ*
PERST*
PCIE_REFCLK_N PCIE_REFCLK_P
PCIE_TXD_P PCIE_RXD_P
ENERGY_DET
DC3 DC4
NC GPIO_2
TRD1_N TRD1_P TRD0_N
TRD2_N TRD2_P TRD3_P
THRM_PAD
XTALI XTALO
SPD100LED*
TRAFFICLED*
TRD3_N
DC5 PCIE_TXD_N
SMB_CLK VDDC
SI
GND VCC
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
D
B
is powered-down in S3/S5 StandardMust isolate from PCIe WAKE# if PHYWAKE#
info as well as code for Bonjour proxy
PHY Non-Volatile Memory
Required for proper PHY operation
ROM contains MAC address, PCIe config
Atmel AT45DB011D (1Mbit) ROM If a different ROM is used then the straps must change
53-VMAIN_PRSNT(IPD)
06-VDDC14-VDDC13-WAKE*
(IPD)
N-channel FET isolation suggested
If PHY is always powered then alias
(OD)(OD)
(IPD)BCM57765 SR pins are internal 1.2V switching regulator
BCM57765 supports both active-levels for WP
All resistors above BOMOPTIONed BCM57765
just decoupling for BCM57765 CR I/Os
CR_BUS_PWR is not for SD Card power,
If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
If unused: Okay to float all 4 pins (Broadcom not so sure now)
(Required ROM size TBD)
All parts below BOMOPTIONed BCM5764M
BCM5764M Support
58-SMB_DATA54-VAUX_PRSNT16-VDDIO
with no stubs
Keep net short,
10%
402 X7R-CERM0.1UF
C39211 2
X5R 6.3V 10%
80510UF
C3935
1
2
6.3V 10%
603 X5R-CERM4.7UF
6.3V 603
4021.24K
0
MF-LFBCM57765
402 1/16W
1K
FERR-600-OHM-0.5APLACE_NEAR=U3900.26:2 mm
C3998
1
2 X7R-CERM 402 PLACE_NEAR=U3900.26:1 mm
BCM5764M
16V0.1UF
C39991 2
402 MF-LF 1/16W 5%
0
0BCM57765
402 1/16W 5%
BCM5764MQFN-8X8
57 60
5 8 9 3
27 28
26 11
38
66 64
59
58
65
68 2
67
41 40
43 44
47 46
49 50
10
54 6
BCM57765
10%
6.3V X5R-CERM 6034.7UF
C39701 20.1UF16V 402 X7R-CERM
C3990
1
2
16V 4020.1UFX7R-CERM
C39001 2
16V 4020.1UFX7R-CERM
C3930
1
2 X7R-CERM 402 10%
0.1UF
C39311 2
6.3V 603 X5R-CERM
C39151
0.1UF
X7R-CERM 10%
402 MF-LF4.7K
C39361 2
4020.1UFX7R-CERM 10%
C39261 2
TP_BCM5764_TRAFFICLED_L
BCM5764_CLK25M_XTALOBCM5764_RDAC
BCM57765_CR_CMD
SDCONN_CLKBCM57765_SD_DETECT
BCM57765_MEDIA_SENSEENET_MDI_P<1>
BCM5764_CS_L
MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3VPP3V3_ENET_PHY_AVDDH
PP3V3_ENET_PHY_BIASVDDH
VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm
PP3V3R1V8_SW_SD_VIO
VOLTAGE=3.3V MIN_LINE_WIDTH=0.3 mmENET_MDI_P<0>
ENET_ENERGY_DET
TP_BCM57765_SR_VDDP
PP1V2_ENET_PHY_AVDDLMIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
PP1V2_ENET_PHY_PCIEPLLMIN_LINE_WIDTH=0.4 mmBCM57765_SR_LX
PP1V2_ENET
PCIE_ENET_D2R_C_P
PCIE_ENET_R2D_NPCIE_CLK100M_ENET_PPCIE_CLK100M_ENET_N
BCM57765_XTALVDDHMIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V
PP3V3_S0
BCM57765_VMAIN_PRSNT
BCM57765_VDDO_PIN20
BCM57765_XTALVDDHBCM57765_CR_DATA<7>
BCM57765_SR_LX
PP3V3_ENET_PHY_XTALVDDHBCM57765_CR_DATA<6>
PP3V3_S0ENET_WAKE_LBCM57765_SR_VFB
Trang 38RX TX
REVISION
D
R PAGE TITLE
B
mirrored on opposite Transformers should be
Place one of 0.1uf cap close to each centertap pin of transformer
Signal aliases required by this page:
Power aliases required by this page:
75
MF-LF4025%
CRITICAL 1000PF
C4008
37
X5R10%
C4004
1
2402
0.1UF
X5R10%
X5R10%
F-RT-TH
J4000
1 10
11 12
2 3 4 5 6 7 8 9
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
Trang 39ATBUSH ATBUSN
VP25
OCR_CTL_V10
VAUX_DETECT
TMS TCK REFCLKN PCIE_TXD0P
AVREG CE
CLKREQN
FW_RESET*
FW620*
JASI_EN MODE_A NAND_TREE
OCR_CTL_V12
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N
SCL SDA SE
SM
TDO TPA1N
TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P TPBIAS0 TPBIAS1 TPBIAS2
DS0
TPA1P
VDD33 VDD10
VREG_VSS VSS
CHIP RESET SCIF
1394 PHY
NCNCNC
NC
IN IN
IN
NCNC
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R
SHEET PAGE TITLE
3 4
5 6
7 8
(Reserved)
NT-5
NT-17 NT-16 (IPD) (OD) NT-4 (IPU)
NT-6 (IPD) NT-18
(IPD) NT-21
135 mA
191
MF-LF 402 1%
6.3V
C4162
1
2470K
402 5%
1/16W
R41621
2
OMITCRITICAL
FW643BGA
U4100
B13 A13 A11
A10 L13
L2
F12 E12 E13
D12
K13 D1 J2 K1
J12 J13
N8 N7 N5 N6
N4 B11
N9 N10
D13
L8
G2 G1 H1 F2
N12 M11 M13
N13
M4 N2 M1 M3
B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4 B7 C3 A2
B10
N1
E1 D2
22PF
CERM 402 5%
1/16W PLACE_NEAR=U4100.B10:2mm
R41601
2
412
MF-LF 402 1%
C41761 2
PLACEMENT_NOTE=Place C4175 close to U4100
0.1UF X5R 40210% 16V
C41751 2
10K
MF-LF 402 5%
6.3V
C41301 21UFCERM 402 10%
6.3V
C41311 2
10%
1UF
CERM 402 6.3V
6.3V
C41321 2
1UF
CERM 402 10%
6.3V
C41351 21UF
CERM 402 10%
6.3V
C41361 2
1UF
CERM 402 10%
6.3V
C41201 21UFCERM 402 10%
6.3V
C41211 21UFCERM 402 10%
6.3V
C41221 21UFCERM 402 10%
6.3V
C41231 21UFCERM 402 10%
6.3V
C41241 2
0.1UF
CERM 402 20%
C41411 2
1UF
CERM 402 10%
R4100
1 114S0557
SYNC_DATE=05/29/2009SYNC_MASTER=K19_MLB
FireWire LLC/PHY (FW643)
FW643_TPCPS
PP1V0_FW_RMIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MIN_LINE_WIDTH=0.4 MMPP1V0_FW_FWPHY
FW643_R0NC_FW2_TPBN
NC_FW643_AVREGTP_FW643_FW620_L
TP_FW643_SCIFCLK
TP_FW643_SM
TP_FW643_VBUF
FW_PORT1_TPA_PFW_PORT1_TPA_N
NC_FW2_TPANNC_FW2_TPAPNC_FW0_TPBN
FW_PORT1_TPB_NFW_PORT1_TPB_P
NC_FW2_TPBPNC_FW0_TPBIAS
NC_FW2_TPBIAS
FW_CLK24P576M_XO_RFW643_REXT
FWPHY_DS2FWPHY_DS0
PP3V3_FW_FWPHYFWPHY_DS1
FW_P1_TPBIASNC_FW0_TPBP
PP3V3_FW_FWPHY_VP25
VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 MM
NC_FW0_TPAPNC_FW0_TPAN
VOLTAGE=1.0V MIN_NECK_WIDTH=0.2 MMPP1V0_FW_FWPHY_AVDD
TP_FW643_SETP_FW643_NAND_TREE
TP_FW643_TDO
PCIE_FW_D2R_C_NPCIE_FW_D2R_C_P
PCIE_CLK100M_FW_NPCIE_CLK100M_FW_P
TP_FW643_TCK
TP_FW643_JASI_ENTP_FW643_CETP_FW643_MODE_A
FW643_SCLTP_FW643_SCIFDAINFW_CLKREQ_PHY_L
Trang 40S G
G D
S
G D
S
OUT
VCC
VCLMP D1-
GND D2- D2+
D1+
FWPWR_EN
BI BI BI BI
OUT
IN
S G D (SYM-VER2)
G
S (SYM-VER1) D
GND VOUT
ON VIN
GND VOUT
ON VIN IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
BRANCH REVISION
D
R PAGE TITLE
B
Signal aliases required by this page:
BOM options provided by this page:
PP1V05_FW PGOOD/FW_RESET_L
3.3V FW FETI(max) = 1.7A (85C)
FireWire Port Power Switch
- =PP3V3_FW_LATEVG_ACTIVE
(NONE)
- =PPBUS_S5_FWPWRSW (system supply for bus power)
Late-VG Protection
- =PPVP_FW_SUMNODE (power passthru summation node)
Power aliases required by this page:
4 1 2 3
0.1UF
10%
402
C42601 2
CRITICAL
Q4270
2 6
1
CRITICAL
BC847CDXV6TXG SOT563
Q4270
5 3
4
MF-LF 5%
402 1/16W
402 MF-LF
1UF
6.3V
C42811 2
4
402 MF-LF 1%
5 6
16V 402
402 MF-LF 5%
C2
A2 B2
A1 B1
CSP
TPS22924
CRITICALU4202
C2
A2 B2
A1 B1
20
CERM 10%
1UF
6.3V 402
C42021 2
CERM 10%
1UF
6.3V 402
C42011 2
SYNC_DATE=05/29/2009SYNC_MASTER=K19_MLB
FireWire Port Power
PP1V05_S0FW_PLUG_DET_L
FW_PORT1_TPA_PFW_PORT1_TPB_N
FW_PWR_EN_L
FW_PORT1_TPA_NFW_PORT1_TPB_P
FW_P1_TPBIAS
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
PPBUS_FW_FWPWRSW_D
MIN_LINE_WIDTH=0.5 mm
PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
FW_DET_MIRRORPP1V05_S0
FW_PLUG_DET
FW_PLUG_DET_L
PPVP_FWPPBUS_G3H
FW643_WAKE_L
PP1V0_FW_FWPHY
P1V0_FW_RC
FW_WAKEPP3V3_FW_FWPHY