apple macbook pro a1286 late 2008 early 2009 laptop logic board schematic diagram

NONESCALE II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART I TO MAINTAIN THE DOCUMENT IN CONFIDENCE NOTICE OF PROPRIETARY PROPERTY DRAWING NUMBER SHT OF SIZE D

Trang 1

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_HEAD

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERSXX

X.XXX.XXX

DO NOT SCALE DRAWING

REV ZONE ECN

CKAPPDDATE

ENGAPPDDATE

1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%

2 ALL CAPACITANCE VALUES ARE IN MICROFARADS

3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ

LPC+SPI Debug Connector

07/01/200851

SMC Support

06/18/200850

SMC

06/18/200849

Front Flex Support

07/01/200848

External USB Connectors

07/02/200846

SATA Connectors

07/01/200845

FireWire Ports

08/14/200843

FireWire Port Power

08/14/200842

FireWire LLC/PHY (FW643)

08/14/200841

Ethernet Connector

07/01/200839

Ethernet & AirPort Support

07/01/200838

Ethernet PHY (RTL8211CL)

07/01/200837

ExpressCard Connector

07/02/200835

Right Clutch Connector

07/02/200834

DDR3 Support

06/18/200833

DDR3 SO-DIMM Connector B

07/22/200832

DDR3 SO-DIMM Connector A

07/22/200831

FSB/DDR3/FRAMEBUF Vref Margining

07/22/200829

SB Misc

12/17/200728

MCP Graphics Support

06/18/200826

MCP Standard Decoupling

06/18/200825

MCP79 A01 Silicon Support

03/31/200824

MCP Power & Ground

06/18/200822

MCP HDA & MISC

06/18/200821

MCP SATA & USB

06/18/200820

MCP PCI & LPC

06/18/200819

MCP Ethernet & Graphics

06/18/200818

MCP PCIe Interfaces

06/18/200817

MCP Memory Misc

06/18/200816

MCP Memory Interface

06/18/200815

MCP CPU Interface

06/18/200814

eXtended Debug Port(MiniXDP)

01/08/200813

CPU Decoupling & VID

10/17/200712

CPU Power & Ground

10/17/200711

CPU FSB

10/17/200710

Signal Aliases

(MASTER)9

Power Aliases

(MASTER)8

Functional / ICT Test

N/A7

JTAG Scan Chain

07/22/20086

BOM Configuration

N/A5

Power Block Diagram

N/A4

Power Block Diagram

12/12/20073

System Block Diagram

12/12/20072

Trang 2

APPLE INC.

NONESCALE

FSB64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

PG 28 J3400 U3900

PG 54

PG 53 U6200

PG 40

HD

E-NET

ODD Conn

PG 40

KEYBOARD TRACKPAD/

800/1067/1333 MHz

DDR2-800MHZDDR3-1067/1333MHZ

SMC

B,0

PrtBSB

PWR

Misc

PG 14

Port80,serial LPC Conn

RGMII

PG 18

AirPort Mini PCI-E

SYNC_MASTER=T18_MLB

Trang 3

APPLE INC.

NONESCALE

PWR_BUTTON(P90)

PM_PWRBTN_LSMC_ONOFF_L

RSMRST_PWRGD

MCP_PS_PWRGD

PWROKCPUPWRGD(GPIO49)

PLT_RST_L

CK_PWRGD

PP5V_S0_FET

(25A MAX CURRENT)

(5A MAX CURRENT)

PM_SLP_S3_DELAY_L SMC_ADAPTER_EN

U7000 ISL6258A BATTERY CHARGER PBUS SUPPLY/

(PAGE 60)

PM_SLP_S5_LPM_SLP_S4_LPM_SLP_S3_L

U4900

SLP_S3_L(P93)SLP_S4_L(P94)SLP_S5_L(P95)

(PAGE 68) LTC2900

P1V8S0_PGOOD CPUVTTS0_PGOOD MCPCORES0_PGOOD P5VRIGHT_PGOOD P1V05S0_PGOOD

P5VS0_SS Q7900

PP5V_RT_REG MCPCPCORE_S0_REG

(PAGE 65)

ISL6236U7500

1.1V MCP_CORE

P1V05S0_EN MCPCORES0_EN

MCPCORES0_EN CPUVTTS0_EN MCPDDR_EN P1V8S0_EN

P5VRIGHT_EN

P5VS0_EN PM_SLP_S3_L

Q3800 WOL_EN

PM_ENET_EN_L

DDRVTT_EN DDRREG_EN

U7300 (PAGE 63) TPS51116

0.9V 1.8V

PP3V3_S5_REG(5.5A MAX CURRENT)

PP5V_S5_REG(8A MAX CURRENT)

(PAGE 66) U7750 ISL8009

CPUVTTS0_PGOOD

PPCPUVTT_S0_REG CPUVTTS0_EN

PGOOD

(PAG 66) U7600 TPS51117

VOUT

PP3V42_G3H_REG (PAGE 59)

U6990 LT3470

3.425V G3HOT

GPU VCORE

U8900 ISL6263B

ISL9504B CPU VCORE

(PAGE 62) U7201 TPS51125 3.3V

5V

(PAGE 82) U9500 TPS51124 1.8V(R/H) 1.103V(L/H)

VIN

U7400 SC417 (PAGE 64)

(PAGE 84) U9701

MCP79

(S0) PBUSVSENS_EN

LIO_S3_EN P5VS3_EN P3V3S3_EN (9 TO 12.6V)

PP3V3_S5PP5V_S3

(S5) CHGR_EN

1.05VEN_PSV

(PAGE 43)

CPU_PWRGD

(6A MAX CURRENT)

M98 POWER SYSTEM ARCHITECTURE

SYNC_MASTER=T18_MLB

051-7546

96A.0.0

SYNC_DATE=12/12/2007

3

Power Block Diagram

Trang 4

APPLE INC.

NONESCALE

Power Block Diagram

Trang 5

BOM OPTIONS BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEMPART NUMBER

QTY

APPLE INC

NONESCALE

TABLE_BOMGROUP_ITEM

BOM OPTIONS BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

BOM OPTIONS BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

CRITICAL 1

338S0523 IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12

335S0384 IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA U8400,U8450,U8500,U8550 VRAM_256_SAMSUNG

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA CRITICAL VRAM_512_QIMONDA

4

138S0603 138S0602 ALL Murata alt to Samsung

U8400,U8450,U8500,U8550IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA CRITICAL VRAM_512_SAMSUNG

U8400,U8450,U8500,U8550

ALL353S1294 LMV2011,OPAMP GBW

353S1681

ALL514-0608 FOXLINK RCVR ALT TO FOXCONN

514-0613

ALL157S0055 Delta alt to TDK Magnetics

157S0058

ALL514-0607

514-0612 FOXLINK XCVR ALT TO FOXCONN

152S0915 Maglayers alt to Cyntec IND

ALL341S2366

353S1466 ALL INTERSIL ALT TO INTERSIL

353S2312

ALL152S0876 152S0867 Maglayer alt to Delta

ALL152S0276 152S0683 Maglayers alt to Dale/Vishay

Trang 6

OUT

GND

VCC

NCNC

YA

INININ

OUT

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D TDO

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

From XDP connector

or via level translator

GPU

U9200 GMUX

U8000

MCP U1400

CPU

To XDP connector and/or level translator

XDP connector

TMS TCK TDI GMUX CPLD Programming Port

0.1UF

JTAG_ALLDEV

20%

CERM402

0

1/16W5%

MF-LF402

SYNC_MASTER=DDR SYNC_DATE=07/22/2008

JTAG Scan Chain

=PP1V05_S0_CPU

MAKE_BASE=TRUE JTAG_MCP_TRST_L XDP_TCK

XDP_TDO

JTAG_GMUX_TCK

GPU_JTAG_TRST_L GPU_JTAG_TMS

XDP_TCK XDP_TDI

345

10987

C0602

12

Trang 7

APPLE INC.

NONESCALE

ICT Test Points

I600

I602 I603 I604 I605 I606 I607 I608 I609 I610 I611 I612 I613

I614 I615 I616 I617 I618 I619

I620 I621 I622 I623 I624 I625

I626 I627

I636 I637 I638 I639

I715 I716 I717 I718 I719 I720 I721 I722 I723 I724 I725 I726 I727

I728 I729 I730 I731 I732 I733 I734 I735 I736 I737

I739 I740 I741 I742 I743 I744 I745 I746 I747 I748 I749 I750 I751

I752 I753 I754 I755 I756

I757 I758 I759

I760 I761 I762

I763 I764

I765

7 96

A.0.0051-7546

Functional / ICT TestSYNC_MASTER=N/A SYNC_DATE=N/A

PP3V3_S5_AVREF_SMC

TRUE

PP3V3_S3_LDO TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP0V9R0V75_S0_DDRVTTTRUE

TRUE PPCPUFSB_ISNS_RPPCPUVTT_S0TRUE

PP1V2R1V05_S5TRUE

TRUE

PM_SLP_S3_LTRUE

TRUE LED_RETURN_1

TRUE LVDS_CONN_A_DATA_P<0>

LVDS_DDC_DATATRUE

WS_KBD21 TRUE

WS_KBD_ONOFF_L TRUE

PSOC_SCLK TRUE

Z2_RESET TRUE

Z2_HOST_INTN TRUE

Z2_BOOST_EN TRUE

WS_KBD2 TRUE

SMBUS_SMC_A_S3_SCL TRUE

PP1V8R1V5_S0_FETTRUE

KBDLED_ANODE TRUE

WS_LEFT_SHIFT_KBD TRUE

WS_KBD10 TRUE

WS_KBD18 TRUE

BI_MIC_SHIELD

TRUE

PSOC_MOSI TRUE

PSOC_F_CS_L TRUE

Z2_BOOT_CFG1 TRUE

PP3V42_G3H TRUE

SPKRCONN_S_P_OUT

TRUE

LVDS_DDC_CLKTRUE

BKL_SYNCTRUE

PP3V3_SW_LCDTRUE

=PP3V3_S0_DDC_LCDTRUE

TRUEPP1V0_FW

PP1V1_S0GPU_REGTRUE

TRUE PP1V8R1V5_S3

TRUEPP1V2R1V05_ENET PPVP_FW

TRUETRUEPP3V3_ENET_PHY

PSOC_MISO TRUE

PP18V5_S3 TRUE

SMBUS_MCP_0_CLKTRUE

TRUEPPVCORE_S0_MCPPPVCORE_S0_MCP_REG

TRUETRUE GND

Trang 8

APPLE INC.

NONESCALE

Power AliasesSYNC_MASTER=(MASTER)

051-7546 A.0.0

968

=PPVCORE_S0_CPU_REG

PP1V8_S0

MIN_LINE_WIDTH=0.5 mm VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmMAKE_BASE=TRUEVOLTAGE=1.25VMIN_NECK_WIDTH=0.2 mm

PPVP_FW

MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE VOLTAGE=1.05V

=PP1V5_S3_MEMRESET

MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP3V3_S0

MIN_LINE_WIDTH=0.30MMVOLTAGE=3.3V

PP5V_S0

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20 MM

PPVTTDDR_S3

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE

=PP1V05_S0_CPU

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V MAKE_BASE=TRUE

PP3V3_S0GPU

MIN_NECK_WIDTH=0.20MMVOLTAGE=3.3V

PP1V1_S0GPU_REG

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE VOLTAGE=1.1V

PPDCIN_G3H

MAKE_BASE=TRUEVOLTAGE=3.42V

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mmVOLTAGE=3.3VMAKE_BASE=TRUE

Trang 9

OUT

IN

OUTOUTOUTOUTOUT

APPLE INC

NONESCALE

Bottom Left GPU

Top GPU Right

Left CPU

TM Hole

Right CPU

These need work Add other PRSNT# straps if needed

Bosses for VRAM HS

STDOFF-4.5OD.98H-1.1-3.48-TH

3R2P5

5%

1/16W402MF-LF

47K

5%

1/16W402

SM

1%

MF-LF402

MF-LF

NO STUFF

NO STUFF 220

MF-LF4025%

1/16W

NO STUFF 200

MF-LF5%

402

1%

150

MF-LF402

NO STUFF

1%

4021/16W

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

MIN_NECK_WIDTH=0.09MMMIN_LINE_WIDTH=0.6MMVOLTAGE=0V

GND GND_CHASSIS_CLUTCH

NO_TEST=TRUE MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3_AUDIO_AMP

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

=PEG_R2D_C_P<0 15>

TP_PCIE_CLK100M_PE4P

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

TP_PCIE_PE4_D2RP TP_PE4_CLKREQ_L

ZT0980

ZT0940

1

R09301

2R0925

R0902

1 2

XW0900

12

XW0901

12

ZT0930

R09601

2

R09501

2R09701

2

R09801

Trang 10

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

ININININOUTIN

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BI

BIBIBIBIBIBIBI

BI

BIBIBIBIBIBIBI

BI

OUT

OUTOUT

OUT

IN

INININININ

ININININ

OUT

ININ

INININ

INOUT

BIBIBIBI

THERMTRIP*

THERMDAPROCHOT*

DBR*

TRST*

TMSTDOTDITCKPREQ*

LINT1LINT0STPCLK*

BSEL0BSEL1BSEL2

DPSLP*

DPWR*

PWRGOODSLP*

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS

402MF-LF

54.9

1/16W1%

MF-LF4021/16W5%

68

402

1K

MF-LF1%

1/16W

4021/16W

2.0K

MF-LF1%

402

54.9

1/16W1%

4021%

402

27.4

1/16W1%

MF-LF5%

1/16W

402

54.9

MF-LF1%

MF-LF

54.9

4021%

MF-LF

649

402MF-LF

NOSTUFF 1K

5%

1/16W

40216V

0.1uF NOSTUFF

96

SYNC_MASTER=M87_MLB SYNC_DATE=10/17/2007

XDP_TCK XDP_TDO

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L CPU_IERR_L

FSB_CPURST_L FSB_RS_L<0>

FSB_RS_L<1>

FSB_RS_L<2>

FSB_TRDY_L

FSB_HIT_L FSB_HITM_L XDP_BPM_L<0>

CPU_PROCHOT_L CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

2

R10041

R1030

R10071

R1024

U1000

N3P5P2L2P4P1R1

Y2U5R3W6

A6

U4Y5U1R4T5T3W2W5Y4J4

U2V4W3AA4AB2AA3

L5L4K5M3N2J1

H1

M1

V1

A22A21

E2

AD4AD3AD1AC4

A5

G6E4D20

C4

B3

C6B4

H4

AC2AC1

D21

K3H2K2J3L1

C1F3F4G3

M4N5T2V3B2F6D2D22D3

A3D5

AC5AA6AB3

A24B25C7AB5G2

AB6

U1000

B22B23C21

R26U26AA1Y1

E22F24

J24J23H22F26K22H23

N22K25P26R23E26

L23M24L22M23P25P23P22T24R24L25G22

T25N25

Y22AB24V24V26V23T22U25U23F23

Y25W22Y23W24W25AA23AA24AB25

AE24AD24G25

AA21AB22AB21AC26AD20AE22AF23AC25AE21AD21E25

AC22AD23AF22AC23

E23K24G24

J26

L26

Y26

AE25H26

C23D25C24AF26AF1A26C3

Trang 11

OUTOUT

VCC

VCCP

VCCA

VID0VID1VID2VID3VID4VID5VID6

2500 mA (after VCC stable)

4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM) 16.8 A (Sleep SuperLFM) 41.0 A (HFM)

(CPU CORE POWER)

TBD A (Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Sleep HFM) TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM) TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Sleep HFM) 21.0 A (HFM)

TBD A (Deep Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM) TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Enhanced Deeper Sleep) TBD A (Deeper Sleep)

TBD A (Deep Sleep LFM) TBD A (Deep Sleep HFM) TBD A (Deep Sleep SuperLFM)

1/16W1%

CPU Power & Ground

051-7546 A.0.0

11 96

=PPVCORE_S0_CPU

CPU_VCCSENSE_N CPU_VCCSENSE_P

B9B10B12B14B15B17B18B20C9C10A10

C12C13C15C17C18D9D10D12D14D15A12

D17D18E7E9E10E12E13E15E17E18A13

E20F7F9F10F12F14F15F17F18F20A15

AA7AA9AA10AA12AA13AA15AA17AA18AA20AB9A17

AC10AB10AB12AB14AB15AB17AB18

AB20AB7AC7

A18

AC9AC12AC13AC15AC17AC18AD7AD9AD10AD12A20

AD14AD15AD17AD18AE9AE10AE12AE13AE15AE17B7

AE18AE20AF9AF10AF12AF14AF15AF17AF18AF20

B26C26

G21V6

R21R6T21T6V21W21

J6K6M6J21K21M21N21N6

AF7

AD6AF5AE5AF4AE3AF3AE2

AE7

U1000

A4A8

B11

W1W4W23W26Y3Y6Y21Y24AA2AA5B13

AA8AA11AA14AA16AA19AA22AA25AB1AB4AB8B16

AB11AB13AB16AB19AB23AB26AC3AC6AC8AC11B19

AC14AC16AC19AC21AC24AD2AD5AD8AD11AD13B21

AD16AD19AD22AD25AE1AE4AE8AE11AE14AE16B24

AE19AE23AE26A2AF6AF8AF11AF13AF16AF19C5

AF21A25AF25B1

C8C11C14A11

C16C19C2C22C25D1D4D8D11D13A14

D16D19D23D26E3E6E8E11E14E16A16

E19E21E24F5F8F11F13F16F19F2A19

F22F25G4G1G23G26H3H6H21H24A23

J2J5J22J25K1K4K23K26L3L6AF2

L21L24M2M5M22M25N1N4N23N26B6

P3

P6P21P24R2R5R22R25T1T4

U3U6U21U24V2V5V22V25

Trang 12

APPLE INC.

NONESCALE

VCCP (CPU I/O) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

2.5VD2T20%

470UF

POLY

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL 22UF

X5R-CERM6036.3V20%

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

6.3V20%

22UF

603X5R-CERM

CRITICAL

20%

X5R-CERM603

22UF

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

X5R-CERM60320%

603

CRITICAL 22UF

X5R-CERM60320%

6.3V

20%

0.1UF

CERM40210V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

CRITICAL 22UF

X5R-CERM60320%

6.3V

CRITICAL

X5R-CERM60320%

22UF

6.3V

20%

CERM402

0.1UF

10V 20%

CERM402

0.1UF

10V 20%

0.1UF

CERM40210V 20%

CERM402

0.1UF

10V 20%

CERM402

0.1UF

10V

CRITICAL

X5R-CERM60320%

22UF

6.3V

PLACEMENT_NOTE=Place near CPU pin B26

CERM40216V

0.01UF

X5R6.3V20%

10uF

603

20%

D2T-SM2POLY-TANT2.0V

330UF CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity

CRITICAL 330UF

20%

POLY-TANTD2T-SM2

PLACEMENT_NOTE=Place in CPU center cavity

2.0V

20%

POLY-TANT

CRITICAL 330UF

2.0V

CPU Decoupling & VIDSYNC_MASTER=M87_MLB

9612

C1219 C1218

C1206 C1204

C1216 C1214

C1203 C1202

C1201

C1213 C1212

C1211

C12001

2

C1210

C12361

2

C1215 C1217

C12371

2

C12381

2

C12391

2

C12401

2

C12411

2

C12811

2C128012

Trang 13

BIBI

OUT

IN

BIINININ

OUT

OUTOUT

BIBIBIBI

OUT

IN

ININ

INOUTOUTOUT

OBSFN_C0

OBSDATA_C0 OBSDATA_C1

OBSDATA_C3 Mini-XDP Connector

VCC_OBS_CD DBR#/HOOK7

Please avoid any obstructions

on even-numbered side of J1300

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDO TDI RESET#/HOOK6 OBSFN_D0

SCL SDA

TRSTn HOOK3

HOOK2 HOOK1

Direction of XDP module

998-1571

ITPCLK#/HOOK5 ITPCLK/HOOK4 OBSDATA_D3 OBSDATA_D2

OBSDATA_D1 OBSDATA_B1

OBSDATA_B0 OBSFN_B1 OBSDATA_A2 OBSDATA_A0 OBSFN_A1 OBSFN_A0

Use with 920-0620 adapter board to support CPU, MCP debugging.

402

XDP

402

0.1uF XDP

16V

X5R10%

0.1uF XDP

16V402

FSB_CPURST_L CPU_PWRGD

XDP_TMS

XDP_TDO_CONN XDP_TRST_L XDP_TDI

FSB_CLK_ITP_N FSB_CLK_ITP_P MCP_DEBUG<5>

JTAG_MCP_TMS MCP_DEBUG<3>

MCP_DEBUG<1>

JTAG_MCP_TRST_L JTAG_MCP_TDO_CONN XDP_BPM_L<5>

XDP_PWRGD TP_XDP_OBSDATA_B3

XDP_OBS20 PM_LATRIGGER_L

JTAG_MCP_TCK

SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA

XDP_TCK

MCP_DEBUG<0>

XDP_DBRESET_L XDP_CPURST_L

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<4>

JTAG_MCP_TDI MCP_DEBUG<2>

C1301

12

202122232425262728293

303132333435363738394

404142434445464748495

505152535455565758596

60

789

Trang 14

OUTBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBI

BIBI

BIBIBIBIBIBIBIBIBI

INBIOUT

OUTOUTOUT

OUTOUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUT

OUT

OUTOUTOUTOUTOUT

OUTOUTIN

BIBI

BCLK_IN_N

CPU_A20M#

CPU_NMICPU_INTRCPU_SMI#

DRAWING NUMBER

SHT OF

SIZE

D Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Loop-back clock for delay matching.

402MF-LF1/16W1%

402MF-LF

49.9

MF-LF402

1%

1/16W

49.9

1/16W1%

402MF-LF

NO STUFF 1K

4025%

1/16W

1K

NO STUFF

402MF-LF5%

1/16W

1K

5%

402MF-LF

NO STUFF

1/16W

1/16W402MF-LF

62

5%

1/16W402MF-LF

54.9

1%

NO STUFF 150

1/16W402MF-LF5%

OMIT MCP79-TOPO-B

(1 OF 11)BGA

1/16W402MF-LF

62

5%

A.0.0

SYNC_DATE=06/18/2008MCP CPU Interface

051-7546

9614

FSB_D_L<38>

FSB_D_L<43>

FSB_D_L<45>

CPU_DPRSTP_L CPU_STPCLK_L FSB_CPUSLP_L FSB_CPURST_L CPU_PWRGD CPU_SMI_L CPU_NMI CPU_INTR CPU_INIT_L CPU_IGNNE_L CPU_A20M_L

FSB_CLK_MCP_P FSB_CLK_MCP_N FSB_CLK_ITP_N FSB_CLK_ITP_P FSB_CLK_CPU_N FSB_CLK_CPU_P FSB_DEFER_L FSB_BPRI_L FSB_D_L<63>

FSB_RS_L<2>

FSB_RS_L<1>

CPU_PROCHOT_L CPU_PECI_MCP FSB_TRDY_L FSB_LOCK_L FSB_HITM_L FSB_HIT_L

FSB_RS_L<0>

CPU_FERR_L

FSB_BREQ0_L FSB_ADS_L

G41G42

AL42AL43

AK42AL41

AM40AM39

AF35AG35AG39AE33AG37AG38AG34AN38AL39AG33AL33

AF41

AJ33AN36AJ35AJ37AJ36AJ38AL37AL34AN37AC34

AJ34AL38AL35AN34AR39AN35

AE38AE34AC37AE37AE35AB35

AD42

AE36AK35

AD43

AA41

AE40AL32

F41D42F42

AM42AM43

Y43W42

R42T39T42T41R41T43W35AA37W33W34Y40

AA36AA34AA38AA35U38U36U35U33U34W38W41

R33U37N34N33R34R35P35R39R37R38Y39

L37L39L38N36N38J39J38J37L42M42V42

P41N41N40M40H40K42H41L41H43H42Y41

K41J40H39M43

Y42P42U41

AH39AH42AF42AC43

AG41

E41AJ41

AH43

AC38AA33AC39AC33AC35

H38

AC41AB41AC42

AM33AH41

AG42

AG43AE41

AG27

AH28AG28AH27

Trang 15

0A MEMORY

CONTROL

MCKE0A_1MCKE0A_0

MODT0A_1MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_NMCLK0A_0_PMCLK0A_1_N

MCLK0A_2_NMCLK0A_1_PMCLK0A_2_P

MA0_0MA0_1MA0_2MA0_3MA0_4MA0_5MA0_6

MA0_8MA0_7MA0_9MA0_10MA0_11

MA0_13MA0_12MA0_14

MBA0_2MBA0_0MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_PMDQS0_0_N

MDQS0_1_PMDQS0_2_NMDQS0_1_N

MDQS0_2_PMDQS0_3_N

MDQS0_4_PMDQS0_3_PMDQS0_4_NMDQS0_5_NMDQS0_5_PMDQS0_6_NMDQS0_6_PMDQS0_7_NMDQS0_7_P

MDQM0_2MDQM0_1MDQM0_0

MDQM0_3MDQM0_4

MDQ0_0MDQM0_7MDQM0_5MDQM0_6MDQ0_1

MDQ0_4MDQ0_3MDQ0_2

MDQ0_5MDQ0_6

MDQ0_9MDQ0_8MDQ0_7MDQ0_10MDQ0_11

MDQ0_29MDQ0_28MDQ0_27

MDQ0_30MDQ0_31

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37MDQ0_38

MDQ0_47MDQ0_46

MDQ0_43

MDQ0_45MDQ0_44

MDQ0_51MDQ0_50MDQ0_49MDQ0_52

MDQ0_48

MDQ0_56MDQ0_57

MDQ0_62MDQ0_63

OUTOUTOUTOUTOUTOUTOUTOUTBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

BIBIBIBI

BIBI

BIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

MEMORY CONTROL 1A

MDQ1_63

MDQ1_58MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_49

MDQ1_42MDQ1_41

MDQ1_36MDQ1_35

MDQ1_31MDQ1_30

MDQ1_22

MDQ1_16

MDQ1_11MDQ1_10

MDQ1_7MDQ1_8MDQ1_9

MDQ1_3MDQ1_6

MDQ1_2MDQ1_4MDQ1_5

MDQ1_1

MDQM1_6MDQM1_5

MDQ1_0MDQM1_7

MDQM1_4MDQM1_3

MDQM1_0MDQM1_1MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_NMDQS1_6_PMDQS1_7_N

MDQS1_5_NMDQS1_5_PMDQS1_4_PMDQS1_3_PMDQS1_4_N

MDQS1_2_PMDQS1_3_N

MDQS1_1_PMDQS1_2_NMDQS1_1_NMDQS1_0_PMDQS1_0_N

MRAS1#

MCAS1#

MWE1#

MBA1_2MBA1_1MBA1_0

MA1_14MA1_13MA1_12MA1_11MA1_10MA1_9MA1_8MA1_7MA1_6MA1_5MA1_4MA1_3MA1_2MA1_1MA1_0

MCLK1A_2_P

MCLK1A_1_PMCLK1A_2_N

MCLK1A_0_PMCLK1A_1_N

MCS1A_1#

MCS1A_0#

MCLK1A_0_N

MODT1A_1MODT1A_0

MCKE1A_0MCKE1A_1

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTBI

OUTOUTOUTOUTOUTOUTOUT

APPLE INC

NONESCALE

15

SYNC_MASTER=T18_MLB SYNC_DATE=06/18/2008MCP Memory Interface

AN19AW21AN23AU15AR23

AU19AV19AN21AR21AP21AU21AR22AV21

AW17AP19AP23AP17

AT23AU23

BC20BB20AY24BA24AV33AW33

AR18AT15AP35

AR35

AV31AT31AW37AV37AR33AU31AN31AV29AN29AV27

AW38

AR31AP31AR29AP29AR27AP27AR25AP25AU27AT27

AV38

AU25AR26AU13AR14AT11AR11AW13AV13AV11AU11

AR38

AV9AU9AY5AW6AP11AW9AU8AU7AV5AU6

AR37

AR5AN10AW5AV6AR7AR6AN7AN6AL7AL6

AV39

AN9AP9AL9AL8

AW39AU37AT37

AR34AV35AW29AN27AN13AR10AU5AN5

AT39AU39AU35AT35AU29AU30AW25AV25AR13AP13AW8AW7AR9AR8AL11AL10

AV15AP15

AV17AR17

U1400

BA18BB25

BA17BC28AW28BA14BA29

BA25BB26BA26BA27AY27BA28AY28BB28

BB17BB18BB29BA15

BB30AY31

AY19BA19BA22BB22BB42BA42

BB16BB14AP42

AR41

BC40BA40AV41AV42AW40BB40AY39BA38BB36BA36

AU41

AY40BA39AW36BC36AY35BA34BB32BA32AY36BA35

AU40

AW32BC32BA12AY12BB9BB8AW12BB12BB10BA9

AN40

AY8BA7BC4BB4BC8BA8BA5BB5BB2BA3

AP41

AW3AW4BC3BB3AY3AY4AU3AU2AR3AR4

AT41

AV3AV2AT3AT4

AT40AW41AW42

AR42AY43BB38BB34BA11AY7BA2AT5

AT43AT42AY42BA43BA37BB37BA33BB33AY11BA10BA6BB6AY1AY2AT1AT2

AY15BB13

AW16BA16

Trang 16

MCLK1B_1_NMCLK1B_0_PMCLK1B_1_PMCLK1B_2_N

MRESET0#

GND55GND56GND57GND58GND60GND59GND61GND62GND63GND64

GND52GND53GND54GND51

GND49GND50GND48GND47GND46

GND39GND40GND38GND37GND36GND35

GND13GND14

GND10GND12GND11

GND2GND3GND4GND1

MEM_COMP_VDDMEM_COMP_GND

MODT0B_0MODT0B_1

MCKE0B_1MCKE0B_0

MCLK0B_0_NMCS0B_0#

MCS0B_1#

MCLK0B_2_NMCLK0B_1_P

MCLK0B_0_PMCLK0B_1_NMCLK0B_2_P

+V_PLL_XREF_XS+V_PLL_CORE+V_VPLL

+VDD_MEM1+VDD_MEM2+VDD_MEM3+VDD_MEM4+VDD_MEM5+VDD_MEM6+VDD_MEM7+VDD_MEM8+VDD_MEM9+VDD_MEM10+VDD_MEM11

+VDD_MEM14+VDD_MEM15+VDD_MEM16+VDD_MEM17+VDD_MEM18+VDD_MEM19+VDD_MEM20+VDD_MEM22+VDD_MEM21+VDD_MEM23+VDD_MEM24+VDD_MEM25+VDD_MEM26

+VDD_MEM30

+VDD_MEM27+VDD_MEM29+VDD_MEM31+VDD_MEM32+VDD_MEM33+VDD_MEM34

+VDD_MEM38+VDD_MEM39+VDD_MEM40+VDD_MEM41+VDD_MEM43+VDD_MEM44+VDD_MEM45+VDD_MEM42

+V_PLL_DP

+VDD_MEM13+VDD_MEM12

+VDD_MEM28

+VDD_MEM37+VDD_MEM36+VDD_MEM35

MEMORY CONTROL 0B MEMORY CONTROL 1B

OUT

APPLE INC

NONESCALE

MF-LF4021%

1/16W

40.2

(4 OF 11)

MCP79-TOPO-B OMIT

SYNC_DATE=06/18/2008SYNC_MASTER=T18_MLB

TP_MEM_A_CLK4N TP_MEM_A_CLK3P

TP_MEM_A_CLK3N TP_MEM_A_CS_L<2>

TP_MEM_A_CS_L<3>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_B_CLK5P TP_MEM_B_CLK5N TP_MEM_B_CLK4P TP_MEM_B_CLK4N TP_MEM_B_CLK3P TP_MEM_B_CLK3N

AT25AP30AR36AU10F28BC21AY9BC9D34F24G30

G32H31K7M38M5M6M7M9N39N8P10

P33P34P37P4P40P7R36R40R43R5T10

T18T20AK11T24T26

T33T34T35T37T38T6

T7T9U18U20U22

V10V34W5

AV23AN25

BA30BA31

BB21BA21BC24BB24AU34AU33

AY20BA20BA23AY23BB41BA41

AU17AR15

BC16BA13

AM41AN41

AN17AN15

AY16BC13

AY32U27

U28T27

T28

AM17

AN20AN24AT17AP16AN22AP20AP24AV16AR16AR20AM19

AR24AW15AP22AP18AU16AN18AU24AT21AY29AV24AM21

AU20AU22AW27BC17AV20AY17AY18AM15AU18AY25AM23

AY26AW19AW24BC25AL30AM31

AM25AM27AM29AN16BC29

Trang 17

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7+AVDD0_PEX8

+AVDD1_PEX3+AVDD1_PEX2+AVDD1_PEX1+AVDD0_PEX13+AVDD0_PEX12+AVDD0_PEX10+AVDD0_PEX9

+AVDD0_PEX6+AVDD0_PEX5+AVDD0_PEX4+AVDD0_PEX3+AVDD0_PEX2+AVDD0_PEX1

+V_PLL_PEX+DVDD1_PEX2+DVDD1_PEX1+DVDD0_PEX8+DVDD0_PEX7+DVDD0_PEX6+DVDD0_PEX5+DVDD0_PEX4+DVDD0_PEX3+DVDD0_PEX2+DVDD0_PEX1

PE1_TX1_NPE1_TX2_P

PE1_TX0_NPE1_TX1_P

PE6_REFCLK_NPEX_RST0#

PE1_TX0_P

PE5_REFCLK_NPE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_NPE4_REFCLK_PPE3_REFCLK_NPE2_REFCLK_N

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_NPE0_TX15_P

PE0_TX13_NPE0_TX14_P

PE0_TX12_NPE0_TX12_PPE0_TX13_PPE0_TX11_NPE0_TX11_PPE0_TX10_N

PE0_TX9_NPE0_TX10_PPE0_TX8_NPE0_TX8_PPE0_TX9_P

PE0_TX7_NPE0_TX7_PPE0_TX6_N

PE0_TX5_NPE0_TX6_P

PE0_TX4_NPE0_TX5_PPE0_TX3_NPE0_TX3_PPE0_TX4_P

PE0_TX2_NPE0_TX2_P

PE0_TX0_NPE0_TX1_NPE0_TX1_PPE0_TX0_P

PEX_CLK_COMP

PE1_RX3_NPE1_RX3_PPE1_RX2_N

PE1_RX0_NPE1_RX1_P

PE1_RX2_PPE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_NPE0_RX14_PPE0_RX15_PPE0_RX14_NPE0_RX15_N

PE0_RX12_PPE0_RX11_P

PE0_RX13_P

PE0_RX11_NPE0_RX12_NPE0_RX10_N

PE0_RX8_PPE0_RX9_PPE0_RX10_P

PE0_RX8_NPE0_RX9_N

PE0_RX5_N

PE0_RX7_PPE0_RX6_NPE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_NPE0_RX4_N

PE0_RX1_PPE0_RX1_N

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUT

OUTOUTOUTOUT

OUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUT

ININ

ININININININININININININININININININININININININININININININ

ININ

IN

ININ

OUTOUT

OUTOUTOUTOUT

OUTOUT

IN

OUT

ININ

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Minimum 1.025V for Gen2 support Minimum 1.025V for Gen2 support

Int PU

Int PU Int PU Int PU

Int PU Int PU

Int PU

Int PU Int PU

84 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

17 96

A.0.0051-7546

AUD_IP_PERIPHERAL_DET TP_PE4_CLKREQ_L PCIE_EXCARD_PRSNT_L

PCIE_EXCARD_D2R_P PCIE_FW_D2R_P PCIE_MINI_D2R_N

PCIE_EXCARD_D2R_N TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN

PCIE_CLK100M_FW_P PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

PCIE_MINI_R2D_C_P PCIE_RESET_L TP_PCIE_CLK100M_PE6N

PCIE_FW_R2D_C_P PCIE_MINI_R2D_C_N

PCIE_EXCARD_R2D_C_P PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

AA12AB12M12P12R12N12T12U12

M13N13P13

T17W19U17V19W16W17W18U16T19U19

T16

E11

E7F7

L8L9

L6L7

N10N11

P9N9

N6N7

N4N5

C7D7

F6E6

F5E5

E3E4

D3C3

H5G5

J6J7

J4J5

L10L11

D4C5

J1H1

J3J2

K3K2

L3L4

M3M4

M1M2

B4C4

A3A4

B2B3

D1C1

E1D2

F2E2

F4F3

H4G3

H2H3

F11G11

J9K9

G9H9

E9F9

G7H7

C8D8

A8B8

B7A7

C6B6

J10J11

F13G13

H13J13

K14L14

M14N14

F17

D5D9E8C10M15B10

L16L18

M16

M18M17M19

Trang 18

BI

OUT

ININININININ

OUT

OUTOUT

OUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTININ

OUTOUT

OUTOUTOUTOUTOUT

IN

INOUT

INININ

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI+V_PLL_HDMI+V_PLL_IFPAB+VDD_IFPB+VDD_IFPA

+V_TV_DAC+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GNDMII_COMP_VDD

LCD_PANEL_PWR/GPIO_58LCD_BKL_ON/GPIO_59LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_PHDMI_TXC_N/ML0_LANE3_NHDMI_TXD0_P/ML0_LANE2_PHDMI_TXD0_N/ML0_LANE2_NHDMI_TXD1_P/ML0_LANE1_PHDMI_TXD1_N/ML0_LANE1_NHDMI_TXD2_P/ML0_LANE0_PHDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_NXTALIN_TV

DDC_DATA2/GPIO_24DDC_CLK2/GPIO_23

RGB_DAC_RSETRGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_PDP_AUX_CH0_N

HPLUG_DET3

HDMI_RSETHDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0DDC_CLK0

RGB_DAC_REDRGB_DAC_GREENRGB_DAC_BLUERGB_DAC_HSYNCRGB_DAC_VSYNCTV_DAC_REDTV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_PIFPA_TXD0_N

IFPA_TXD2_P

IFPB_TXC_PIFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_PIFPB_TXD4_N

IFPB_TXD6_PIFPB_TXD5_NIFPB_TXD6_NIFPB_TXD7_PIFPB_TXD7_N

DDC_DATA3DDC_CLK3

IFPAB_RSETIFPAB_VPROBE

RGMII_RXD2RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36MII_COL/GPIO_20/MSMB_DATAMII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUETV_DAC_HSYNC/GPIO_44TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXENRGMII_TXC/MII_TXCLK

RGMII_TXD3RGMII_TXD2RGMII_TXD1RGMII_TXD0

+3.3V_DUAL_RMGT1+3.3V_DUAL_RMGT2

OUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTBIOUTBIOUTOUT

OUT

OUTOUTOUT

APPLE INC

NONESCALE

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1 0 MII

RGMII Interface

Network Interface Select

NOTE: All Apple products set strap to feature via software This avoids a leakage issue since

5 mA (A01)

DisplayPort DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N TMDS_IG_DDC_DATA TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N TMDS/HDMI

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N DP_IG_HPD DP_IG_DDC_DATA DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET.

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below) (See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0) To ensure pins are low

by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

49.9

1/16W

49.9

4021%

MCP79-TOPO-B OMIT

10K

4021/16W5%

MF-LF

4025%

100K

1/16W402

MF-LF5%

MCP Ethernet & Graphics

=DVI_HPD_GMUX_INT

LVDS_IG_BKL_PWM MCP_CLK27M_XTALOUT

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

CRT_IG_VSYNC CRT_IG_HSYNC CRT_IG_B_COMP_PB

=MCP_MII_CRS

=MCP_MII_COL

=MCP_MII_RXER

TP_ENET_PWRDWN_L ENET_MDC

ENET_RESET_L

ENET_RXD<1>

ENET_RXD<2>

ENET_CLK125M_RXCLK ENET_RX_CTRL ENET_RXD<3>

TP_ENET_INTR_L ENET_RXD<0>

MCP_TV_DAC_RSET

MCP_IFPAB_VPROBE MCP_IFPAB_RSET

MCP_DDC_CLK0 MCP_DDC_DATA0

MCP_CLK25M_BUF0_R ENET_MDIO

=MCP_HDMI_HPD

DP_IG_AUX_CH_N DP_IG_AUX_CH_P MCP_TV_DAC_VREF

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

MCP_CLK27M_XTALIN

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXC_P

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

MCP_MII_COMP_VDD MCP_MII_COMP_GND

E16B15

J31

E35D35

F35G35

G33F33

H33J33

J30

C31F31

C35B35

A32B32

C32D32

C33D33

C34B34

E32G31

K31L31

H29J29

K29L29

K30L30

M30N30

G39E37F40

B26

B27C27B22

J23

F23

E28

J24K24

T23

U23V23

M29M28

J32K32

T25

M27M26

B40A39

A40B39

C39B38

A41

J22

D21C21G23

A23C22

C23B23E24A24

D24C26

B24C24C25D25

C36B36

D36A36

E36A35

C37

C38D38

Trang 19

OUTBIBIBIBI

PCI_AD5PCI_AD6

PCI_AD9PCI_AD8PCI_AD7

PCI_AD10PCI_AD11

PCI_AD21PCI_AD22

PCI_AD25PCI_AD23

PCI_AD26

PCI_AD29PCI_AD31

GND66GND67GND69GND68GND70GND71GND72GND74GND73GND75GND76GND77GND79GND78GND80GND81

GND84GND83GND82

GND85GND86GND87GND89GND88GND90GND91GND92GND94GND93GND95GND96GND97

PCI_STOP#

PCI_RESET0#

PCI_RESET1#

PCI_CLK2PCI_CLK1PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1LPC_AD0LPC_RESET0#

LPC_CLK0LPC_AD3LPC_AD2

GND115GND114GND113

GND116GND117

GND120GND119GND118

PCI_CLKRUN#/GPIO_42PCI_AD28

OUT

BIBIBIBIBIBIBIBI

OUT

OUTOUT

APPLE INC

NONESCALE

MCP79-TOPO-B OMIT

22

402MF-LF1/16W5%

8.2K

402MF-LF1/16W5%

8.2K 5% 1/16W MF-LF 402

8.2K

402MF-LF1/16W5%

8.2K 8.2K

5% 1/16W MF-LF 402

19

MF-LF4021/16W5%

MCP PCI & LPC

GMUX_JTAG_TDI GMUX_JTAG_TMS

TP_PCI_INTX_L TP_PCI_INTZ_L

FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ PM_CLKRUN_L

PCI_REQ0_L PCI_REQ1_L

LPC_PWRDWN_L LPC_RESET_L LPC_FRAME_R_L

LPC_CLK33M_SMC_R LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

TP_PCI_CLK0 TP_PCI_RESET1_L

PM_LATRIGGER_L TP_PCI_STOP_L TP_PCI_SERR_L TP_PCI_PAR TP_PCI_IRDY_L TP_PCI_FRAME_L TP_PCI_DEVSEL_L TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<0>

MCP_RS232_SOUT_L TP_PCI_GNT1_L TP_PCI_GNT0_L

U1400

AB18H34AB20AB21AB23AB24AB25AB26AB27AB28AB34AB37AB4AB40AC22AC36AC40AB33AC5AD16AD17AD18AD19AD20AD24AD25AD26AD27AD28AD33AD34

U24U26U39U4U8V16V17V18V20V22V24V26V27V28V33V37V4V40V7W20W22W24W36W40W43Y16Y17Y18Y19Y20Y22Y24Y25

Y26Y27

AD3AD2AD1AD5AE9AE1

AE2

AD4AE12AE5

AE6

AC3AE10

AC9AC10AC11AA1AA5Y5W3W6W4W7AC4

V3W8V2W9U3W11U2U5U1U6AE11

T5U7

AB3AC6AB2AC7AC8AA2

AA3AA6AA11W10

R6R7R8

R9

AD11

AA9Y4

R3U10R4U11P3

P2N3N2N1

AA10Y1AB9

T1

T2V9T3U9T4

R10R11

AA7Y2

R1994 1 2R1992 1 2

Trang 20

ININININ

GND143GND144GND142GND141GND140GND139GND136

GND133GND134GND132GND131USB_RBIAS_GND

USB11_NUSB11_PUSB10_NUSB10_PUSB9_NUSB9_P

USB7_N

USB8_NUSB8_PUSB7_PUSB6_NUSB6_PUSB5_NUSB4_NUSB4_P

USB5_P

USB2_NUSB2_P

USB0_N

USB1_NUSB1_PUSB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_NSATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_NSATA_B1_RX_PSATA_B1_TX_NSATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_PSATA_B0_TX_P

SATA_A1_RX_NSATA_A1_RX_PSATA_A1_TX_NSATA_A0_TX_P

GND138GND137GND135

USB3_PUSB3_N

USB_OC0#/GPIO_25USB_OC1#/GPIO_26USB_OC2#/GPIO_27/MGPIOUSB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_NSATA_A0_TX_N

SATA_C1_TX_NSATA_C1_TX_P

SATA_C0_RX_PSATA_C0_RX_NSATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1+DVDD0_SATA2+DVDD0_SATA3+DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1+AVDD0_SATA2+AVDD0_SATA3+AVDD0_SATA4+AVDD0_SATA5+AVDD0_SATA6+AVDD0_SATA7+AVDD0_SATA8+AVDD0_SATA9+AVDD1_SATA1+AVDD1_SATA2+AVDD1_SATA3+AVDD1_SATA4+DVDD1_SATA1

SATA USB

OUTOUT

ININ

OUTOUTININ

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

External D External A

Camera

Bluetooth IR

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

Minimum 1.025V for Gen2 support

MF-LF

4021/16W1%

MF-LF

806

4021/16W

MF-LF4021/16W

BGA

OMIT MCP79-TOPO-B

MCP SATA & USBSYNC_MASTER=T18_MLB

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

TP_SATA_C_D2RP TP_SATA_C_D2RN

PP1V05_S0_MCP_PLL_SATA

USB_EXTA_OC_L

TP_USB_11N TP_USB_11P TP_USB_10P USB_EXTC_N USB_EXCARD_N

USB_EXTB_N USB_EXTB_P USB_BT_N USB_BT_P USB_TPAD_N USB_TPAD_P USB_IR_N USB_IR_P USB_CAMERA_N USB_CAMERA_P USB_EXTD_N USB_EXTD_P USB_MINI_N USB_EXTA_N USB_EXTA_P

MCP_SATA_TERMP

TP_SATA_F_D2RP TP_SATA_F_D2RN TP_SATA_F_R2D_CN TP_SATA_E_D2RN

TP_SATA_D_R2D_CN

TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP

TP_MCP_SATALED_L

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

USB_EXTC_P USB_EXCARD_P

AJ12AN11AK12AK13AL12AM11AM12AN12AL13AN14AL14AM13AM14

AF19AG16AG17AG19AH17AH19AE16

L28

AJ5AJ4

AJ6AJ7

AJ9AK9

AJ10AJ11

AJ2AJ1

AJ3AK2

AL4AK3

AL3AM4

AM2AM3AM1AN1

AN3AN2

AP2AP3

E12

AE3

D29C29

G25F25

L23K23

D28C28

B28A28

G29F29

L27K27

J27J26

G27F27

E27D27

L25K25

J25H25

L21K21J21H21

Trang 21

OUTOUT

BIBIOUTOUT

OUTOUT

OUT

OUTOUT

ININ

OUT

OUTIN

OUT

ININOUT

ININININOUT

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

MCP_VID2/GPIO_15MCP_VID1/GPIO_14MCP_VID0/GPIO_13THERM_DIODE_N

EXT_SMI/GPIO_32#

FANCTL1/GPIO_62FANRPM1/GPIO_63FANCTL0/GPIO_61FANRPM0/GPIO_60

SIO_PME#

KBRDRSTIN#

PKG_TESTTEST_MODE_ENBUF_SIO_CLKCPUVDD_EN

SMB_DATA0SMB_CLK0SPKR

HDA_RESET#

HDA_SYNC

HDA_BITCLKHDA_SDATA_OUT

XTALIN_RTCXTALOUT

XTALOUT_RTC

JTAG_TRST#

XTALINJTAG_TCKJTAG_TMS

CPU_VLDJTAG_TDIJTAG_TDO

RTC_RST#

PS_PWRGDPWRGD_SB

A20GATE

GPIO_12/SUS_STAT#/ACCLMTR

HDA_SDATA_IN0

GPIO_1/PWRDN_OK/SPI_CS1HDA_PULLDN_COMP

THERM_DIODE_PSLP_RMGT#

SMB_CLK1/MSMB_CLKSMB_DATA1/MSMB_DATASMB_ALERT#/GPIO_64

SPI_CS0/GPIO_10SPI_CLK/GPIO_11SPI_DI/GPIO_8SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1+V_DUAL_HDA2

+V_PLL_NV_H+V_PLL_SP_SPREF

IN

ININ

INOUTOUT

APPLE INC

NONESCALE

Int PU (S5) Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5) Int PU Int PU

25 MHz

42 MHz 0

LPC ROMs So Apple designs will

0 1 HDA_SYNC

24 MHz

0 1

1 0

SPI_CLK SPI_DO

0

1 1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1 1 0 0

LPC_FRAME#

0 1 0

1

Int PU

Int PD Int PD Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option Rev B01 will.

Int PU Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP recovery USER mode: Normal

Connects to SMC for automatic recovery.

1K

MF-LF1%

1/16W402

26 90

23

MF-LF4025%

22

1/16W

MF-LF5%

1/16W402

22

5%

22

MF-LF402

4025%

5%

10K

402MF-LF

BOOT_MODE_USER

1/16W

4025%

402

4021/16W5%

402CERM

50V

10PF

5%

402CERM

BGA(9 OF 11)

MCP79-TOPO-B OMIT

100K

10K

5%

1/16W402MF-LF402

1/16W5%

10K

22K

5%

MF-LF402

22K

5%

MF-LF402402

1/16W

100K

1/16W5%

100K

402MF-LF

4021/16W5%

10K 10K

5%

MF-LF402

21 96

A.0.0051-7546

PM_PWRBTN_L

RTC_RST_L

MCP_PS_PWRGD

JTAG_MCP_TDI JTAG_MCP_TDO

SMBUS_MCP_1_DATA AP_PWR_EN

MCP_VID<2>

SMBUS_MCP_0_DATA PM_BATLOW_L

SPI_CS0_R_L

RTC_CLK32K_XTALOUT RTC_CLK32K_XTALIN MCP_CLK25M_XTALOUT MCP_CLK25M_XTALIN JTAG_MCP_TCK

PM_CLK32K_SUSCLK_R

SPI_MISO SPI_MOSI_R

SMBUS_MCP_0_CLK MCP_THMDIODE_N

PM_SYSRST_DEBOUNCE_L TP_MCP_KBDRSTIN_L

HDA_RST_L HDA_BIT_CLK HDA_SDOUT

MCP_VID<2>

MCP_VID<1>

JTAG_MCP_TMS

MCP_TEST_MODE_EN JTAG_MCP_TRST_L

PM_RSMRST_L SM_INTRUDER_L

ARB_DETECT

HDA_SYNC HDA_RST_R_L

ODD_PWR_EN_L MEM_EVENT_L SMC_WAKE_SCI_L

=PP3V3_S0_MCP_GPIO

MEM_EVENT_L SMC_IG_THROTTLE_L

SMC_ADAPTER_EN

TP_MLB_RAM_VENDOR TP_MLB_RAM_SIZE

HDA_SYNC_R

AUD_I2C_INT_L PM_SLP_S3_L PM_SLP_S4_L

=PP3V3_S0_MCP

MCP_SPKR

MCP_CPUVDD_EN ARB_DETECT SMC_IG_THROTTLE_L

C2173

12

C21701

2

C217212

B12D12

L26L24

E15

K17L17A15

L13

M25M24

L20M20M21

J16K16

AE18AE17

C19

J17G17H17

M23

L19G21K19F21

D13C14C15B14C13

B18

K22

C11B11

A16

A19B16

Trang 22

GND161

GND167GND168

GND171GND170GND169

GND172GND173

GND176GND175GND174

GND177GND178

GND181GND180GND179

GND182GND183GND184

GND187GND186GND185

GND188GND189

GND192GND191GND190

GND193GND194

GND197GND196GND195

GND198

GND203

GND208

GND213GND214

GND217GND216GND215

GND218GND219

GND222GND221GND220

GND223GND224GND225

GND228GND227GND226

GND229GND230

GND233GND232GND231

GND234GND235

GND238GND237GND236

GND239GND240

GND243GND242GND241

GND244

GND249

GND252GND251GND250 GND342

GND316GND317GND315GND314GND313GND311GND310GND312

GND309GND308

GND305GND306GND307

GND268GND267

GND264GND265GND266

GND263GND262

GND259GND260GND261

+VTT_CPUCLK+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17+VTT_CPU16+VTT_CPU15+VTT_CPU14+VTT_CPU13+VTT_CPU12+VTT_CPU11+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1+VDD_CORE2+VDD_CORE3+VDD_CORE4+VDD_CORE5+VDD_CORE6

+VDD_CORE13+VDD_CORE14+VDD_CORE15+VDD_CORE16+VDD_CORE17+VDD_CORE18+VDD_CORE19+VDD_CORE21+VDD_CORE22+VDD_CORE23+VDD_CORE24+VDD_CORE25+VDD_CORE26+VDD_CORE27+VDD_CORE28+VDD_CORE29+VDD_CORE30+VDD_CORE32+VDD_CORE33+VDD_CORE34+VDD_CORE35+VDD_CORE36+VDD_CORE37+VDD_CORE39+VDD_CORE40+VDD_CORE41

+VDD_CORE47+VDD_CORE48+VDD_CORE49+VDD_CORE50+VDD_CORE51+VDD_CORE52+VDD_CORE53+VDD_CORE54

+VTT_CPU51+VTT_CPU50+VTT_CPU47+VTT_CPU46+VTT_CPU45+VTT_CPU43+VTT_CPU42+VTT_CPU41+VTT_CPU40+VTT_CPU39+VTT_CPU38+VTT_CPU37+VTT_CPU36+VTT_CPU35+VTT_CPU34+VTT_CPU32+VTT_CPU31+VTT_CPU30+VTT_CPU29+VTT_CPU28+VTT_CPU26+VTT_CPU25+VTT_CPU24+VTT_CPU23+VTT_CPU22+VTT_CPU21+VTT_CPU20+VTT_CPU19+VTT_CPU18

+VTT_CPU9+VTT_CPU8+VTT_CPU7+VTT_CPU6+VTT_CPU5+VTT_CPU4+VTT_CPU3

+VDD_CORE38

+VTT_CPU33+VTT_CPU27

+VDD_CORE55+VDD_CORE56+VDD_CORE57+VDD_CORE58+VDD_CORE59+VDD_CORE60+VDD_CORE61+VDD_CORE62+VDD_CORE63+VDD_CORE64+VDD_CORE65+VDD_CORE66+VDD_CORE67+VDD_CORE68+VDD_CORE69+VDD_CORE70+VDD_CORE71+VDD_CORE72+VDD_CORE73+VDD_CORE74+VDD_CORE75+VDD_CORE76+VDD_CORE77+VDD_CORE78+VDD_CORE79+VDD_CORE80+VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1+3.3V_DUAL2+3.3V_DUAL3+3.3V_DUAL4+3.3V_DUAL_USB1+3.3V_DUAL_USB3+3.3V_DUAL_USB4

+VDD_AUXC1+VDD_AUXC3+VDD_AUXC2+VDD_CORE43

+VTT_CPU2

+VDD_CORE46+VDD_CORE45+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49+VTT_CPU48+VTT_CPU44

+3.3V_7+3.3V_6+3.3V_5+3.3V_4+3.3V_3+3.3V_2

+VDD_CORE20

+VDD_CORE12+VDD_CORE11+VDD_CORE10+VDD_CORE9+VDD_CORE8

APPLE INC

NONESCALE

BGA

MCP79-TOPO-B OMIT

051-7546 A.0.0

9622

MCP Power & Ground

AV40BA1BA4AW31AY6L35BC33BC37BC41AY14BC5C2D10D14D15D18D19D22D23D26D30D37D6E13E17E21E25E29E33F12F16F32F8G10G12G14G16BC12G22G24AW20G34G4G43G6G8H11H15AW35H23AN8G40J12J8K10K12K18K26K37K4K40K8AU1L40L43L5M10M34M35M37Y28Y33Y34Y35Y37Y38AB17AB16AN26AD7M11AA4AB19AY13P11Y6T11V11Y11AH16T22

U1400

AD10AE8AB10AD9Y10AB11AA8Y9

G18H19J20K20G26H27J28K28

A20

T21U21V21

AA25

AA26AA27AA28AC16AC17AC18AC19AC20AC21AA17AC23

AC24AC25AC26AC27AC28AD21AD23W27V25AA18U25

AE19AE21AE23AE25AE26AE27AE28AF10AF11AA19AH12

AF2AF21AF23AF25AF3AF4AF7AH23AF9AA20AG10

AG11AG12AG21AG23AG25AG3AG4AA21AG6AG7AG5

AG8AG9AH1AH10AH11W26AH2AA23W28AH25Y21

AH21AH3AH4AH5AH6AH7AH9AA24W21W23Y23

W25AF12

AA16

R32

P31AF32AE32AH32AJ32AK31AK32AD32AL31AB32AC32

B41B42C40C41C42D39D40D41E38E39E40

F37F38F39G36G37G38H35H37J34J35J36

K33K34K35L32L33L34M31M32M33N31N32

P32Y32AA32

T32U32V32W32

Trang 23

OUTOUTOUTOUT

APPLE INC

NONESCALE

MCP_A01&MCP_A01P&MCP_A01Q

402MF-LF1/16W5%

10K

402MF-LF1/16W5%

10K

MCP_A01&MCP_A01P&MCP_A01Q 10K

402MF-LF1/16W5%

5% 1/16W MF-LF 402

10K

SYNC_DATE=03/31/2008 SYNC_MASTER=T18_MLB

MCP79 A01 Silicon Support

051-7546 A.0.0

9623

PM_LATRIGGER_L

PM_SYSRST_DEBOUNCE_L

SMC_WAKE_SCI_L

PM_BATLOW_L PM_PWRBTN_L SMC_RUNTIME_SCI_L

JTAG_MCP_TMS JTAG_MCP_TDI PCIE_WAKE_L

MAKE_BASE=TRUE

MCP_LID_L TP_MCP_LID_L

=PP3V3_S5_MCP_A01

R2412 1 2R2411 1 2R2410 1 2

R2403 1 2R2402 1 2R2401 1 2R2400 1 2

R2404 1 2

R2413 1 2R2405 1 2

44 8

Trang 24

APPLE INC

NONESCALE

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)

Apple: 5x 2.2uF 0402 (11 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 1x 2.2uF 0402 (2.2 uF) MCP 1.05V AUX Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)

270 mA (A01)

40220%

4.7UF

4V

4024V

4.7UF

20%

4024V20%

4.7UF

40220%

1UF

402-1X5R10V

1UF

402-1X5R10V

1UF

402-1

40220%

CERM

0.1UF

10V40220%

CERM

0.1UF

10V40220%

CERM

0.1UF

10V40220%

CERM

0.1UF

10V40220%

CERM

0.1UF

10V40220%

CERM

0.1UF

CERM402-LF20%

2.2UF

6.3VCERM

402-LF20%

2.2UF

6.3VCERM

402-LF20%

6.3V

2.2UF

CERM402-LF20%

2.2UF

6.3VCERM

402-LF20%

2.2UF

6.3VCERM

402-LF6.3V

2.2UF

20%

CERM402-LF20%

1UF

402-1X5R402

20%

4V

4.7UF

CERM402-LFCERM

402-LF20%

2.2UF

6.3V402

20%

4.7UF

4V

CERM402-LF20%

2.2UF

6.3VCERM

402-LF20%

2.2UF

6.3V

CERM402-LF20%

6.3V

2.2UF

CERM402-LF20%

2.2UF

6.3VCERM

402-LF20%

6.3V

2.2UF

CERM402-LF20%

2.2UF

6.3V

10V402CERM20%

0.1UF

10V402CERM20%

0.1UF

10V402CERM20%

0.1UF

10V402CERM20%

0.1UF

10V402CERM20%

0.1UF

10V402CERM20%

0.1UF

10V402CERM20%

0.1UF

10V402

0.1UF

CERM20%

10V40220%

CERM

0.1UF

4024V

4.7UF

20%

CERM402-LF20%

4024V20%

4V

4.7UF

40220%

4V

4.7UF

10V402

0.1uF

20%

CERM10V

2.2UF

6.3V

10V40220%

0.1UF

CERM 10V

40220%

0.1UF

CERM

4024V

1/16W

1.47K

10V40220%

0.1uF

20%

CERM10V

402CERM20%

0.1uF

10V40220%

CERM

0.1uF

10V40220%

0.1UF

CERM

10V402

0.1UF

CERM20%

10V402

0.1UF

CERM20%

10V402

0.1UF

20%

CERM

10V402

0.1uF

20%

CERM402

4V

4.7uF

20%

40220%

4V

4.7UF

96051-7546 A.0.0

24

MCP Standard DecouplingSYNC_MASTER=T18_MLB SYNC_DATE=06/18/2008

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

PP3V3_S0_MCP_PLL_USB

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_PEX

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05VMIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

20%

CERM402-LF

PP1V05_S0_MCP_PLL_FSB

0603

MIN_LINE_WIDTH=0.4 MM

402-HFMF1/6W

0.2

1%

C250312

C258212

C258812

C258412

C258612

C25551

2

C250212

C25071

2

C25061

2

C25051

2

C25041

2

C25111

2

C25101

2

C25091

2

C25081

2

C25131

2

C25121

2

C25361

2C25351

2C25341

2C25331

2C25321

2C25311

2C25301

2

C25171

2C25161

2C251512

C25721

2C25711

2C25201

2

C25701

2

C25741

2C25731

2

C25761

2

C25751

2

C25531

2

C25521

2

C25511

2

C25501

2

C25491

2C25481

2C25471

2C25461

2C25451

2C25441

2C25431

2C25421

2C25411

2C254012

C25621

2

C25641

2

C258012

C25261

2

C25251

2

C25601

2

C25891

2

C25901

2

C259512

R25911

2

C25211

2C2518

1

2

C25191

2

C25811

2

C25831

2

C25851

2

C25871

2

C25961

2

C25291

2C252812

Trang 25

A0 VCC

SDA

WP GND

INBI

APPLE INC

NONESCALE

WF: Open question on which packge option(s) nVidia can support.

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Apple: 1x 2.2uF 0402 (2.2 uF) NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

95 mA (A01)

6.3V402-LF

NO STUFF 2.2UF

20%

NO STUFF 30-OHM-1.7A

0.1uF

OMIT

SOICAT24C08402

1/16W402

45

402MF-LF5%

2.2UF

6.3V

SYNC_DATE=06/18/2008SYNC_MASTER=AMASON_M98_MLB

MCP Graphics Support

25 96

A.0.0051-7546

TP_MCP_RGB_RED TP_MCP_RGB_GREEN

CRT_IG_B_COMP_PB

MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MMVOLTAGE=3.3V

MCP_IFPAB_VPROBE

MCP_TV_DAC_RSET MCP_TV_DAC_VREF

MAKE_BASE=TRUENC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC TP_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y CRT_IG_G_Y_Y

2.2UF

402-LF6.3V

R2620

1

2

C26101

2

C26501

2

L2650

C262012

R2630

1

2

C263012

C261512

C264012

L2640

C26411

2

C2616

12

U2695

123

4

658

7

C269012

Trang 26

OUTIN

NCNC

OUT

OUTIN

IN

OUTOUT

OUT

OUTOUT

IN

ININ

OUT

Y B A

VIN

GND

VOUTEN

NC

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D but results in MCP79 ROMSIP sequence happening after CPU powers up.

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

Reset Button

10K pull-up to 3.3V S0 inside MCP

LPC Reset (Unbuffered) Platform Reset Connections

PCIE Reset (Unbuffered)

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for MCP S0 PWRGD & CPU_VLD

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.

RTC Crystal RTC Power Sources

12pF

50V

5%

50VCERM402

12pF

4021/16W

1/16W402

33

5%

1/16WPLACEMENT_NOTE=Place close to U1400

402

MF-LF4021/16W5%

0

402MF-LF5%

0 OMIT

SILK_PART=FP SYS RESET

5%

33

MF-LFPLACEMENT_NOTE=Place close to U1400

CRITICAL 25.0000M

SM-3.2X2.5MM402

MF-LF

33

402

40210V

1UF

NO STUFF

36

MF-LF5%

27

402MF-LF5%

0

85

402MF-LF5%

MF-LF

33

MF-LF4021/16W5%

PLACEMENT_NOTE=Place close to U1400

1/16W

0

402

MCPSEQ_MIX MCPSEQ_SMC

TC7SZ08AFEAPESOT665

1.0M

5%

NO STUFF

1/10W603MF-LF

6.3V10%

402CERM

1UF

2%

0.08F

XHHGSM3.3V

100

5%

1/16W402

PCIE_RESET_L

VR_PWRGOOD_DELAY

S0_AND_IMVP_PGOOD ALL_SYS_PWRGD

PM_CLK32K_SUSCLK LPC_CLK33M_GMUX

=PP3V3_S5_RTC_D

RTC_CLK32K_XTALOUT_R

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT

12

C280112C2800

12

Trang 27

OUTOUT

V+

V-RESET*

A0A1A2

SCLSDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPAD

NCNC

IN

INBI

VDD

VOUTDVOUTCVOUTBVOUTASCL

SDAA0A1GND

INBI

APPLE INC

NONESCALE

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mANominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 VMax Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

(i.e not simultaneously) due to current limitation of TPS51116 regulator

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

MEM B VREF DQMEM A VREF DQ

Required zero ohm resistors when no VREF margining circuit stuffed

Power aliases required by this page:

20%

402CERM

100

4021%

VREFMRGN

1/16W

5% VREFMRGNMF-LF4021/16W

MF-LF5% VREFMRGN402

100K

9

MF-LF402

49.9

1%

VREFMRGN

UCSPMAX4253VREFMRGN

UCSPVREFMRGNMAX4253

UCSPMAX4253VREFMRGN

UCSPVREFMRGNMAX4253

UCSPMAX4253VREFMRGN

VREFMRGN

1%

200

1/16W402

200

1%

MF-LFVREFMRGN

1%

200

1/16W402VREFMRGN

5%

100K

1/16W402VREFMRGN

100K

1/16W5%

402MF-LFVREFMRGN

402

100

1%

1/16WVREFMRGN

MF-LF4021%

1/16W

100

VREFMRGN

402MF-LF1%

100

VREFMRGN

MF-LFVREFMRGN4021/16W

402

100

MF-LF1%

1/16WVREFMRGN

5%

4021/16W

100K

MF-LFVREFMRGN

VREFMRGN 0.1UF

CERM20%

2.2UF

CERM20%

0.1UF

CERM

0.1UF VREFMRGN

40220%

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=DDR

051-7546 A.0.0

9627

VREFMRGN_FRAMEBUF_ENVREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_ENVREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_ENVREFMRGN_CA_SODIMMA_BUFVREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_FRAMEBUF_ENVREFMRGN_DQ_SODIMMB_ENVREFMRGN_CPUFSB_EN

=I2C_VREFDACS_SDA

PCA9557D_RESET_LVREFMRGN_DQ_SODIMMA_EN

=I2C_VREFDACS_SCL

VREFMRGN_CA_SODIMMB_EN

CPU_GTLREFGPU_FB_B_VREF_DIVGPU_FB_A_VREF_DIV

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

=PP3V3_S3_VREFMRGN

VREFMRGN_CPUFSBVREFMRGN_DQ_SODIMM

679101112131415

12

C2903

12

C2902

12

3

67

81245

C2901

12

C2900

12

C2905

12

Trang 28

A5

DQ33

VDDA10/AP

VDD

VSS

SA1VTT

VSS

DQS4*

DQS4VSSDQ35

VSSCK0*

SA0

VSSDQ58DQ59DM7

VSSDQ57DQ56

DQ50DQ51VSS

DQS6*

DQS6VSSDQ49DQ48

DQ43VSS

DM5VSSDQ42

SDASCLVTT

VSSEVENT*

DQ62VSSDQ63

DQS7*

DQS7

DQ60DQ61VSS

VSSDQ55DQ54

DM6VSS

DQ53VSSDQ52

DQ47VSS

DQS5VSSDQ46DQ41

VSSDQ40DQ34VSSDQ32TESTVDD

VDDS1*

A13CAS*

WE*

BA0VDD

VDDCK0A1A3VDD

VDDA8A9A12/BC*

VDDBA2NCVDDCKE0

VSSDQS5*

VSSDQ44DQ45

DQ39DQ38VSS

VSSDM4

VSSDQ37DQ36VREFCA

VDDODT1NC

S0*

ODT0

BA1RAS*

VDD

CK1*

VDD

VDDA0CK1

A2VDDA4VDD

VDDA14A15

CKE1VDD

BIIN

BIBIBIBIBIBIIN

BIIN

BIBIBIINBIBIBIBIBIBIBIBI

DQ16

DM3DQ26DQ27

DQ4

DQ31DQ30DQS3DQS3*

DQ29DQ28DQ23DQ22DM2DQ21DQ20DQ15DQ14RESET*

DM1DQ13DQ12DQ7DQ6DQS0DQS0*

DQ5

DQ24DQ25

DQ19DQ18DQS2DQS2*

DQ17DQ11DQ10DQS1DQS1*

DQ8DQ9

DM0

DQ0DQ1VREFDQ

DQ3DQ2VSSVSS

VSS

INBIBIBIBIBI

BIBI

BIBIBI

BIBI

ININ

ININININ

ININ

BIBIBIBIINBIBI

IN

BIBI

INBIBI

BIBI

BI

BIBI

BIINBIBIBIBI

BIBI

OUTBIIN

IN

INININININININININININININININ

BIBIBIBIBIBIBI

INBI

BIBIBIBIBIBIBIBI

IN

BIBI

APPLE INC

NONESCALE

"Factory" (top) slot

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Signal aliases required by this page:

6.3V 402-LF 20%

0.1UF

402-LF 20%

10K

MF-LF 5%

402

2.2UF

20%

CERM 402-LF 6.3V

10UF

20%

6.3V603

6.3V

10UF

X5R

CERM40210V

402CERM10V

20%

402CERM

0.1UF

20%

402CERM 10V

0.1UF

20%

402CERM 10V

0.1UF

20%

402CERM 10V

0.1UF

20%

402CERM 10V

402CERM

0.1UF

20%

402CERM 10V

0.1UF

20%

402CERM

SYNC_MASTER=DDR SYNC_DATE=07/22/2008

DDR3 SO-DIMM Connector A

051-7546 A.0.0

9628

107

8483

119

8078

9695

9291

908689

85

109

10879

115

101103

102104

141143

130132

140142

147149

157159

146148

158160163

165

175177

164166

174176

181183

191193

180182

192194

137135

154152

171169

188186

198

77

122116120

110114

144145

150151

172173

178179

184185

C3130

1 2

3335

2224

343639

41

5153

15

4042

5052

5759

6769

565817

6870

46

161821

23

1210

2927

4745

6462

5455

8

6061

C3135

1 2

R3141

1 2

R3140

1 2

C3140

1 2

C3100

12

C3101

12

C3110

12

C3111

12

C3112

12

C3113

12

C3114

12

C3115

12

C3116

12

C3117

12

C3118

12

C3119

12

C3120

12

C3121

12

C3122

12

C3123

12

Trang 29

BIBIBIOUTBIIN

IN

ININININININ

ININININININININ

BIBIBIBIBIBIBI

INBIBIBIBIBIBIBIBI

IN

BIBI

BIBIIN

VDDA1A3VDDA5A8VDDA9

VDDA12/BC*

VSS

DQ42DQ43DQ48DQ49VSS

VSSDQ41DQS4*

DM5

VDDCKE1A15A14VDDA11A7A6VDDA4A2

CK1

A0VDD

VDDCK1*

VDDRAS*

BA1

ODT0S0*

NCODT1VDD

VREFCAVDD

DQ36DQ37VSS

DM4VSSVSSDQ38DQ39

DQ45DQ44VSS

DQS5*

VSS

CKE0VDDNCBA2

CK0

VDDBA0WE*

A13S1*

VDD

VDDTEST

DQ33DQ32VSS

DQ34

DQ40VSS

DQ46VSSDQS5

VSSDQ47DQ52VSSDQ53

VSSDM6DQ54DQ55VSS

VSSDQ61DQ60

DQS7DQS7*

DQ63

VSSDQ62

EVENT*

VSS

VTTSCLSDA

VSS

DQS6DQS6*

VSSDQ51DQ50

A10/APVDDCK0*

DQ35VSSDQS4VSSCAS*

VDD

DM7VSSDQ56

MTG PIN

MTG PINMTG PIN MTG PINMTG PIN MTG PIN

MTG PIN

VSSDQ57

VTTSA1SA0

DQ58VSSDQ59VSSVDDSPD

BIIN

BI

BIBIINBIBIBIBIBIBIBI

BI

DQ2DQ3

VREFDQ

DQ1DQ0

DM0

DQ9DQ8

DQS1*

DQS1DQ10DQ11

DQ17DQS2*

DQS2DQ18DQ19

DQ25DQ24

DQ5DQS0*

DQS0DQ6DQ7DQ12DQ13DM1RESET*

DQ14DQ15DQ20DQ21DM2DQ22DQ23DQ28DQ29DQS3*

DQS3DQ30DQ31DQ4

DQ27DQ26DM3

DQ16

VSS

VSSVSSVSSVSSVSS

VSSVSS

KEY

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSS

VSS

INBIBIBIBIBI

BI

BIBI

BIBIBIBIBI

INININ

BI

INININININININININININ

BIBIBIBIINBIBI

IN

BIBIIN

BIBIBIBIBIBIBIBIBI

BIIN

BIBIBIBI

APPLE INC

NONESCALE

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

2.2UF

10K

1/16W 5%

402

10K

5%

402 MF-LF

2.2UF

6.3V 402-LF CERM 20%

6036.3VX5R

20%

CERM402

0.1UF

40210V

15

20%

CERM402

0.1UF

CERM40220%

0.1UF

CERM40220%

0.1UF

10V

CERM40220%

0.1UF

10V

CERM40220%

0.1UF

10V

CERM40220%

0.1UF

10V

0.1UF

CERM40220%

0.1UF

10V

CERM40220%

0.1UF

10V

CERM40220%

2.2UF

6.3V 20%

107

8483

119

8078

9695

9291

908689

85

109

10879

115

101103

102104

141143

130132

140142

147149

157159

146148

158160163

165

175177

164166

174176

181183

191193

180182

192194

137135

154152

171169

188186

198

77

122116120

110114

144145

150151

172173

178179

184185

C3230

1 2

3335

2224

343639

41

5153

15

4042

5052

5759

6769

565817

6870

46

161821

23

1210

2927

4745

6462

5455

8

6061

C3235

1 2

R3241

1 2

R3240

1 2

C3240

1 2

C3200

12

C3201

12

C3210

12

C3211

12

C3212

12

C3213

12

C3214

12

C3215

12

C3216

12

C3217

12

C3218

12

C3219

12

C3220

12

C3221

12

C3222

12

C3223

12

Trang 30

OUT

APPLE INC

NONESCALE

3.3V input must be stable before

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

DDR3 RESET Support

1/16W5%

MF-LF

1K

402

CERM20%

0.1UF MEMRESET_HW

40210V

5%

10K MEMRESET_HW

1/16W402

16

MEMRESET_MCP

MF-LF5%

1/16W

0

402

MMDT3904-X-G MEMRESET_HW

SOT-363-LF

MF-LF

20K

4025%

1/16W402

DDR3 Support

30 96

A.0.0051-7546

Trang 31

ININ

Y B A

MOSFET

P-TYPE FDC606P

0.8 A (EDP)

26 mOhm @4.5V 5V S3 WLAN FET

750 mA nominal max 1000 mA peak

AIRPORT

518S0610

206 mA nominal max

ALS CAMERA

USB_CAMERA_P CONN_USB2_BT_N

USB_BT_P USB_BT_N

=PP5V_S3_WLAN

P5VWLAN_SS

PP5V_WLAN_F

VOLTAGE=5VMIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.5 mm

CONN_USB2_BT_P USB_CAMERA_CONN_P

MINI_CLKREQ_L

PCIE_MINI_R2D_C_N PCIE_MINI_R2D_C_P

USB_CAMERA_N

PCIE_CLK100M_MINI_CONN_N PCIE_MINI_R2D_N

PCIE_MINI_R2D_P PCIE_MINI_D2R_N PCIE_MINI_D2R_P

PCIE_MINI_PRSNT_L

PP5V_S3_BTCAMERA_F

VOLTAGE=5VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

MINI_CLKREQ_Q_L

Right Clutch Connector

31 96

A.0.0051-7546

SYNC_MASTER=YITE_M98_MLB SYNC_DATE=07/02/2008

PLACEMENT_NOTE=Place close to J3401

10VCERM402

0.1uF

4025%

1/16W

0.033UF

16V402

X5R

0.1UF

16V402

62K

1/16W5%

MF-LF402

5%

33K

1/16W402

20%

10UF

80510V

0.1uF

16V

0.1uF

10V402CERM

C34201

1 2

C345112R3450

1 2

R34511

2

C342212

L3404

1 2

54

U3402

2

3 1

54

L3401

34

L3402

34

L3403

34

Q3401

6

21

Q3401

3

54

Trang 32

NCNC

OUTOUT

ININOUT

OUT

NCNCNCNC

VENICE

10% 16V

0.1uF

402X5R

10uF

X5R

0.1uF

16V10%

DLP11S90-OHM-100MA

0.1uF

16VX5R40210%

VENICE

74HC1G00GWDGSC70-5

1/16W5%

402MF-LF0

CRITICAL TPS2231

QFN

10uF

X5R6.3V

0.1uF

CERM40220%

X5R

10uF

60320%

6.3V

0.1uF

CERM40220%

CERM

0.1uF

40220%

402

100K

MF-LF1%

1/16W

0.1uF

CERM40220%

0

40216V

0.1uF

SN74LVC1G04YZPR

BGA

6.3V20%

603

10uF

42 43

74HC1G00GWDGSC70-5

EXCARD_CPUSB_L

PLT_RESET_SWITCH_L PP3V3_S0_EXCARD_SWITCH

EXCARD_CPPE_L PCIE_CLK100M_EXCARD_CONN_P

PCIE_EXCARD_D2R_N

=SMBUS_EXCARD_SCL

PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N

EXCARD_CPPE_L EXCARD_CPUSB_L

PCIE_CLK100M_EXCARD_CONN_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=.3mm MIN_NECK_WIDTH=0.2mm

USB2_EXCARD_CONN_P PP1V5_S0_EXCARD_SWITCH PCIE_EXCARD_R2D_P

FC_RESET_L FC_PRSNT_L

=PP1V5_FC_CON

=PP3V3_FC_CON

PCIE_FC_D2R_N PCIE_FC_D2R_P PCIE_FC_R2D_N PCIE_FC_R2D_P PCIE_CLK100M_FC_N PCIE_CLK100M_FC_P FC_CLKREQ_L

PCIE_EXCARD_PRSNT_L

PCIE_EXCARD_R2D_N PCIE_CLK100M_EXCARD_P

EXCARD_CPPE_L PCIE_CLK100M_EXCARD_CONN_P

EXCARD_CLKREQ_L

402PLACEMENT_NOTE=Place close to J3500

45131416

19

8

18

2016

21

122

113

C35011

2

C35041

2

C35051

2

C35021

2

C35031

2C35001

2

C35351

2

C35341

2

C35311

2

C35301

2

C355012

R35611

2

C356012

R3500 1 2

U3561B1

C1

A2C2

U3560

321

45

J3500

1

1011121314151617

1819

2

202122232425262728

29

3456789

C35711 2

L3503

34

C3570

1 2

J3501

2324

2526

45

Trang 33

IN

INBI

IN

BI

BIBI

BIBIBIBIBI

OUT

OUTOUTOUTOUT

MDI-[3]

LED1/PHYAD1LED2/RXDLYLED0/PHYAD0

CLOCKRESET

LED

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D

PLACE R3796 CLOSE TO U1400, PIN D24

Alias to GND for external 1.05V supply.

Alias to =PP3V3_ENET_PHY for internal switcher.

WF: Marvell numbers, update for Realtek

If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

PHYAD = 01 (PHY Address 00001)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect)

(19mA typ - Energy Detect) (43mA typ - 1000base-T)

If internal switcher is not used, VDDREG and REGOUT can float.

Configuration Settings:

Hence, RC (R3725 and C3725) are made NOSTUFF.

ENET_RESET_L is not asserted when WOL is active.

per RealTek request.

Reserved for EMI

TXDLY = 0 (No TXCLK Delay)

AN[1:0] = 11 (Full auto-negotiation)

RXDLY = 0 (RXCLK transitions with data)

0

4021/16W5%

MF-LF

NO STUFF 10V

CERM40220%

0.1UF

2.49K

MF-LF1%

1/16W402

NO STUFF

5%

4.7K

402MF-LF

10K

MF-LF4025%

1/16W

CRITICAL FERR-120-OHM-1.5A

0402-LF

0.1UF

16V402

16V40210%

0.1UF

16V40210%

22

402

402MF-LF1/16W5%

22

402MF-LF1/16W5%

22

402

22

MF-LF1/16W5%

402

22

MF-LF1/16W5%

402

22

MF-LF1/16W5%

1/16W

402

4.7K

MF-LF5%

1/16W

9

402MF-LF5%

0.1UF

16V40210%

16V402

0.1UF

16V40210%

CERM50V

10PF

22

MF-LF4021/16W5%

18

91

OMIT RTL8211CLGR

TQFP

Ethernet PHY (RTL8211CL)SYNC_MASTER=SUMA_M98_MLB

A.0.0

33 96051-7546

ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK

ENET_TX_CTRL

=PP3V3_ENET_PHY

ENET_TXD<2>

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM

R3724

C3725

12

2

C37061

2

C37001

2

C37011

2

C3702

12

R3790 1 2R3791 1 2R3792 1 2R3793 1 2R3794 1 2

L3715

1

2

C371112C37101

2

C371412

C379012

30

21

54

98

1211

27

23242526

Trang 34

DS

OUT

D

SG

D

SG

D

SG

D

SG

IN

D

SG

IN

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D

ARB for alternate power options.

=P3V3ENET_EN Nets separated on Recommend aliasing PM_SLP_RMGT_L and

1.05V ENET FET WLAN Enable Generation

Recommend aliasing PM_SLP_RMGT_L and

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

RTL8211 25MHz Clock

ARB for alternate power options.

=P1V05ENET_EN Nets separated on

I(max) = 1.7A (85C)

3.3V ENET FET Rds(on) = 90mOhm max

MOBILE:

@ 2.5V Vgs:

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

10%

CERM16V402

0.01UF

0.033UF

10%

40216V

1/16WPLACEMENT_NOTE=Place close to U1400

33 91

0.01UF

16VCERM402

SI2312BDS

SOT23

CRITICAL

MF-LF4021/16W

10K

402MF-LF5%

SYNC_MASTER=SUMA_M98_MLB SYNC_DATE=07/01/2008

=P3V3ENET_EN

PM_SLP_S3_L SMC_ADAPTER_EN

AC_OR_S0_L AP_PWR_EN

C3810

12

C38111

2R3810

C384012

Trang 35

RXTX

BI

RX

TX

BIBI

APPLE INC

NONESCALE

Page Notes

BOM options provided by this page:

MF-LF

75

4021/16W5% 1/16W5%

402MF-LF

402MF-LF5%

1000PF CRITICAL

120610%

33

16V

0.1UF

X5R 10%

0.1UF

402 16V 10%

0.1UF

16V 402

96

Ethernet ConnectorSYNC_MASTER=SUMA_M98_MLB SYNC_DATE=07/01/2008

ENET_BOB_SMITH_CAP

ENETCONN_N<2>

ENET_CTAP2

ENET_CTAP1 ENET_CTAP0 ENETCONN_P<0>

ENET_MDI_P<3>

ENET_MDI_N<3>

ENET_CTAP3 ENET_MDI_P<2>

3

45

89

T3900

1

1011122

3

45

89

R39001

2R39011

2

R39021

2

R39031

1 2

C3906

12

C3904

12

C3902

1 2

C3900

1 2

J3900

110

1112

2345678

Trang 36

ATBUSHATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMSTCKREFCLKNPCIE_TXD0P

AVREGCE

CLKREQN

FW_RESET*

FW620*

JASI_ENMODE_ANAND_TREE

OCR_CTL_V12

PCIE_RXD0NPCIE_RXD0PPCIE_TXD0N

SCLSDASE

SM

TDOTPA1N

TPA2NTPA2PTPB0NTPB0PTPB1NTPB1PTPB2NTPB2PTPBIAS0TPBIAS1TPBIAS2

DS0

TPA1P

VDD33VDD10

VREG_VSSVSS

CHIP RESETSCIF

1394 PHY

NCNCNC

NC

ININ

OUTOUT

OUT

INININBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

IN

NCNC

APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D

NAND tree order.

NOTE: NT-xx notes show

NT-10 (IPD)

(IPD) NT-18

NT-12 (IPD) NT-13

FIXME!!! - TYPO IN SYMBOL REGCTL

(IPU) (IPD) NT-21

(IPU)

(IPD) NT-20 (IPD) NT-19

(IPD) NT-9

NT-2 (IPU)

(OD)

NT-4 (IPU) NT-3 (IPU) NT-1 (IPU)

(IPU) NT-8 (IPD) NT-11

NT-15 (IPD)

191

1%

1/16W402

CERM-X5R

0.33UF

6.3V40210%

CERM

22PF

5%

50V402

50V5%

22PF

CERM402

390K

MF-LF5%

1/16W402

412

MF-LF1%

1/16W402

10K

MF-LF5%

1/16W402

10K

MF-LF5%

1/16W402

0.1UF

PLACEMENT_NOTE=Place C4175 close to U4000

16VX5R 40210%

10K

MF-LF5%

1/16W402

0.1UF

PLACEMENT_NOTE=Place C4171 close to U1400

16VX5R 40210%

0.1UF

PLACEMENT_NOTE=Place C4170 close to U140016V

X5R 40210%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1UF

10%

CERM402

1/16W402

SYNC_MASTER=SENSORFireWire LLC/PHY (FW643)

PP3V3_FW_FWPHY_VDDA

PCIE_FW_R2D_C_N

FW_P0_TPA_N FW_P0_TPA_P

PP3V3_FW_FWPHY_VP25

FW_CLK24P576M_XO_R

FW_P2_TPBIAS FW_P0_TPBIAS FW_P2_TPB_P FW_P2_TPB_N FW_P1_TPB_P FW_P1_TPB_N FW_P0_TPB_N FW_P2_TPA_P FW_P2_TPA_N

FW_P1_TPA_N FW_P1_TPA_P

FW_RESET_L

TP_FW643_MODE_A

TP_FW643_JASI_EN TP_FW643_FW620_L

FW643_TPCPS

=PPVP_FW_PHY_CPS

FW_CLK24P576M_XI FW_CLK24P576M_XO

2R41621

2

U4100B13

A13A11

A10L13

L2

F12E12E13

D12

K13D1J2K1

J12J13

N8N7N5N6

N4B11

N9N10

D13

L8

G2G1H1F2

N12M11M13

N13

M4N2M1M3

B8A8B5A5B3A3B9A9B6A6B4A4B7C3A2

B10

N1

E1D2

H13A1 B1 B12 C13 E2 E10 H2 H12 K2 L1 M12 N3 N11 C1 C12 F1 G12 J1 L3 L11 M2 A12 D5 D6 D8 L5 L10 L6 L9 K12

2

R41641

2

R41651

2

C41761 2C41751 2

R41661

2

C41711 2C41701 2

C413012C413112

C41001

2

C41011

2

C413212

C41021

2

C41031

2

C413512C413612

C41041

2

C41101

2

C41051

2

C41061

2

C412012C412112C412212C412312C412412

C414112

C41111

2

C41401

Trang 37

V-D

SG

ININ

D

SG

D

G S

APPLE INC

NONESCALE

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PPVP_FW_SUMNODE (power passthru summation node)

Late-VG Event Detection

2.81V on late Vg event and port power is off

FireWire Port Power Switch

Enables port power when machine

200K

1%

MF-LF4021/16W

50V

100pF

10K

MF-LF1%

402

80.6K

MF-LF402

16V402CERM

0.01uF

402

470K

1/16W5%

MF-LF

SSM6N15FEAPE

SOT563

MF-LF402

=PP3V3_FW_LATEVG_ACTIVE

P2V4_FWLATEVG_RC

LATEVG_EVENT_L FWLATEGV_3V_REF

MIN_NECK_WIDTH=0.25 mm

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mmVOLTAGE=12.6V

PP2V4_FW_LATEVG

=PPBUS_S5_FWPWRSW

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=12.6V

1812L15024HF

PPBUS_FW_FWPWRSW_F

R42191

2

C42191

2

C42101

2

R4210

1 2

U42104

3

1

52

R42111

2

C421112

R42121

2

R42131

2

D421912

Q4260

5678

4123

C426012

R42601

2

Q4261 3

R42611

Trang 38

GND CHASSIS

SHLD CABLE OUTER TPA+ TPA(R) TPA- VG NC

VP TPB+

TPB(R) TPB-

DRAWING NUMBER

SHT OF

SIZE

D

constrained on this page It is

provide the appropriate constraints

Configures PHY for:

"Snapback" & "Late VG" Protection

NOTE: This page is expected to contain

FireWire PHY Config Straps

- 1-port Portable Power Class (0)

PP2V4_FWLATEVG needs to be biased

to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4390 should be 390 Ohms max for a 3.3V rail

assumed that FireWire PHY page will

to apply to entire TPA/TPB XNets.

Termination

FW spec calls out 0.33uF

Place close to FireWire PHY

TI PHYs require 1uF even though

appropriate connectors and/or to

NOTE: FireWire TPA/TPB pairs are NOT

Cable Power

(GND_FW_PORT1_VG) (FW_PORT1_BREF)

AREF needs to be isolated from all

INPUT

NC

VPTPB+

TPB<R>

TPB-TPA<R>

TPA-VGNC

TPA+

ESD and late-VG rail

local grounds per 1394b spec

(Common to all ports)

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

the necessary aliases to map the

FireWire TPA/TPB pairs to their

- =GND_CHASSIS_FW_PORT1

PORT 1 Note: Trace PPVP_FW_PORT1 must handle up to 5A

BOM options provided by this page:

properly terminate unused signals.

SIGNAL_MODEL=EMPTY

56.2

MF-LF402

1%

1/16W

MF-LF4021/16W1%

4.99K

SIGNAL_MODEL=EMPTY1%

1/16W402

56.2

220pF

CERM4025%

25V

1%

56.2

MF-LF402SIGNAL_MODEL=EMPTY

0.33UF

CERM-X5R6.3V10%

402

1/16W1%

MF-LF402

56.2

SIGNAL_MODEL=EMPTY

50V603-1X7R

0.1uF

PLACEMENT_NOTE=Place C4319 close to connector pin 5

MF-LF402

0.01uF

50V402

1/16W1%

402MF-LF

F-RT-TH1

MF-LF402

1%

1/16W

10K

4021/16W1%

470K

1/16W5%

402MF-LF

SYNC_DATE=08/14/2008SYNC_MASTER=SENSOR

NC_FW2_TPBPMAKE_BASE=TRUE

FW_P2_TPB_P

NC_FW2_TPBNMAKE_BASE=TRUE

FW_P0_TPA_P FW_P2_TPA_N

MAKE_BASE=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P FW_PORT1_TPA_N

MIN_LINE_WIDTH=0.5 mm

FW_P2_TPB_N FW_P0_TPB_N

FW_P0_TPA_N FW_P2_TPBIAS FW_P0_TPBIAS

2

C43641

2

R43611

2

C43601

2

R43601

2

C431912

R43191

2

C43141

2

L4310

C431012DP4310

1

26

C431112DP4310

4

53

2

C431212

R4390

1 2

D4390

13

J4310

1

101112131415

2

3456789

Trang 39

D

SG

D

SG

NCNCNC

SYM_VER-1

OUTOUT

ININ

APPLE INC

NONESCALE

PLACEMENT_NOTE=Place FL4520 close to J4500

CRITICALDLP11S90-OHM-100MA

0.068UF

10V

16VCERM402

0.01UF

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

402CERM10% 16V

0.01UF

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

402

0.1UF

DLP11S90-OHM-100MA

CRITICAL

40210V

SATA Connectors

39 96

A.0.0051-7546

SATA_ODD_R2D_N

ODD_PWR_EN_LS5V_L

SATA_HDD_R2D_UF_P

SATA_HDD_D2R_UF_PSATA_HDD_D2R_C_P

SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_PSATA_ODD_R2D_UF_P

PLACEMENT_NOTE=Place C4510 close to MCP79PLACEMENT_NOTE=Place C4511 next to C4510

23456789

FL4520

12

FL4525

34

Q4596 3

54

2021

22

3456789

L4500

C4501

12

FL4501

12

C4502

12

FL4502

34

Trang 40

IO NC IOGNDVBUS NC

OUT2

TPADGND

OUT1OC1*

EN2EN1OC2*

IN

VCC

GNDSELOE*

D+

D-Y+

M+

Y-

M-APPLE INC

NONESCALE

DRAWING NUMBER

SHT OF

SIZE

D

We can add protection to 5V if we want, but leaving NC for now

USB/SMC Debug Mux

Left USB Port B

Left USB Port A

Place L4600 and L4605 at connector pin

514-0606

Port Power Switch

SEL=0 Choose SMC SEL=1 Choose USB

0603

FERR-220-OHM-2.5A CRITICAL

CASE-B2-SMPOLY-TANT

0.1UF

402CERM10V

0.1UF SMC_DEBUG_YES

0

MF-LF

SMC_DEBUG_NO

SMC_DEBUG_NO 0

4025%

1/16W

16V402

0.01uF

CERM20%

402CERM16V

CRITICAL

6.3VX5R

10UF

60320%

CASE-B2-SM6.3VPOLY-TANT

100UF CRITICAL

SLP1210N6

CRITICAL RCLAMP0502N

603

10UF

X5R20%

6.3V

USB

CRITICALF-RT-TH-M97-3

F-RT-TH-M97-3USB

CRITICAL

MSOPTPS2064DGN

4021/16W

5.1K

MF-LF5%

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.375 mmVOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

PP5V_S3_RTUSB_B_F

VOLTAGE=5VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.375 mmVOLTAGE=5V

SMC_RX_L SMC_TX_L

USB_EXTB_P

PP5V_S3_RTUSB_A_ILIM

MIN_NECK_WIDTH=0.375 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=5V

2C469512

C46911

2

C465012

R46501

2

L4600

34

C4615

12

C4617 1

2C4616

12

D4600

1

5 4

2 36

D4610

1

5 4

2 36

C469012

J4600

1234

56

78

J4610

1234

56

78

Q4690

34

1

285

7

6

9

R46901

2

C469212

U4650

67

45

21

Tiêu đề	Apple Macbook Pro A1286 Late 2008 Early 2009 Laptop Logic Board Schematic Diagram
Thể loại	Sơ đồ
Năm xuất bản	2008

Định dạng
Số trang	96
Dung lượng	1,74 MB