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Tiêu đề Apple Macbook A1181 K36C Mlb
Thể loại Schematic
Năm xuất bản 2009
Thành phố unknown
Định dạng
Số trang 76
Dung lượng 1,31 MB

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TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITE

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TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DO NOT SCALE DRAWING

CK APPD

DATE

ENG APPD

DATE

1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2 ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLESTABLE_TABLEOFCONTENTS_ITEM

QTY

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

K36C MLB SCHEMATIC

APR/10/2009

051-8089 SCHEM,MLB,K36C

MCP79 A01 Silicon Support

MCP HDA & MISC

Date (.csa)

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APPLE INC. SCALE

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DIMM’s

Boot ROMSPI

J4501 J5800

J4810

U6610,6620,6630 U6801

Speaker

PG 57

Amps

J3900 U3700

J9001

J4500 J4501

Connectors

PG 39

SMB CONN

SMC

B,0

Prt BSB

PWR

Misc

Port80,serialLPC Conn

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APPLE INC. SCALE

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

EN

PVIN

1.5V (S0) TPS62510

17 06

SLP_S4_L(P94)

CPUVTTS0_PGOOD

TPS51116 U7300

U7400

VR_ON

IMVP_VR_ON

LT3470VOUTPP3V42_G3H_REG

SMC PWRGD

SMC_RESET_L RN5VD30A-F

CPUVTT

MCP_PS_PWRGD

U1400 U2850

ENABLESVIN

3.3V TPS51125

(23A MAX CURRENT)

(4.5A MAX CURRENT)

SN0802043

PP5V_LT_S3_PGOOD MCPCORES0_PGOOD PP5VLT_S3

MCPCORES0_PGOOD

P5V_LT_S3_PGOOD

P1V5_S0_PGOOD P5V3V3_PGOOD

04-1

EN

VOUT1PGOOD1

PGOOD2

SLP_S3_L(P93)SMC_ONOFF_L

OVT

PWR_BUTTON(P90)P17(BTN_OUT)

K36B POWER SYSTEM ARCHITECTURE

25

PVIN

TPS62510 1.05V (S5)

PGOOD

ISL9504B

VIN

109 3

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CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_ITEM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC THE POSSESSORAGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEMCRITICAL BOM OPTION

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM

ALTERNATES OPTION BOM OPTION

BOARD STACK-UP AND CONSTRUCTION

(NONE)

(NONE)

BOTTOM 11 10 9 8 7 6 5 4 3 2

SIGNAL(High Speed) POWER

SIGNAL(High Speed) SIGNAL(High Speed)

POWER GROUND GROUND

GROUND SIGNAL

SIGNAL(High Speed) SIGNAL

GROUND

(NONE)

BOM options provided by this page:

Top

Signal aliases required by this page:

Power aliases required by this page:

ALTERNATE PER CYNDIALL

1

514-0667 CONN,RCPT,3.5MM AUDIO OUT,R/A

J3900CONN,RCPT,RJ45,NO FILTER,8P

338S0694

341S2420 1 IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK U4900 CRITICAL SMC_PROG

341S2418 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_PROG

341S2093 1 IC, CYPRESS, CY7C63833 U4800 CRITICAL

338S0654 1 IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127 U4100 CRITICAL

IC,GMCP,MCP79,35X35MM,BGA1437,B03

1

338S0702

J4600CONN,RCPT,USB,4P,MIDPLANE

SYNC_MASTER=K36B_MLB

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APPLE INC. SCALE

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT OF

SIZE

D

- CHANGE R1440 TO 150_5% AND NO STUFF

- RTC FOLLOW M97 DESIGN AND USE SUPERCAP SOLUTION

- U1000 CHANGE FROM 373S3646 TO 373S3702

- NETNAME ENET_INTR_L CHANGE TO TP_ENET_INTR_L

- DELETE R1987,R1988,R1995,R1970,R1971,R1972,R1973,R1996,R1997,R1998,R1999,R1978,R1979

- NET LVDSMUX_SEL_IG_L SYNC M97 NETNAME

- REMOVE NET DIMM_OVERTEMPA_L

- REMOVE NET DIMM_OVERTEMPA_LPAGE 42:

- ADD SMC_EXCARD_PWR_EN TO TP_SMC_EXCARD_PWR_EN

- ADD SMC_RSTGATE_L TO TP_SMC_RSTGATE_L

- ADD ALS_GAIN TO NC_ALS_GAIN

- PULL R3240 DOWN TO GND PULL R3241 HIGH

CHANGE CSA BASE ON WILL’S SUGGESTION

- NET DPMUX_SEL_IG_L SYNC M97 NETNAME

- NET DPMUX_LOWPWR_L SYNC M97 NETNAME AUD_IPHS_SWITCH_EN

- ENET_PWRDWN_L CHANGE TO TP_ENET_PWRDWN_L

(FOLLOW M97 DESIGN)

*****2008/10/30*****

- J6950 516S0735 CHANGE TO 516S0620PAGE 69:

- C7321 FROM 128S0111(POLY) CHANGE TO 128S0218 (POLY,CASE-D2E-SM)

- XDP FOLLOW M97 DESIGN CONNECTOR FROM 998-1571 CHANGE TO 516S0625

- I2C_ALS_SDA CHANGE TO I2C_MINI_PCIE_SDA

- I2C_ALS_SCL CHANGE TO I2C_MINI_PCIE_SCL

- ADD R3731 (116s0026 22 ohm 5% 0402) FOR EMI 125MHZ NOISE

- C6830/C6831 CHANGE TO APN 128S0220, and REMOVE BOMOPTION OMIT

- C6605 CHANGE TO APN 128s0148, HF APN 128s0221, and REMOVE BOMOPTION OMIT

- C6601/C6603 CHANGE TO APN 128S0135, and REMOVE BOMOPTION OMIT

- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE

- R5417 ADD BOM OPTION FOR NO STUFF

- DELETE R2400~R2413 FOR MCP A01 VERSION

- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE

- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE

- R4690 FROM NO STUFF CHANGE TO STUFF

- R5416 ADD BOM OPTION FOR NO STUFF

- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE

- ADD SMC_ANALOG_ID TO NC_SMC_ANALOG_ID

- ADD SMC_SYS_KBDLED TO NC_SMC_SYS_KBDLED

- ADD R5054 10KOHM LINK SMC_GPU_ISENSE PULL DOWN TO GND

- R5142 CHANGE TO NO STUFF

PAGE 46:

- ADD =PP1V05_ENET_PHY LINK TO PP1V2R1V05_ENET

- ADD =PP3V3_S5_P3V3ENETFET LINK TO PP3V3_S5

MODIFY ALL NOSTUFF TO NO STUFF

- ADD R5055 10KOHM LINK SMC_NB_MISC_ISENSE PULL DOWN TO GND

PAGE 19:

PAGE 18:

- DELETE 1.05V S0 FET CIRCUIT

- U7500 PIN TONSEL LINK TO GND DIRECTLY

- U7500 PIN V5DRV1 LINK TO PP5V_S0_MCPREG_VCC

- ADD =PP3V3_ENET_PHY_VDDREG LINK TO TP_PP3V3_ENET_PHY_VDDREG

- FOLLOW M97 DESIGN

PAGE 26:

PAGE :PAGE 57:

- R5417 CHANGE TO 4.53K AND DELETE BOM OPTION

- R5416 CHANGE TO 4.53K AND DELETE BOM OPTION

- R1860 AND R1861 CHANGE TO PAGE 68

- C2504-C2507 FROM 138S0578(402) CHANGE TO 138S0614(402-1)

- R4150 FROM 118S0343 (0201) CHANGE TO 116S0056(0402)

- R0602 BOMOPTION FROM JTAG_1DEV CHANGE TO NO STUFF

- Q7320 FROM 376S0512 CHANGE TO 376S0652 (H-F)

- REMOVE ALT TABLE

- REMOVE ALT TABLEPAGE 94:

- CHANGE ODD CONNECTOR FROM 516S0720 TO 516S0719

- REMOVE J9001 PIN 20 AND PIN21 NET

- R5418 CHANGE TO 4.53K AND DELETE BOM OPTION

- REMOVE BOMOPTION TABLE OF R2903/R2905/R2909/R2911

- REMOVE K36 BOM OPTION TABLE AND ALT TABLE

- ADD GMUX_JTAG_TMS AND GMUX_JTAG_TDI IN MISC NC MCP79 ALIASES

- BOM change U1400 CHANGE FROM 338S0678 TO 338S0702

- C6210 CHANGE FROM 127S0062 TO 127S0108

PAGE 102:

- NETNAME FROM CHGR LOWCURRENT GATE CHANGE TO CHGR_LOWCURRENT_GATE

- NETNAME FROM CHGR LOWCURRENT REF CHANGE TO CHGR_LOWCURRENT_REF

02

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OUT

INININ

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

10987

12

1 11

10V402

JTAG_ALLDEV

CERM20%

0.1UF C0601

JTAG_ALLDEV

10K

5%

402MF-LF

2

402MF-LF

SYNC_DATE=08/17//2008SYNC_MASTER=K36B_MLB

JTAG Scan Chain

051-8089

=PP3V3_S0_XDP

XDP_TRST_L XDP_TMS

XDP_TCK XDP_TDI XDP_TRST_L

JTAG_MCP_TDO_CONN XDP_TCK

JTAG_MCP_TDO

XDP_TDO_CONN XDP_TMS

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APPLE INC. SCALE

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I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Need 4 TP

Need 3 TPNeed 4 TPNeed 4 TP

Need 6 TPNeed 4 TP

Need 4 TPNeed 2 TPNeed 2 TP

#J4500 SATA ODD

#J6703 Right SUB SPEAKER CONNECTOR

#J6702 Left SPEAKER CONNECTOR

# J5800 GEYSER AND DIMM0 REMOTE TEMP SENSORS

#J5520 CPU/MCP Thermal Sensor

I160 I161 I162 I163 I164 I165 I167 I168 I169 I170 I171 I172 I173 I174

I175 I176 I177 I178 I179 I180 I181 I182 I183 I184 I185 I186 I187

I188 I189 I190 I191 I192 I193 I194 I195 I196 I197 I198 I199

I200 I201 I202

I203 I204 I205 I206 I207 I208

I209 I210 I211 I212 I213 I214 I215 I216 I217 I218

I219 I220 I221 I222 I223 I224 I225 I226 I227 I228

I229 I230 I231 I232 I233 I234 I235 I236 I237 I238 I239

I240 I241 I242 I243 I244 I245 I246 I247 I248 I250 I251 I252 I253 I254 I255 I256 I257 I258

I259 I260 I261 I262 I263 I264 I265 I266 I267 I268

I269 I270 I271 I272 I273 I274 I275

I276 I277 I278 I279 I280 I281 I282 I283 I284

051-8089FUNC TEST

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APPLE INC. SCALE

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

(DDR PWR AFTER SENSE RES.)

(MCP VCORE AFTER SENSE RES)

051-8089Power Aliases

109 8

02

SYNC_MASTER=K36B_MLB

PP3V3_S3

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP1V8_S3

MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8VMIN_LINE_WIDTH=1.5 mmMAKE_BASE=TRUE

=PP1V05_S0_SMC_LS

PPVCORE_S0_MCP_R

MIN_LINE_WIDTH=0.6 MMVOLTAGE=1.05VMAKE_BASE=TRUE

=PP1V05_S0_FET

PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.3 MMMAKE_BASE=TRUEVOLTAGE=0.9V

=PPBUS_S5_FW_FET

=PPVTT_S3_DDR_BUF

PP5VLT_S3

MIN_NECK_WIDTH=0.2 MMVOLTAGE=5VMAKE_BASE=TRUE

PP1V0_FW

MAKE_BASE=TRUEVOLTAGE=1.0VMIN_NECK_WIDTH=0.2MM

PP3V3_S0

MIN_LINE_WIDTH=0.30MMVOLTAGE=3.3VMAKE_BASE=TRUE

PPBUS_G3H_CPU_ISNS

VOLTAGE=12.6VMIN_LINE_WIDTH=0.6MMMAKE_BASE=TRUE

PPBUS_G3H

MIN_NECK_WIDTH=0.25MMMAKE_BASE=TRUEMIN_LINE_WIDTH=0.5MMVOLTAGE=12.6V

PP3V42_G3H

MAKE_BASE=TRUEVOLTAGE=3.42VMIN_NECK_WIDTH=0.2MM

PP18V5_G3H

MAKE_BASE=TRUEVOLTAGE=18.5VMIN_NECK_WIDTH=0.3 MM

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUEVOLTAGE=1.05V

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 mmVOLTAGE=3.3VMAKE_BASE=TRUE

PP1V2R1V05_ENET

MAKE_BASE=TRUEVOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mm

PP1V05_S0

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM

PP0V9_S0

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9VMAKE_BASE=TRUE

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MMVOLTAGE=1.05VMAKE_BASE=TRUE

PP1V05_S5_REG

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05VMIN_LINE_WIDTH=0.6 MM

PP3V3_S5

VOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1.5 mm

MIN_NECK_WIDTH=0.2MMVOLTAGE=1.8VMIN_LINE_WIDTH=0.5MMMAKE_BASE=TRUE

PPVP_FW

MAKE_BASE=TRUE VOLTAGE=12.6V

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II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TABLE_5_HEADPART# QTY DESCRIPTION REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

MISC NC MCP79 ALIASES

UNUSED EXPRESS CARD LANE

BLUETOOTH

CPU HEATSINK STANDOFF SCREW HOLE

BUT, NEED CHANGE TO HIGH STANDOFF SYMBOLFOR LAYOUT PLACEMENT

0 0 0

UNUSED ADDRESS PINS

UNUSED USB PORTS

Screw Holes

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND

DCIN CONNECTOR CHASSIS GND

DP HOTPLUG PULL-DOWN

ROM FAILURE OVERRIDE

Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

MCP_SAFE_MODE SIGNAL TO SUPPORT

FW PULL-DOWN

USB ALIASES

UNUSED LVDS SIGNALS

LVDS ALIASES

DIP DIMM CONNECTOR CHASSIS GND

SATA,LVDS CONNECTOR CHASSIS GND

DIP DIMM CONNECTOR CHASSIS GND

I/O CONNECTOR CHASSIS GND

5%

47K

1/16W402

MF-LF402

R0940

1

2

OMIT STDOFF-4.5OD3.95H-1.1-3.2-TH Z0905

1

OMIT STDOFF-4.2OD3.95H-5.52R3.37-6B Z0903

1

7X7R2P3-5B

OMIT Z0902

1

6P5R2P6-7SQB

OMIT Z0907

1

CLIP-SM-M42EMI-SPRING

ZS0920

1

5R2P3-7SQBNP OMIT

Z0906

1

OMIT STDOFF-4.2OD2.15H-1.2-3.2-TH Z0912

1

OMIT STDOFF-4.2OD3.95H-5.52R3.37-6B Z0913

1

47K

1/16W402MF-LF

0

MF-LF402

R0920

20K

402MF-LF5%

2

0.01UF

16VCERM40210%

C0940

12

051-8089

109 02 9

SYNC_MASTER=K36B_MLB

SIGNAL ALIAS

?Z0903,Z0904,Z0905,Z0921 STANDOFF860-0964 4 THERMAL STANDOFF

Z0912STANDOFF WIRELESS

PCIE_FW_PRSNT_L

DP_HOTPLUG_DET

PEG_PRSNT_LPEG_CLKREQ_L

INVT_CHGND

MCP_MII_COLPCIE_EXCARD_D2R_P

SMC_MCP_SAFE_MODE

MCP_MII_RXERAUD_IPHS_SWITCH_EN

MEM_A_A<15>

MEM_B_A<15>

GMUX_JTAG_TDI

USB_EXTD_PUSB_EXCARD_P

=P3V3ENET_EN

=PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUEUSB_TPAD_P

TP_USB_EXTDP

MAKE_BASE=TRUE

MAKE_BASE=TRUEUSB_TPAD_N

TP_MEM_B_A15

MAKE_BASE=TRUEUSB_BT_P

MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUEGND_AUDIO_CODEC

PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE NO_TEST=TRUE

=PEG_D2R_N<15:0>

=PEG_D2R_P<15:0>

MAKE_BASE=TRUE NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

LVDS_IG_B_CLK_PLVDS_IG_B_CLK_NLVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<3:0>

USB_EXTC_N

MAKE_BASE=TRUENC_RTL8211_REGOUT

TP_USB_EXTCN

MAKE_BASE=TRUE

USB_MINI_PMAKE_BASE=TRUE

=USB_MINI_P

USB_MINI_NMAKE_BASE=TRUE

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

MAKE_BASE=TRUETP_PCIE_CLK100M_EXCARDN

Trang 10

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

ININININOUTIN

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BI

BIBIBIBIBIBIBI

BI

BIBIBIBIBIBIBI

BI

OUT

OUT

OUTOUT

OUT

IN

INININININ

ININININ

OUT

ININ

ININ

INININ

INOUT

BIBIBIBI

TEST7TEST6

BSEL0BSEL1BSEL2

DPRSTP*

DPSLP*

DPWR*

PWRGOODSLP*

THERMTRIP*

THERMDAPROCHOT*

DBR*

TRST*

TMSTDOTDITCKPREQ*

LINT1LINT0STPCLK*

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

PLACEMENT_NOTE (all 4 resistors):

CPU JTAG Support

402 MF-LF54.91/16W 1%

2

402 MF-LF 5%

MF-LF1K

Place within 12.7mm of CPU

2

402 MF-LF 1%

27.4

Place within 12.7mm of CPU

R1022

1 2

54.9

1%

1/16W 402

Place within 12.7mm of CPU

2

27.4

402 MF-LF 1%

Place within 12.7mm of CPU

R1020

1 2

NO STUFF

R1010

1 2

4021K

MF-LF 5%

2

54.9

1/16W 402 1%

R1090

1 2 402

54.9

MF-LF 1%

R1094

1 2

1/16W 5%

1K

MF-LF 402

R26 U26 AA1 Y1

E22 F24

J24 J23 H22 F26 K22 H23

N22 K25 P26 R23 E26

L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 G22

T25 N25

Y22 AB24 V24 V26 V23 T22 U25 U23 F23

Y25 W22 Y23 W24 W25 AA23 AA24 AB25

AE24 AD24 G25

AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 E25

AC22 AD23 AF22 AC23

E23 K24 G24

J26

L26

Y26

AE25 H26

C23 D25 C24 AF26 AF1 A26 C3

402 1%

Y2 U5 R3 W6

A6

U4 Y5 U1 R4 T5 T3 W2 W5 Y4 J4

U2 V4 W3 AA4 AB2 AA3

L5 L4 K5 M3 N2 J1

H1

M1

V1

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1 H5 F21

A5

G6 E4 D20

C4

B3

C6 B4

H4

AC2 AC1

D21

K3 H2 K2 J3 L1

C1 F3 F4 G3

M4 N5 T2 V3 B2 F6 D2 D22 D3

A3 D5

AC5 AA6 AB3

A24 B25 C7 AB5 G2

XDP_TDI

XDP_DBRESET_LXDP_TRST_LXDP_TMS

CPU_INIT_L

XDP_TCKXDP_BPM_L<4>

FSB_BPRI_L

FSB_RS_L<2>

FSB_RS_L<0>

FSB_ADS_LFSB_BNR_L

FSB_DEFER_LFSB_DRDY_LFSB_DBSY_L

TP_CPU_RSVD_D3TP_CPU_RSVD_D22TP_CPU_RSVD_D2TP_CPU_RSVD_V3TP_CPU_RSVD_M4CPU_NMICPU_INTRCPU_IGNNE_L

CPU_BSEL<2>

TP_CPU_TEST3CPU_GTLREF

TP_CPU_TEST5TP_CPU_TEST6TP_CPU_TEST7CPU_TEST4CPU_TEST2

FSB_HIT_L

CPU_IERR_LFSB_BREQ0_L

Trang 11

OUTOUT

VCC

VCCP

VCCA

VID0VID1VID2VID3VID4VID5VID6

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

44 A (SV Design Target)(CPU CORE POWER)

130 mA

NEED 1.5V POWER SOURCE

(CPU INTERNAL PLL POWER 1.5V)

100

402 MF-LF

B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 A10

C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 A12

D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 A13

E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 A15

AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 A17

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7

A18

AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 A20

AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 B7

AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

B26 C26

G21 V6

R21 R6 T21 T6 V21 W21

J6 K6 M6 J21 K21 M21 N21 N6

AF7

AD6 AF5 AE5 AF4 AE3 AF3 AE2

B11

W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 B13

AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 B16

AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 B19

AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 B21

AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 B24

AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 C5

AF21 A25 AF25 B1

C8 C11 C14 A11

C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 A14

D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 A16

E19 E21 F5 F8 F11 F13 F16 F19 F2 A19

F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 A23

J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 AF2

L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 B6

P3

P6 P21 P24 R2 R5 R22 R25 T1 T4

T26 U3 U6 U21 U24 V2 V5 V22 V25

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1001%

1/16W 402 MF-LF

R1100

1 2

02

11 109

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

CPU Power & Ground

Trang 12

APPLE INC. SCALE

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

CERM 805 6.3V 20%

22UFPlace inside socket cavity on secondary side

CRITICAL

C1206

1 2

PLACEMENT_NOTE=PLACE C1260 BETWEEN CPU & MCP79

330UF

2.0V 20%

CRITICAL

D2T-SM2 POLY-TANT

2 3

CERMPlace inside socket cavity on secondary side

6.3V 20%

CERMPlace inside socket cavity on secondary side

6.3V 20%

CERM

CRITICAL

Place inside socket cavity on secondary side

6.3V 20%

22UF

805

C1208

1 2 CERM

6.3V

CRITICAL

C1207

1 2 CERM

Place inside socket cavity on secondary side

6.3V 20%

80522UF

CRITICAL

C1202

1 2 CERM

CRITICAL

22UFPlace inside socket cavity on secondary side

805 20%

6.3V

C1201

1 2

CERM 20%

805

Place inside socket cavity on secondary side

22UF6.3V

CRITICAL

C1213

1 2 CERM 805Place inside socket cavity on secondary side

6.3V 20%

22UF

CRITICAL

C1212

1 2 CERMPlace inside socket cavity on secondary side

805

22UF20%

6.3V

CRITICAL

C1219

1 2

CERM

CRITICAL

22UFPlace inside socket cavity on secondary side

6.3V 20%

805

C1200

1 2

22UFCERMPlace inside socket cavity on secondary side

6.3V 20%

805

CRITICAL

C1210

1 2

20%

402 CERM 10V0.1UF

C1261

1 2

6.3V

CRITICAL

C1209

1 2

CERMPlace inside socket cavity on secondary side

805

22UF20%

6.3V

CRITICAL

C1217

1 2

20%

402 CERM 10V0.1UF

C1262

1 2

20%

402 CERM0.1UF10V

C1263

1 2

20%

402 CERM 10V0.1UF

C1264

1 2

20%

402 CERM 10V0.1UF

C1265

1 2

20%

CERM 10V0.1UF

402

C1266

1 2

CERM 20%

PLACEMENT_NOTE=PLACE C1250 C1251 NEAR CPU PIN B26

402 CERM 10%

0.01UF

C1251

1 2 20%

6.3V X5R10uF

2

Place on secondary side

D2T-SM2 POLY-TANT 2.0V 20%

330UF

CRITICAL

C1240

1 2 3

330UF

20%

CRITICAL

2.0V POLY-TANT D2T-SM2

Place on secondary side

C1241

1 2 3

Place on secondary side

330UF

20%

2.0V POLY-TANT D2T-SM2

CRITICAL

C1242

1 2 3

CRITICAL

330UF

2.0V D2T-SM2

Place on secondary side

20%

POLY-TANT

C1243

1 2 3

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

109 12

Trang 13

BIBI

BIBI

OUT

IN

BIINININ

OUT

OUTOUT

BIBIBIBI

BIBIBIBI

OUT

IN

ININ

INOUTOUTOUT

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

VCC_OBS_CD

DBR#/HOOK7NOTE: XDP_DBRESET_L must be pulled-up to 3.3V

TCK0

OBSDATA_A3OBSDATA_A1

OBSFN_C0

OBSDATA_C3

Mini-XDP Connector

Please avoid any obstructions

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDOOBSFN_D0

SCLSDA

TRSTn

HOOK3HOOK2HOOK1

TMS

OBSDATA_D0

TCK1

OBSDATA_B2OBSDATA_B3OBSFN_B0

ITPCLK#/HOOK5OBSDATA_D3

OBSDATA_B1OBSDATA_B0

OBSDATA_A2

OBSDATA_A0

OBSDATA_C1Use with 920-0620 adapter board to support CPU, MCP debugging

on even-numbered side of J1300

69 14 10

1/16W 5%

XDP

MF-LF 402

1/16W54.9

2

X5R 10%

60

9

109 02SYNC_MASTER=M99_MLB SYNC_DATE=01/08/2008

13

eXtended Debug Port(MiniXDP)

051-8089

FSB_CPURST_LCPU_PWRGD

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2TP_XDP_OBSDATA_B3

XDP_OBS20

PM_LATRIGGER_LJTAG_MCP_TCK

XDP_TCK

FSB_CLK_ITP_PMCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

MCP_DEBUG<4>

XDP_TMSXDP_TDI

XDP_DBRESET_LXDP_CPURST_LFSB_CLK_ITP_NTP_XDP_OBSDATA_B1

=PP3V3_S0_XDP

XDP_TDO_CONNXDP_PWRGD

Trang 14

OUTBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBI

BIBI

BIBI

BIBIBIBIBIBIBIBIBI

INBIOUT

OUTOUTOUT

OUTOUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUT

OUT

OUTOUTOUTOUTOUT

OUTOUTIN

BIBI

BCLK_IN_N

CPU_A20M#

CPU_NMICPU_INTR

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

402 MF-LF

R1436

1 2 1/16W 1%

402 MF-LF

MF-LF

R1435

1 2

NO STUFF

402 5%

1K

1/16W

R1422

1 2

NO STUFF

1K

402 MF-LF 5%

2

402 1/16W

402 1%

R1440

1 2

OMIT

MCP79-TOPO-B(1 OF 11) BGA

U1400

AK41 AJ40

G41 G42

AL42 AL43

AK42 AL41

AM40 AM39

AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33

AF41

AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AC34

AJ34 AL38 AL35 AN34 AR39 AN35

AE38 AE34 AC37 AE37 AE35 AB35

AD42

AE36 AK35

AD43

AA41

AE40 AL32

F41 D42 F42

AM42 AM43

Y43 W42

R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 Y40

AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 W41

R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 Y39

L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 V42

P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 Y41

K41 J40 H39 M43

Y42 P42 U41

AH39 AH42 AF42 AC43

AG41

E41 AJ41

AH43

AC38 AA33 AC39 AC33 AC35

H38

AC41 AB41 AC42

AM33 AH41

AG42

AG43 AE41

AG27

AH28 AG28 AH27

62

MF-LF 5%

402 1/16W

R1416

1 2

02

14 109

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

CPU_PECI_MCP

=PP1V05_S0_MCP_FSB

FSB_TRDY_LFSB_HITM_LFSB_HIT_LFSB_DRDY_LFSB_DBSY_LFSB_BREQ0_LFSB_BNR_LFSB_ADS_L

FSB_CLK_CPU_PFSB_CLK_CPU_NFSB_CLK_ITP_PFSB_CLK_ITP_N

CPU_A20M_L

CPU_STPCLK_LFSB_DPWR_LCPU_DPSLP_LFSB_CPURST_L

=MCP_BSEL<0>

=MCP_BSEL<1>

CPU_NMIPP1V05_S0_MCP_PLL_FSB

CPU_SMI_LCPU_PWRGD

FSB_CPUSLP_LMCP_BCLK_VML_COMP_VDD

Trang 15

0A MEMORY

CONTROL

MCKE0A_1MCKE0A_0

MODT0A_1MODT0A_0MCS0A_0#

MCS0A_1#

MCLK0A_0_NMCLK0A_0_PMCLK0A_1_N

MCLK0A_2_NMCLK0A_1_PMCLK0A_2_P

MA0_0MA0_1MA0_2MA0_3MA0_4MA0_5MA0_6

MA0_8MA0_7MA0_9MA0_10MA0_11

MA0_13MA0_12MA0_14

MBA0_2

MBA0_0MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_PMDQS0_0_N

MDQS0_1_PMDQS0_2_N

MDQS0_1_N

MDQS0_2_PMDQS0_3_N

MDQS0_4_P

MDQS0_3_PMDQS0_4_NMDQS0_5_NMDQS0_5_PMDQS0_6_NMDQS0_6_PMDQS0_7_NMDQS0_7_P

MDQM0_2MDQM0_1MDQM0_0

MDQM0_3MDQM0_4

MDQ0_0MDQM0_7

MDQM0_5MDQM0_6MDQ0_1

MDQ0_4MDQ0_3MDQ0_2

MDQ0_5MDQ0_6

MDQ0_9MDQ0_8MDQ0_7MDQ0_10MDQ0_11

MDQ0_15MDQ0_14MDQ0_13MDQ0_12MDQ0_16

MDQ0_21MDQ0_20

MDQ0_18MDQ0_19

MDQ0_17

MDQ0_25MDQ0_24MDQ0_23MDQ0_22MDQ0_26

MDQ0_29MDQ0_28MDQ0_27

MDQ0_30MDQ0_31

MDQ0_35MDQ0_34

MDQ0_40MDQ0_39MDQ0_42

MDQ0_47MDQ0_46

MDQ0_43

MDQ0_45MDQ0_44

MDQ0_51MDQ0_50MDQ0_49MDQ0_52

MDQ0_48

MDQ0_55MDQ0_54MDQ0_53

MDQ0_56MDQ0_57

MDQ0_61MDQ0_60

MDQ0_58MDQ0_59

MDQ0_62MDQ0_63

OUTOUTOUTOUTOUTOUTOUTOUTBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

OUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

BIBIBIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBI

BIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBI

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

OUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

MEMORY CONTROL 1A

MDQ1_63

MDQ1_60MDQ1_59MDQ1_62

MDQ1_58MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56MDQ1_55MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51MDQ1_50

MDQ1_48MDQ1_47MDQ1_46

MDQ1_43MDQ1_44MDQ1_45

MDQ1_42MDQ1_41

MDQ1_37MDQ1_38MDQ1_39

MDQ1_36MDQ1_35

MDQ1_32MDQ1_33MDQ1_34

MDQ1_31MDQ1_30

MDQ1_27MDQ1_28MDQ1_29

MDQ1_22

MDQ1_26MDQ1_25MDQ1_24MDQ1_23

MDQ1_17MDQ1_19MDQ1_20

MDQ1_18MDQ1_21

MDQ1_16

MDQ1_12MDQ1_13MDQ1_14MDQ1_15

MDQ1_11MDQ1_10

MDQ1_7MDQ1_8MDQ1_9

MDQ1_3MDQ1_6

MDQ1_2MDQ1_4MDQ1_5

MDQ1_1

MDQM1_6MDQM1_5

MDQ1_0MDQM1_7

MDQM1_4MDQM1_3

MDQM1_0MDQM1_1MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_NMDQS1_6_PMDQS1_7_N

MDQS1_5_NMDQS1_5_P

MDQS1_4_P

MDQS1_3_PMDQS1_4_N

MDQS1_2_PMDQS1_3_N

MDQS1_1_PMDQS1_2_N

MDQS1_1_NMDQS1_0_PMDQS1_0_N

MRAS1#

MCAS1#

MWE1#

MBA1_2MBA1_1MBA1_0

MA1_14MA1_13MA1_12MA1_11MA1_10MA1_9MA1_8MA1_7MA1_6MA1_5MA1_4MA1_3MA1_2MA1_1MA1_0

MCLK1A_2_P

MCLK1A_1_PMCLK1A_2_N

MCLK1A_0_PMCLK1A_1_N

MCS1A_1#

MCS1A_0#

MCLK1A_0_N

MODT1A_1MODT1A_0

MCKE1A_0MCKE1A_1

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTBI

OUTOUTOUTOUTOUTOUTOUT

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

U1400

AR19 AT19

AN19 AW21 AN23 AU15 AR23

AU19 AV19 AN21 AR21 AP21 AU21 AR22 AV21

AW17 AP19 AP23 AP17

AT23 AU23

BC20 BB20 AY24 BA24 AV33 AW33

AR18 AT15 AP35

AR35

AV31 AT31 AW37 AV37 AR33 AU31 AN31 AV29 AN29 AV27

AW38

AR31 AP31 AR29 AP29 AR27 AP27 AR25 AP25 AU27 AT27

AV38

AU25 AR26 AU13 AR14 AT11 AR11 AW13 AV13 AV11 AU11

AR38

AV9 AU9 AY5 AW6 AP11 AW9 AU8 AU7 AV5 AU6

AR37

AR5 AN10 AW5 AV6 AR7 AR6 AN7 AN6 AL7 AL6

AV39

AN9 AP9 AL9 AL8

AW39 AU37 AT37

AR34 AV35 AW29 AN27 AN13 AR10 AU5 AN5

AT39 AU39 AU35 AT35 AU29 AU30 AW25 AV25 AR13 AP13 AW8 AW7 AR9 AR8 AL11 AL10

AV15 AP15

AV17 AR17

U1400

BA18 BB25

BA17 BC28 AW28 BA14 BA29

BA25 BB26 BA26 BA27 AY27 BA28 AY28 BB28

BB17 BB18 BB29 BA15

BB30 AY31

AY19 BA19 BA22 BB22 BB42 BA42

BB16 BB14 AP42

AR41

BC40 BA40 AV41 AV42 AW40 BB40 AY39 BA38 BB36 BA36

AU41

AY40 BA39 AW36 BC36 AY35 BA34 BB32 BA32 AY36 BA35

AU40

AW32 BC32 BA12 AY12 BB9 BB8 AW12 BB12 BB10 BA9

AN40

AY8 BA7 BC4 BB4 BC8 BA8 BA5 BB5 BB2 BA3

AP41

AW3 AW4 BC3 BB3 AY3 AY4 AU3 AU2 AR3 AR4

AT41

AV3 AV2 AT3 AT4

AT40 AW41 AW42

AR42 AY43 BB38 BB34 BA11 AY7 BA2 AT5

AT43 AT42 AY42 BA43 BA37 BB37 BA33 BB33 AY11 BA10 BA6 BB6 AY1 AY2 AT1 AT2

AY15 BB13

AW16 BA16

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

Trang 16

MCLK1B_1_NMCLK1B_0_PMCLK1B_1_PMCLK1B_2_N

MRESET0#

GND55GND56GND57GND58

GND60GND59

GND61GND62GND63GND64

GND52GND53GND54GND51

GND49GND50GND48GND47GND46

GND44GND45GND43GND42GND41

GND39GND40GND38GND37GND36GND35

GND33GND34GND32GND31GND30

GND28GND29GND27GND26GND25GND24

GND18GND19GND17GND16GND15

GND13GND14

GND10

GND12GND11

GND8GND9GND7GND6GND5

GND2GND3GND4GND1

MEM_COMP_VDDMEM_COMP_GND

MODT0B_0MODT0B_1

MCKE0B_1MCKE0B_0

MCLK0B_0_N

MCS0B_0#

MCS0B_1#

MCLK0B_2_NMCLK0B_1_P

MCLK0B_0_PMCLK0B_1_NMCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE+V_VPLL

+VDD_MEM1+VDD_MEM2+VDD_MEM3+VDD_MEM4+VDD_MEM5+VDD_MEM6+VDD_MEM7+VDD_MEM8+VDD_MEM9+VDD_MEM10+VDD_MEM11

+VDD_MEM14+VDD_MEM15+VDD_MEM16+VDD_MEM17+VDD_MEM18+VDD_MEM19+VDD_MEM20

+VDD_MEM22+VDD_MEM21

+VDD_MEM23+VDD_MEM24+VDD_MEM25+VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31+VDD_MEM32+VDD_MEM33+VDD_MEM34

+VDD_MEM38+VDD_MEM39+VDD_MEM40+VDD_MEM41

+VDD_MEM43+VDD_MEM44+VDD_MEM45+VDD_MEM42

+V_PLL_DP

+VDD_MEM13+VDD_MEM12

+VDD_MEM28

+VDD_MEM37+VDD_MEM36+VDD_MEM35

GND21GND20

GND22GND23

MEMORY CONTROL 0B MEMORY CONTROL 1B

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

MF-LF 402

2

OMIT

BGAMCP79-TOPO-B

(4 OF 11)

U1400

AA22

AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AP12

AT25 AP30 AR36 AU10 F28 BC21 AY9 BC9 D34 F24 G30

G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P10

P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T10

T18 T20 AK11 T24 T26

T33 T34 T35 T37 T38 T6

T7 T9 U18 U20 U22

V10 V34 W5

AV23 AN25

BA30 BA31

BB21 BA21 BC24 BB24 AU34 AU33

AY20 BA20 BA23 AY23 BB41 BA41

AU17 AR15

BC16 BA13

AM41 AN41

AN17 AN15

AY16 BC13

AY32 U27

U28 T27

T28

AM17

AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AM19

AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AM21

AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AM23

AY26 AW19 AW24 BC25 AL30 AM31

AM25 AM27 AM29 AN16 BC29

109 16

02

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

TP_MEM_B_CS_L<2>

MCP_MEM_COMP_GND

TP_MEM_A_CLK4N

TP_MEM_A_CLK5PTP_MEM_A_CLK5N

TP_MEM_B_CLK5PTP_MEM_B_CLK5NTP_MEM_B_CLK4PTP_MEM_B_CLK4NTP_MEM_B_CLK3PTP_MEM_B_CLK3N

Trang 17

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7+AVDD0_PEX8

+AVDD1_PEX3+AVDD1_PEX2+AVDD1_PEX1+AVDD0_PEX13+AVDD0_PEX12+AVDD0_PEX10+AVDD0_PEX9

+AVDD0_PEX6+AVDD0_PEX5+AVDD0_PEX4+AVDD0_PEX3+AVDD0_PEX2+AVDD0_PEX1

+V_PLL_PEX+DVDD1_PEX2+DVDD1_PEX1+DVDD0_PEX8+DVDD0_PEX7+DVDD0_PEX6+DVDD0_PEX5+DVDD0_PEX4+DVDD0_PEX3+DVDD0_PEX2+DVDD0_PEX1

PE1_TX1_NPE1_TX2_P

PE1_TX0_NPE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_NPE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_NPE4_REFCLK_PPE3_REFCLK_NPE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_NPE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_NPE0_TX15_P

PE0_TX13_NPE0_TX14_P

PE0_TX12_NPE0_TX12_P

PE0_TX13_PPE0_TX11_NPE0_TX11_PPE0_TX10_N

PE0_TX9_NPE0_TX10_PPE0_TX8_NPE0_TX8_P

PE0_TX9_P

PE0_TX7_NPE0_TX7_PPE0_TX6_N

PE0_TX5_NPE0_TX6_P

PE0_TX4_NPE0_TX5_PPE0_TX3_NPE0_TX3_P

PE0_TX4_P

PE0_TX2_NPE0_TX2_P

PE0_TX0_N

PE0_TX1_NPE0_TX1_PPE0_TX0_P

PEX_CLK_COMP

PE1_RX3_NPE1_RX3_PPE1_RX2_N

PE1_RX0_NPE1_RX1_P

PE1_RX2_PPE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_NPE0_RX14_P

PE0_RX15_PPE0_RX14_N

PE0_RX15_N

PE0_RX12_PPE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_NPE0_RX10_N

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUT

OUTOUTOUTOUT

OUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUT

ININ

ININININININININININININININININININININININININININININININ

ININ

ININ

IN

ININ

ININ

ININ

ININ

OUTOUT

OUTOUT

OUTOUTOUTOUT

OUTOUT

OUTOUT

IN

OUTIN

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Int PU

Int PUInt PU

Int PU

Int PU

84 mA (A01)

Int PUInt PU

Int PU

Int PU (S5)

IF PE1 INTERFACE IS NOT USED, GROUND DVDD1_PEX AND AVDD1_PEX

IF PE0 INTERFACE IS NOT USED, GROUND DVDD0_PEX AND AVDD0_PEX

OMIT

BGA (5 OF 11)MCP79-TOPO-B

U1400

Y12

AC12 AD12 V12 W12

AA12 AB12 M12 P12 R12 N12 T12 U12

M13 N13 P13

T17 W19 U17 V19 W16 W17 W18 U16 T19 U19

T16

E11

E7 F7

L8 L9

L6 L7

N10 N11

P9 N9

N6 N7

N4 N5

C7 D7

F6 E6

F5 E5

E3 E4

D3 C3

H5 G5

J6 J7

J4 J5

L10 L11

D4 C5

J1 H1

J3 J2

K3 K2

L3 L4

M3 M4

M1 M2

B4 C4

A3 A4

B2 B3

D1 C1

E1 D2

F2 E2

F4 F3

H4 G3

H2 H3

F11 G11

J9 K9

G9 H9

E9 F9

G7 H7

C8 D8

A8 B8

B7 A7

C6 B6

J10 J11

F13 G13

H13 J13

K14 L14

M14 N14

F17

D5 D9 E8 C10 M15 B10 L16 L18 M16 M18 M17 M19

PLACEMENT_NOTE=Place within 12.7mm of U1400

1%

R1710

1 2

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

PCIE_EXCARD_PRSNT_LEXCARD_CLKREQ_LFW_CLKREQ_LPCIE_MINI_PRSNT_L

TP_PE4_CLKREQ_LTP_PE4_PRSNT_L

TP_MCP_GPIO_17

PCIE_WAKE_L

PCIE_MINI_D2R_PPCIE_MINI_D2R_NPCIE_FW_D2R_PPCIE_FW_D2R_N

=PP1V05_S0_MCP_PEX_DVDD1

PEG_CLKREQ_LEXTGPU_RESET_LPEG_PRSNT_L

TP_PCIE_PE4_R2D_CN

PCIE_FW_R2D_C_NPCIE_EXCARD_R2D_C_PTP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE4PPCIE_CLK100M_EXCARD_NPCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_NPEG_CLK100M_P

Trang 18

BI

OUT

ININININININ

OUT

OUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUTOUTOUTININ

OUTOUT

OUTOUTOUTOUTOUT

IN

INOUT

INININ

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI+V_PLL_HDMI+V_PLL_IFPAB+VDD_IFPB+VDD_IFPA

+V_TV_DAC+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GNDMII_COMP_VDD

LCD_PANEL_PWR/GPIO_58LCD_BKL_ON/GPIO_59LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_PHDMI_TXC_N/ML0_LANE3_NHDMI_TXD0_P/ML0_LANE2_PHDMI_TXD0_N/ML0_LANE2_NHDMI_TXD1_P/ML0_LANE1_PHDMI_TXD1_N/ML0_LANE1_NHDMI_TXD2_P/ML0_LANE0_PHDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_NXTALIN_TV

DDC_DATA2/GPIO_24DDC_CLK2/GPIO_23

RGB_DAC_RSETRGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_PDP_AUX_CH0_N

HPLUG_DET3

HDMI_RSETHDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0DDC_CLK0

RGB_DAC_REDRGB_DAC_GREENRGB_DAC_BLUERGB_DAC_HSYNCRGB_DAC_VSYNC

TV_DAC_REDTV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_PIFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_PIFPA_TXD1_N

IFPA_TXD3_PIFPA_TXD2_N

IFPB_TXC_PIFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_PIFPB_TXD4_N

IFPB_TXD6_PIFPB_TXD5_N

IFPB_TXD6_NIFPB_TXD7_PIFPB_TXD7_N

DDC_DATA3DDC_CLK3

IFPAB_RSETIFPAB_VPROBE

RGMII_RXD2RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36MII_COL/GPIO_20/MSMB_DATAMII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUETV_DAC_HSYNC/GPIO_44TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXENRGMII_TXC/MII_TXCLK

RGMII_TXD3RGMII_TXD2RGMII_TXD1RGMII_TXD0

+3.3V_DUAL_RMGT1+3.3V_DUAL_RMGT2

OUTOUTOUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTBIOUTBIOUTOUT

OUT

OUTOUTOUT

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Okay to float all TV_DAC signals

avoids a leakage issue since

GPIO 57-59 ( IF LCD PANEL IS USED):

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting IFP interface can

NOTE: 20K pull-down required on DP_HOTPLUG_DET

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used

TP_DP_IG_AUX_CHP/NTMDS_IG_HPDTMDS_IG_DDC_DATATMDS_IG_DDC_CLKTMDS_IG_TXD_P/N<2>

E16 B15

J31

E35 D35

F35 G35

G33 F33

H33 J33

J30

C31 F31

C35 B35

A32 B32

C32 D32

C33 D33

C34 B34

E32 G31

K31 L31

H29 J29

K29 L29

K30 L30

M30 N30

G39 E37 F40

B26

B27 C27 B22

J23

F23

E28

J24 K24

T23

U23 V23

M29 M28

J32 K32

T25

M27 M26

B40 A39 A40 B39

C39 B38

A41

J22

D21 C21 G23

A23 C22

C23 B23 E24 A24

D24 C26

B24 C24 C25 D25

C36 B36 D36 A36

E36 A35

C37

C38 D38

1/16W 5%

402

10K

R1850

1 2

47K

5%

1/16W 402 MF-LF

2

1/16W 402 MF-LF 5%

100KR1861

73

100K5%

MF-LF 402 1/16WR1860

ENET_TXD<3>

ENET_TXD<2>

ENET_CLK125M_RXCLK

NO_TEST=TRUENC_MCP_RGB_VSYNC

NC_MCP_RGB_BLUE NO_TEST=TRUENC_MCP_RGB_RED NO_TEST=TRUEENET_TXD<0>

=PP3V3_S5_MCP_GPIO

LPCPLUS_GPIODP_IG_CA_DET

MCP_CLK27M_XTALINMCP_CLK27M_XTALOUT

MCP_HDMI_TXD_P<1>

ENET_RXD<1>

LVDS_IG_PANEL_PWR

MCP_HDMI_TXC_PMCP_HDMI_TXC_NMCP_HDMI_TXD_P<0>

MCP_HDMI_TXD_N<1>

TP_DP_IG_AUX_CHNTP_DP_IG_AUX_CHPMCP_HDMI_TXD_N<2>

MCP_HDMI_TXD_P<2>

=PP3V3_ENET_MCP_RMGT

CRT_IG_B_COMP_PBCRT_IG_G_Y_YCRT_IG_R_C_PR

CRT_IG_VSYNC

LVDS_IG_A_CLK_PLVDS_IG_A_CLK_N

DP_HOTPLUG_DETMCP_HDMI_HPD

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDDPP3V3_S0_MCP_VPLL

=MCP_HDMI_DDC_DATA

LVDS_IG_B_DATA_N<0>

LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_CLKLVDS_IG_DDC_CLKLVDS_IG_B_DATA_N<3>

MCP_HDMI_TXD_N<0>

LVDS_IG_BKL_PWMLVDS_IG_BKL_ON

=PP1V05_ENET_MCP_RMGT

PP1V05_ENET_MCP_PLL_MAC

MCP_TV_DAC_VREFMCP_TV_DAC_RSET

TP_ENET_INTR_LMCP_MII_COLMCP_MII_RXER

ENET_TX_CTRLENET_CLK125M_TXCLKENET_TXD<1>

TP_ENET_PWRDWN_LENET_MDIOENET_MDC

MCP_DDC_DATA0MCP_DDC_CLK0

MCP_MII_COMP_GNDMCP_MII_COMP_VDD

NO_TEST=TRUE NC_MCP_RGB_DAC_RSET

NC_MCP_RGB_GREEN NO_TEST=TRUE

NO_TEST=TRUENC_MCP_RGB_HSYNC

Trang 19

OUTBIBIBIBI

PCI_AD5PCI_AD6

PCI_AD9PCI_AD8PCI_AD7

PCI_AD10PCI_AD11

PCI_AD14PCI_AD13PCI_AD12

PCI_AD15PCI_AD16PCI_AD17

PCI_AD20PCI_AD19PCI_AD18

PCI_AD21PCI_AD22

PCI_AD25PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66GND67

GND69GND68

GND70GND71GND72

GND74GND73

GND75GND76GND77

GND79GND78

GND80GND81

GND84GND83GND82

GND85GND86GND87

GND89GND88

GND90GND91GND92

GND94GND93

GND95GND96GND97

PCI_CLKIN

LPC_FRAME#

LPC_AD1LPC_AD0LPC_RESET0#

LPC_CLK0LPC_AD3LPC_AD2

GND99GND98

GND100

GND102GND101

GND104GND103

GND105GND106GND107

GND109GND108

GND110GND111GND112

GND115GND114GND113

GND116GND117

GND120GND119GND118

GND121GND122GND123

GND125GND124

GND126GND127GND128

GND130GND129

PCI_AD30PCI_AD27PCI_AD24

PCI_CLKRUN#/GPIO_42PCI_AD28

OUT

IN

INOUTOUT

OUT

BIBIBIBIBIBIBIBI

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

U1400

AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34

U24 U26 U39 U4 U8 V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22 Y24 Y25

Y26 Y27

AD3 AD2 AD1 AD5 AE9 AE1

AE2

AD4 AE12 AE5

AE6

AC3 AE10

AC9 AC10 AC11 AA1 AA5 Y5 W3 W6 W4 W7 AC4

V3 W8 V2 W9 U3 W11 U2 U5 U1 U6 AE11

T5 U7

AB3 AC6 AB2 AC7 AC8 AA2

AA3 AA6 AA11 W10

R6 R7 R8

R9

AD11

AA9 Y4

R3 U10 R4 U11 P3

P2 N3 N2 N1

AA10 Y1 AB9

T1

T2 V9 T3 U9 T4

R10 R11

AA7 Y2

PLACEMENT_NOTE=Place close to pin R8

R1910

1 2

402 5% 1/16W MF-LF8.2K

402 MF-LF 1/16W 5%

8.2K

5% 1/16W MF-LF 4028.2K

10K

R1961

1 2

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02

MCP PCI & LPC

051-8089

LPC_PWRDWN_LLPC_RESET_L

TP_PCI_TRDY_LTP_PCI_INTZ_L

TP_PCI_INTX_LTP_PCI_INTY_L

Trang 20

ININININ

GND153GND154GND152GND151GND150

GND148GND149GND147GND146GND145

GND143GND144GND142GND141GND140GND139GND136

GND133GND134GND132GND131USB_RBIAS_GND

USB11_NUSB11_PUSB10_NUSB10_PUSB9_NUSB9_P

USB7_N

USB8_NUSB8_PUSB7_PUSB6_NUSB6_PUSB5_N

USB4_NUSB4_P

USB5_P

USB2_NUSB2_P

USB0_N

USB1_NUSB1_PUSB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_NSATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_NSATA_B1_RX_PSATA_B1_TX_NSATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_PSATA_B0_TX_P

SATA_A1_RX_NSATA_A1_RX_PSATA_A1_TX_NSATA_A0_TX_P

GND138GND137GND135

USB3_PUSB3_N

USB_OC0#/GPIO_25USB_OC1#/GPIO_26USB_OC2#/GPIO_27/MGPIOUSB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_NSATA_A0_TX_N

SATA_C1_TX_NSATA_C1_TX_P

SATA_C0_RX_PSATA_C0_RX_NSATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1+DVDD0_SATA2+DVDD0_SATA3+DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1+AVDD0_SATA2+AVDD0_SATA3+AVDD0_SATA4+AVDD0_SATA5+AVDD0_SATA6+AVDD0_SATA7+AVDD0_SATA8+AVDD0_SATA9

+AVDD1_SATA1+AVDD1_SATA2+AVDD1_SATA3+AVDD1_SATA4+DVDD1_SATA1

OUTOUT

ININ

OUTOUTININ

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

IRCameraExternal DAirPort (PCIe Mini-Card)External A

1/16W 402

R2010

1 2

1/16W 402 1%

MF-LF

R2053

1 2

8.2K

5%

1/16W 402

2

1/16W 5%

8.2K

402

R2051

1 2

OMIT

(8 OF 11) BGAMCP79-TOPO-B

U1400

AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24

AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13 AN14 AL14 AM13 AM14

AF19 AG16 AG17 AG19 AH17 AH19 AE16

L28

AJ5 AJ4

AJ6 AJ7

AJ9 AK9

AJ10 AJ11

AJ2 AJ1

AJ3 AK2

AL4 AK3

AL3 AM4

AM2 AM3 AM1 AN1

AN3 AN2

AP2 AP3

E12

AE3

D29 C29

G25 F25

L23 K23

D28 C28

B28 A28

G29 F29

L27 K27

J27 J26

G27 F27

E27 D27

L25 K25

J25 H25

L21 K21 J21 H21

02

SATA_ODD_D2R_P

TP_SATA_F_R2D_CPTP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_MCP_SATALED_LTP_SATA_F_D2RP

MCP_SATA_TERMP

MCP_USB_RBIAS_GND

USB_EXTD_P

USB_IR_PUSB_IR_N

USB_EXTA_PUSB_EXTA_N

SATA_ODD_R2D_C_P

SATA_HDD_D2R_PSATA_HDD_D2R_N

SATA_ODD_R2D_C_N

USB_EXTD_NSATA_HDD_R2D_C_P

USB_CAMERA_NUSB_CAMERA_P

USB_MINI_NUSB_MINI_P

TP_SATA_E_R2D_CPSATA_HDD_R2D_C_N

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

TP_USB_11N

TP_SATA_D_D2RPTP_SATA_D_D2RNTP_SATA_D_R2D_CNTP_SATA_D_R2D_CP

TP_SATA_C_D2RPTP_SATA_C_D2RNTP_SATA_C_R2D_CN

USB_EXCARD_NUSB_EXTB_P

USB_BT_PUSB_BT_N

USB_EXTB_N

USB_EXTC_P

TP_USB_10NTP_USB_10PUSB_EXTC_N

Trang 21

OUTOUT

BIBIOUTOUT

OUTOUTOUT

OUTOUT

OUT

OUTOUT

ININ

OUT

OUT

OUT

OUTIN

OUT

ININOUT

INININ

INOUT

THERM_DIODE_NTHERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMPHDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15MCP_VID1/GPIO_14MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62FANRPM1/GPIO_63FANCTL0/GPIO_61FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TESTTEST_MODE_ENBUF_SIO_CLKCPUVDD_EN

SMB_DATA0SMB_CLK0SPKRHDA_SYNC

XTALIN_RTCXTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALINJTAG_TCKJTAG_TMS

CPU_VLD

JTAG_TDIJTAG_TDO

RTC_RST*

PS_PWRGDPWRGD_SB

SPI_CS0/GPIO_10SPI_CLK/GPIO_11SPI_DI/GPIO_8SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1+V_DUAL_HDA2

OUTIN

IN

IN

OUTOUTIN

IN

ININ

ININ

INOUTOUT

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

37 mA (A01)

17 mA

PCI

not use LPC for BootROM override

LPC_FRAME# high for SPI1 ROM override

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

24 MHz

0 1

1 0

SPI_CLK SPI_DO

0

1 1

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM bydefault, LPC+ debug card pulls

1 1 0 0

0 1 0

1

Int PU

Int PU

Int PDInt PD

20 mA

Int PU (S5)Int PU

Int PU (S5)

7 mA (A01)

HDA Output Caps

For EMI Reduction on HDA interface

1K

1%

R2190

1 2

R2170

1 2

22

402 1/16W 5%

MF-LF

R2171

1 2

1/16W 5%

402 MF-LF

8.2K

1/16W 5%

R2160

1 2

R2180

1 2 1/16W

BOOT_MODE_USER

MF-LF 402

10K

5%

R2181

1 2

MF-LF

49.9

R2110

1 2

MF-LF 402 5%

10PF

50V

C2173

1 2

L26 L24

E15

K17 L17 A15

L13

M25 M24

L20 M20 M21

J16 K16

AE18 AE17

L22

E20 C16

D20

D16 C20

C19

J17 G17 H17

M23

L19 G21 K19 F21

D13 C14 C15 B14 C13

B18

K22

C11 B11

A16

A19 B16

R2147

1 2

100K

MF-LF 402 5%

R2146

1 2

MF-LF 5%

10K

R2141

1 2

10K

402 1/16W 5%

R2140

1 2

MF-LF 402 1/16W 5%

22K

R2157

1

2 402

1/16W 5%

22K

R2156

1

2 402

1/16W 5%

22K

R2155

1 2

402 5%

2

10K

402 1/16W 5%

MCP_CPUVDD_ENSMBUS_MCP_1_DATA

SPI_CLK_RHDA_BIT_CLK_R

MCP_CLK25M_XTALINJTAG_MCP_TCK

SM_INTRUDER_L

PM_DPRSLPVR

SMC_ADAPTER_EN

TP_MCP_KBDRSTIN_LTP_SB_A20GATE

SMC_WAKE_SCI_L

TP_MCP_LID_LPM_BATLOW_L

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

PM_CLK32K_SUSCLK_RSPI_MOSI_RSPI_MISO

PM_SLP_S4_L

HDA_SDOUT_R

=PP3V3R1V5_S0_MCP_HDA

MCP_TEST_MODE_ENMCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

HDA_BIT_CLK_R

JTAG_MCP_TRST_L

=PP3V3_S3_FETRTC_CLK32K_XTALOUT

PM_RSMRST_L

JTAG_MCP_TDI

JTAG_MCP_TMSJTAG_MCP_TDOMCP_CPU_VLDMCP_PS_PWRGDRTC_RST_L

AP_PWR_EN

MEM_EVENT_L

AP_PWR_ENSMBUS_MCP_1_CLKSMBUS_MCP_0_DATASMBUS_MCP_0_CLKMCP_SPKRMCP_VID<2>

MCP_VID<1>

MCP_VID<0>

MCP_THMDIODE_NMCP_THMDIODE_PPM_SLP_S3_L

MCP_GPIO_4AUD_I2C_INT_L

SMC_IG_THROTTLE_L

ARB_DETECTMCP_GPIO_4

Trang 22

GND161

GND165GND166GND164GND163GND162

GND167GND168

GND171GND170GND169

GND172GND173

GND176GND175GND174

GND177GND178

GND181GND180GND179

GND182GND183GND184

GND187GND186GND185

GND188GND189

GND192GND191GND190

GND193GND194

GND197GND196GND195

GND198

GND202GND201GND200GND199

GND203

GND206GND207GND205GND204

GND208

GND212GND211GND210GND209

GND213GND214

GND217GND216GND215

GND218GND219

GND222GND221GND220

GND223GND224GND225

GND228GND227GND226

GND229GND230

GND233GND232GND231

GND234GND235

GND238GND237GND236

GND239GND240

GND243GND242GND241

GND244

GND248GND247GND246GND245

GND249

GND252GND251GND250 GND342

GND341

GND343GND340GND339GND338GND337GND336GND335GND334GND333

GND331GND332GND330GND329GND328

GND326GND327GND325GND324GND323

GND321GND322GND320GND319GND318

GND316GND317GND315GND314GND313GND311GND310

GND312

GND309GND308

GND305GND306GND307

GND304GND303GND301GND300

GND302

GND299GND298GND296GND295

GND297

GND294GND293GND292GND291GND290GND289GND288GND287

GND285GND286GND284GND283GND282

GND280GND281GND279GND278GND277

GND275GND276GND274GND273GND272GND270GND269

GND271

GND268GND267

GND264GND265GND266

GND263GND262

GND259GND260GND261

GND258GND257GND255GND254

GND256GND253

+VTT_CPUCLK+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17+VTT_CPU16+VTT_CPU15+VTT_CPU14+VTT_CPU13+VTT_CPU12+VTT_CPU11+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1+VDD_CORE2+VDD_CORE3+VDD_CORE4+VDD_CORE5+VDD_CORE6

+VDD_CORE13+VDD_CORE14+VDD_CORE15+VDD_CORE16+VDD_CORE17+VDD_CORE18+VDD_CORE19

+VDD_CORE21+VDD_CORE22+VDD_CORE23+VDD_CORE24+VDD_CORE25+VDD_CORE26+VDD_CORE27+VDD_CORE28+VDD_CORE29+VDD_CORE30

+VDD_CORE32+VDD_CORE33+VDD_CORE34+VDD_CORE35+VDD_CORE36+VDD_CORE37

+VDD_CORE39+VDD_CORE40+VDD_CORE41

+VDD_CORE47+VDD_CORE48+VDD_CORE49+VDD_CORE50+VDD_CORE51+VDD_CORE52+VDD_CORE53+VDD_CORE54

+VTT_CPU51+VTT_CPU50

+VTT_CPU47+VTT_CPU46+VTT_CPU45+VTT_CPU43+VTT_CPU42+VTT_CPU41+VTT_CPU40+VTT_CPU39+VTT_CPU38+VTT_CPU37+VTT_CPU36+VTT_CPU35+VTT_CPU34+VTT_CPU32+VTT_CPU31+VTT_CPU30+VTT_CPU29+VTT_CPU28+VTT_CPU26+VTT_CPU25+VTT_CPU24+VTT_CPU23+VTT_CPU22+VTT_CPU21+VTT_CPU20+VTT_CPU19+VTT_CPU18

+VTT_CPU9+VTT_CPU8+VTT_CPU7+VTT_CPU6+VTT_CPU5+VTT_CPU4+VTT_CPU3

+VDD_CORE38

+VTT_CPU33+VTT_CPU27

+VDD_CORE55+VDD_CORE56+VDD_CORE57+VDD_CORE58+VDD_CORE59+VDD_CORE60+VDD_CORE61+VDD_CORE62+VDD_CORE63+VDD_CORE64+VDD_CORE65+VDD_CORE66+VDD_CORE67+VDD_CORE68+VDD_CORE69+VDD_CORE70+VDD_CORE71+VDD_CORE72+VDD_CORE73+VDD_CORE74+VDD_CORE75+VDD_CORE76+VDD_CORE77+VDD_CORE78+VDD_CORE79+VDD_CORE80+VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1+3.3V_DUAL2+3.3V_DUAL3+3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3+3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3+VDD_AUXC2+VDD_CORE43

+VTT_CPU2

+VDD_CORE46+VDD_CORE45+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49+VTT_CPU48+VTT_CPU44

+3.3V_7+3.3V_6+3.3V_5+3.3V_4+3.3V_3+3.3V_2

+VDD_CORE20

+VDD_CORE12+VDD_CORE11+VDD_CORE10+VDD_CORE9+VDD_CORE8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

MCP79-TOPO-B(11 OF 11)

OMIT

U1400

AH26 AH33 AH34 AH37 AH38 AJ39 AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9 AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33 AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43 AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41

AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22

MCP79-TOPO-BBGA (10 OF 11)

OMIT

U1400

AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9

G18 H19 J20 K20 G26 H27 J28 K28

A20

T21 U21 V21

AA25

AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17 AC23

AC24 AC25 AC26 AC27 AC28 AD21 AD23 W27 V25 AA18 U25

AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19 AH12

AF2 AF21 AF23 AF25 AF3 AF4 AF7 AH23 AF9 AA20 AG10

AG11 AG12 AG21 AG23 AG25 AG3 AG4 AA21 AG6 AG7 AG5

AG8 AG9 AH1 AH10 AH11 W26 AH2 AA23 W28 AH25 Y21

AH21 AH3 AH4 AH5 AH6 AH7 AH9 AA24 W21 W23 Y23

W25 AF12

AA16

R32

P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 AC32

B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 E40

F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 J36

K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 N32

P32 Y32 AA32

T32 U32 V32 W32

Trang 23

APPLE INC. SCALE

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I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Trang 24

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Apple: 1x 2.2uF 0402 (2.2 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)MCP FSB (VTT) Power

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)Apple: 2x 2.2uF 0402 (4.4 uF)

562 mA (A01)

MCP79 Ethernet VRef

402 20%

4.7UF4V

2

X5R 4V4.7UF20%

2

402 4V 20%

2

6.3V 20%

402-LF CERM2.2UF

C2555

1 2

20%

X5R 4V4.7UF

2

402-1 X5R 10%

1UF10V

C2507

1 2 402-1 X5R 10%

1UF10V

C2506

1 2 402-1 X5R 10%

1UF10V

C2505

1 2 402-1 X5R 10%

1UF10V

C2504

1 2

20%

CERM 10V0.1UF

402

C2511

1 2 20%

CERM 10V0.1UF

402

C2510

1 20.1UF20%

CERM 402

C2509

1 2 402 20%

CERM 10V0.1UF

C2508

1 2

20%

CERM 10V0.1UF

402

C2513

1 2 20%

CERM 10V0.1UF

402

C2512

1 2

CERM 402-LF 20%

2.2UF6.3V

C2536

1 22.2UF20%

6.3V 402-LF CERM

C2535

1 2 20%

6.3V2.2UFCERM 402-LF

C2534

1 2 20%

2.2UF6.3V 402-LF

C2533

1 2 CERM 20%

2.2UF6.3V 402-LF

C2532

1 2 CERM2.2UF20%

402-LF

C2531

1 2 CERM 20%

2.2UF6.3V 402-LF

C2530

1 2

402-1 10V1UF10%

X5R

C2517

1 2 402-1 X5R 10%

1UF10V

C2516

1 2 20%

4V4.7UF

402

402-LF 20%

2.2UF6.3V

C2572

1 2 CERM 402-LF 20%

2.2UF6.3V

C2571

1 2 20%

4.7UF4V 402

402-LF 20%

2.2UF6.3V

C2570

1

402-LF 20%

2.2UF6.3V

C2574

1 2 CERM 402-LF 20%

6.3V2.2UF

C2573

1 2

6.3V2.2UF20%

402-LF CERM

C2576

1 2 CERM 402-LF 20%

2.2UF6.3V

C2575

1 2

CERM 402-LF 20%

6.3V2.2UF

C2553

1 2 CERM 402-LF 20%

2.2UF6.3V

C2552

1 2 402-LF 20%

6.3V2.2UF

CERM

C2551

1 2 CERM 402-LF 20%

2.2UF6.3V

C2550

1 2

10V 402 20%

0.1UFCERM

C2549

1 2 CERM 20%

0.1UF

402

C2548

1 2 CERM 20%

0.1UF

402 10V

C2547

1 2 CERM 20%

0.1UF

402 10V

C2546

1 2 20%

0.1UF

402 10V CERM

C2545

1 2 CERM 20%

0.1UF10V 402

C2544

1 2 CERM 20%

0.1UF

402 10V

C2543

1 2 CERM 20%

4020.1UF10V

C2542

1 2 20%

0.1UF

402 10V CERM

C2541

1 2 402 4V4.7UF20%

2

CERM 402-LF 20%

2.2UF6.3V

C2562

1 2

6.3V2.2UF20%

402-LF CERM

C2564

1 2

402 4V 20%

X5R4.7UF

2

20%

4V4.7UF

C2526

1 20.1uF20%

402 CERM 10V

C2525

1 2

CERM 402-LF 20%

2.2UF6.3V

C2560

1 2

20%

0.1UF

402 CERM

C2589

1 2

20%

402 CERM 10V0.1UF

C2590

1 2

402 4V4.7UF20%

1.47K

2

10V 402 CERM

0.1UF

C2591

1 2

1/16W1.47K1%

MF-LF 402

2

18

0.1uF20%

402 CERM 10V

C2521

1 20.1uF

10V 402 20%

C2519

1 2

402 10V0.1UFCERM 20%

C2581

1 2

10V 4020.1UFCERM

C2583

1 2

402 10V0.1UF

CERM 20%

C2585

1 2

402 10V0.1UFCERM 20%

C2587

1 2

0.1UF20%

CERM 10V 402

C2596

1 2

20%

402 CERM 10V0.1uF

C2529

1 2 X5R 4V4.7uF

402 20%

2

4.7UF

X5R 20%

4V

2

25 051-8089SYNC_MASTER=K36B_MLB

109 02

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3VPP3V3_S0_MCP_PLL_USB

VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MMPP1V05_S0_MCP_PLL_PEX

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MMPP1V05_S0_MCP_PLL_NV

PP1V05_ENET_MCP_PLL_MACMIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

VOLTAGE=1.05VPP1V05_S0_MCP_PEX_AVDDMIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_SATA_AVDDMIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

Trang 25

A0 VCC

SDA

WP GND

INBI

SCLSDAWPVCC

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

WF: Checklist says 0-ohm resistor placeholder for ferrite bead

Apple: 1x 2.2uF 0402 (2.2 uF)

HDCP ROM

SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

402-LF CERM 20%

6.3V2.2UF

C2651

1 2 6.3V 402-LF 20%

2.2UF

C2650

1 2

1/16W

R2630

1

2 402

NO STUFF

20%

CERM 10V

0.1UF

2

X5R 4V4.7UF20%

2

4.7UFCERM 603 20%

C2641

1 2

10V0.1UF

402 20%

CERM

C2616

1 2

6 5 8 7

0.1UF

CERM 20%

402

2

402 1/16W 5%

MF-LF10K

MF-LF

1K

1%

1/16W 402

R2620

1 2

6.3V2.2UF20%

402-LF CERM

C2610

1 2

26 051-8089

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

MCP Graphics Support

02 109HDCPROM_WP

=PP3V3R1V8_S0_MCP_IFP_VDD

MCP_IFPAB_VPROBEMCP_IFPAB_RSET

=PP3V3_S0_MCP_DAC_UF PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM

=PP3V3_S0_MCP_VPLL_UF

MIN_NECK_WIDTH=0.2 MMPP3V3_S0_MCP_VPLL

Trang 26

IN OUT

OUT

OUTIN

NCNC

OUT

OUTIN

ININ

OUT

OUTOUT

OUTIN

IN

OUT

Y B A

OUT

VIN

GND

VOUTEN

NC

IN

OUT

NCNC

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

10K pull-up to 3.3V S0 inside MCP

MCP S0 PWRGD Reset Button

SYNC FROM T18

ALIAS MEM_VTT_EN TO =DDRVTT_EN

CHANGE Y2810 AND U2850 TO SMALLER PARTS

REMOVE R2824 AND NET PCI_CLK33M_SLOT_A

REMOVE UNUSED PCIE RESET SIGNALS

LPC Reset (Unbuffered)

CHANGE RESET BUTTOM TO RESET PADS

CHANGE RTC POWER SOURCE FROM COIN CELL TO SUPER CAPS

Platform Reset Connections

PCIE Reset (Unbuffered)

12pF

C2810

1 2

402 5%

12pF

50V CERM

C2811

1 2

05%

1/16W 402 MF-LF

R2810

1/16W 402 5%

MF-LF33

PLACEMENT_NOTE=Place close to U1400

R2883

402 MF-LF 5%

33PLACEMENT_NOTE=Place close to U1400

R2881

0

MF-LF 5%

1/16W 402

R2825

5%

402 MF-LF

PLACEMENT_NOTE=Place close to U1400 22

72 19

50V 5%

12pF

402 CERM

C2815

1 2

5%

50V CERM 402

MF-LF 5%

402 1/16W0

R2853

10V 402 20%

CERM0.1UF

C2850

1 2

33

1/16W 402

R2899

1 2

402 5%

1/16W0SILK_PART=SYS RST

NO STUFF

2

1/16W 402

XDP

05%

0.08F

XHHG

C2800

12

27

5%

0

1/16W 402

TC7SZ08AFEAPESOT665

U2850

213

54

MF-LF 402 1/16W 5%

0

R2872

CERM402

1UF

6.3V10%

C2801

12

100

MF-LF1%

4021/16W

R2801

1

2

402 CERM 50V 5%

10PF

NO STUFF

C2826

12

18

50V 5%

402 CERM

12pF

C2820

1 2

MF-LF 402 5%

0

R2820

SM-227MHZ

MF-LF10M

402

2

402 CERM 5%

50V12pF

C2821

1 2

18

28 051-8089

SB Misc

02 109SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

LPC_CLK33M_SMC_R

PM_CLK32K_SUSCLK

MEM_VTT_EN_RMCP_CLK27M_XTALIN

MCP_CLK27M_XTALOUT

FW_RESET_L

MAKE_BASE=TRUEMEM_VTT_EN

PP3V3_G3_RTCMIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

XDP_DBRESET_L

BKLT_PLT_RST_L

SMC_LRESET_LDEBUG_RESET_L

Trang 27

V+

V+

V+

V-RESET*

A0A1A2

SCLSDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPAD

NCNCNC

IN

INBI

VDD

VOUTDVOUTCVOUTBVOUTASCL

SDAA0A1

GND

INBI

NC

NC

OUT

NCNC

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TABLE_5_ITEM TABLE_5_ITEM

Place close to U1000.AD26

BOM OPTION TO SELECT VREF SOURCE

10mA max load

Place close to J3200.1

MAX4253UCSP

B4

MAX4253

VREFMRGN

UCSPU2902

C3

C2

C1C4B1

B4

MAX4253UCSP

B4

MAX4253

VREFMRGN

UCSPU2904

A3

A2

A1A4B1

100K

MF-LFVREFMRGN5%

4021/16W

345

679101112131415

12

3

67

81245

44

44

0.1UF VREFMRGN

40220%

CERM

C2901

12

2.2UF VREFMRGN

6.3V20%

402-LF

C2900

12

VREFMRGN

402CERM10V

0.1UF C2905

12

100K

1/16WVREFMRGN

R2913

VREFMRGN 0.1UF

40220%

CERM10V

C2903

12

69

10

29 051-8089

FSB/DDR2 VREF MARGINING

SYNC_MASTER=K36B_MLB

109 02

=PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.25 mmMEM_VREF_A

CPU_GTLREF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CPUFSB_ENVREFMRGN_CPUFSB_BUF

Trang 28

VSS2DQ5

SA1SA0VSS58DQ63DQ62VSS56DQS7DQS7*

VSS54DQ60VSS52DQ54VSS50VSS48CK1*

CK1VSS46DQ53DQ52VSS44VSS42DQS5DQS5*

VSS39DQ45DQ44VSS37DQ39DQ38VSS35DM4VSS34DQ37DQ36VSS32NC3VDD11NC/A13ODT0VDD9S0*

RAS*

BA1VDD7A0A2A4VDD5A6A7A11VDD3NC/A14NC/A15VDD1NC/CKE1VSS30DQ31DQ30VSS28DQS3DQS3*

VSS26DQ29DQ28VSS24DQ23DQ22VSS22DM2NC0VSS19DQ21DQ20VSS17VSS15DQ15DQ14VSS13CK0*

CK0VSS11DQ13VSS7DQ7VSS5DM0

DQ4VSS0

DM1DQ12DQ6

DQ47DQ46

DQ61DQ55DM6

VDDSPDSCLSDAVSS57DQ59DQ58VSS55DM7VSS53DQ56VSS51DQ50VSS49DQS6*

VSS47NC_TESTVSS45DQ49DQ48VSS43VSS41DM5VSS40DQ41VSS38DQ35VSS36DQS4DQS4*

VSS33DQ33DQ32VSS31NC/ODT1VDD10NC/S1*

CAS*

VDD8WE*

BA0A10/APVDD6A1A3A5VDD4A8A9A12VDD2BA2NC2VDD0CKE0VSS29DQ27DQ26VSS27NC1DM3VSS25DQ25DQ24VSS23DQ19DQ18VSS21DQS2DQS2*

VSS18DQ17DQ16VSS16VSS14DQ11DQ10VSS12DQS1DQS1*

DQ9DQ8VSS8DQ3DQ2VSS6DQS0DQS0*

VSS4

VSS1VREFDQ0DQ1

DQ34

DQ40

DQ42DQ43

DQS6

DQ51

DQ57

KEYVSS9

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DDR2 Bypass Caps

(NONE)

(For return current)

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V8_S3_MEM

NC

NCNCNC

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps, when they get cheaper.

C3121

12

10V

0.1UF

CERM20%

402

C3110

12

0.1UF

20%

402CERM

J3100

102101

105

9089

10099

9897

949293

91

107

10685

113

3032

164166

3537

2022

3638

4345

5557

17

4446

5658

6163

7375

626419

7476

123125

135137

124126

1341364

141143

151153

140142

152154

157159

6

173175

158160

174176

179181

189191

14

180182

192194

16

2325

1311

3129

5149

7068

131129

148146

169167

188186201

202

116

868480

119115

198200197

138139

1449

10V

CERM

C3111

12

0.1UF

10V

20%

402CERM

C3112

12

40220%

20%

CERM402

10V

0.1UF

C3115

12

2.2UF

20%

6.3V

CERM402-LF

C3116

12

2.2UF

20%

6.3V

CERM402-LF

C3117

12

10K

5%

1/16W402

R3141

1 2

10K

1/16W402MF-LF5%

R3140

1 2

31 051-8089

Trang 29

VSS2DQ5

SA1SA0VSS58DQ63DQ62VSS56DQS7DQS7*

VSS54DQ60VSS52DQ54VSS50VSS48CK1*

CK1VSS46DQ53DQ52VSS44VSS42DQS5DQS5*

VSS39DQ45DQ44VSS37DQ39DQ38VSS35DM4VSS34DQ37DQ36VSS32NC3VDD11NC/A13ODT0VDD9S0*

RAS*

BA1VDD7A0A2A4VDD5A6A7A11VDD3NC/A14NC/A15VDD1NC/CKE1VSS30DQ31DQ30VSS28DQS3DQS3*

VSS26DQ29DQ28VSS24DQ23DQ22VSS22DM2NC0VSS19DQ21DQ20VSS17VSS15DQ15DQ14VSS13CK0*

CK0VSS11DQ13VSS7DQ7VSS5DM0

DQ4VSS0

DM1DQ12DQ6

DQ47DQ46

DQ61DQ55DM6

VDDSPDSCLSDAVSS57DQ59DQ58VSS55DM7VSS53DQ56VSS51DQ50VSS49DQS6*

VSS47NC_TESTVSS45DQ49DQ48VSS43VSS41DM5VSS40DQ41VSS38DQ35VSS36DQS4DQS4*

VSS33DQ33DQ32VSS31NC/ODT1VDD10NC/S1*

CAS*

VDD8WE*

BA0A10/APVDD6A1A3A5VDD4A8A9A12VDD2BA2NC2VDD0CKE0VSS29DQ27DQ26VSS27NC1DM3VSS25DQ25DQ24VSS23DQ19DQ18VSS21DQS2DQS2*

VSS18DQ17DQ16VSS16VSS14DQ11DQ10VSS12DQS1DQS1*

DQ9DQ8VSS8DQ3DQ2VSS6DQS0DQS0*

VSS4

VSS1VREFDQ0DQ1

DQ34

DQ40

DQ42DQ43

DQS6

DQ51

DQ57

KEYVSS9

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

- =PPSPD_S0_MEM (2.5V - 3.3V)

- =PP1V8_S3_MEMPower aliases required by this page:

C3221

12

0.1UF

10VCERM20%

4VX5R

J3200

102101

105

9089

10099

9897

949293

91

107

10685

113

3032

164166

3537

2022

3638

4345

5557

17

4446

5658

6163

7375

626419

7476

123125

135137

124126

1341364

141143

151153

140142

152154

157159

6

173175

158160

174176

179181

189191

14

180182

192194

16

2325

1311

3129

5149

7068

131129

148146

169167

188186201

202

116

868480

119115

198200197

138139

1449

0.1UF

C3212

12

1/16W402MF-LF5%

10K R3241

1

2

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

02 109

DDR2 SO-DIMM Connector B

051-8089 32

Trang 30

IN

ININININININININININININININ

ININ

IN

INININ

ININININ

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

One cap for each side of every RPAK, one cap for every two discrete resistors BOMOPTION shown at the top of each group applies to every part below it

47

1/16WMF-LF4025%

47

MF-LF4021/16W5%

5%

47

4021/16WMF-LF

021

47

1/16W5% SM-LFRP3300 4 5

47

SM-LF1/16W5%

RP3300 1 8

47

1/16W5% SM-LFRP3300 2 7

47

SM-LF1/16W5%

RP3301 2 7

47

1/16WSM-LF5%

RP3301 1 8

47

1/16W5% SM-LFRP3301 4 5

47

1/16WSM-LF5%

RP3301 3 6

1/16W5% SM-LF

47

RP3302 4 5

47

1/16WSM-LF5%

RP3302 1 8

47

5%1/16WSM-LFRP3302 3 6

47

1/16WSM-LF5%

RP3302 2 7

SM-LF5%

47

1/16WRP3303 1 8

47

1/16W5% SM-LFRP3303 2 7

47

SM-LF1/16W5%

RP3303 3 6

47

SM-LF5% 1/16WRP3303 4 5

47

SM-LF1/16W5%

RP3304 1 8

47

SM-LF1/16W5%

RP3304 3 6

47

5%1/16WSM-LFRP3304 4 5

1/16WSM-LF5%

47

RP3305 1 8

47

5%1/16WSM-LFRP3305 2 7

47

1/16W5% SM-LFRP3305 3 6

47

SM-LF1/16W5%

RP3305 4 5

47

1/16W5% SM-LFRP3306 2 7

47

SM-LF1/16W5%

RP3306 3 6

47

SM-LF5% 1/16WRP3307 4 5

47

SM-LF5% 1/16WRP3307 3 6

47

SM-LF1/16W5%

RP3307 2 7

47

1/16WSM-LF5%

RP3307 1 8

47

1/16W5% SM-LFRP3308 4 5

47

SM-LF5% 1/16WRP3308 3 6

47

SM-LF5% 1/16WRP3308 2 7

47

SM-LF1/16W5%

RP3308 1 8

47

SM-LF1/16W5%

RP3309 1 8

47

SM-LF1/16W5%

RP3309 2 7

47

SM-LF1/16W5%

RP3309 3 6

47

SM-LF1/16W5%

RP3309 4 5

47

SM-LF1/16W5%

RP3310 3 6

47

SM-LF1/16W5%

RP3310 2 7

47

SM-LF1/16W5%

RP3310 1 8

47

5%1/16WSM-LFRP3310 4 5

47

SM-LF1/16W5%

RP3311 1 8

47

SM-LF1/16W5%

RP3311 2 7

47

1/16W5% SM-LFRP3311 4 5

47

SM-LF1/16W5%

RP3306 4 5

47

1/16W5% SM-LFRP3311 3 6

0.1UF

C3300

1 2

0.1UF

20%

402 10V CERM

C3301

1 2

0.1UF

CERM 10V 402

C3302

1 2

402 10V CERM 20%

0.1UF

C3303

1 2

0.1UF

CERM 10V 402

C3304

1 2

0.1UF

402 20%

CERM

C3305

1 2

0.1UF

CERM 10V 402

C3306

1 2

402 20%

0.1UF

CERM 10V

C3308

1 2

402 20%

CERM

0.1UF

C3309

1 2

0.1UF

20%

CERM 10V 402

C3310

1 2

20%

402 10V CERM

0.1UF

C3311

1 2

20%

402 CERM 10V

C3313

1 2

10V CERM 20%

402

0.1UF

C3314

1 2

402 20%

CERM

0.1UF

C3315

1 2

0.1UF

402 CERM 10V

C3317

1 2

0.1UF

CERM 10V 402

C3318

1 2

402 20%

CERM

0.1UF

C3319

1 2

0.1UF

CERM 10V 402

C3320

1 2

402 20%

CERM

0.1UF

C3321

1 2

0.1UF

CERM 10V 402

C3322

1 2

402 20%

CERM

0.1UF

C3323

1 2

0.1UF

CERM 10V 402

C3324

1 2

0.1UF

CERM 10V 402

C3325

1 2

RP3304 2 7

SM-LF5% 1/16W

47

RP3306 1 8

1/16W 4025% MF-LF

0 1 2 3 4 5 6 7

10 11 9 8

13 12

Memory Active Termination

051-8089 33

MEM_A_BA<2 0>

MEM_A_A<14 0>

MEM_B_BA<2 0>

MEM_A_WE_LMEM_A_CAS_LMEM_A_RAS_L

Trang 31

Y B A

OUTOUTINOUT

INOUT

BIIN

D

SG

D

SG

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

CERM40210V

0.1uF

C34521 2

TC7SZ08AFEAPESOT665

U3401

213

54

MF-LF 5%

1/16W 5%

MF-LF 402

6.3V

2

F-ST-SMCRITICAL

17 7

20%

CERM 10V 4020.1uF

2603 6.3V 20%

10uF

C3420

12

10%

X5R0.1UF

402 16V

MF-LF

R3450

0.033UF10%

X5R

2

10K5%

1/16W 402 MF-LF

C3406

12

SSM6N15FEAPE

SOT563

2 1

SOT563

SSM6N15FEAPE

5 4

34 051-8089

Right Clutch Connector

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

02 109

PCIE_MINI_D2R_PPCIE_MINI_D2R_N

=PP1V5_S0_AIRPORT

PCIE_MINI_PRSNT_L

PP3V3_WLAN_FMIN_LINK_WIDTH=1 MMVOLTAGE=3.3 VMIN_NECK_WIDTH=0.5 MM

=USB_MINI_N

=USB_MINI_PMINI_CLKREQ_CONN_L

Trang 32

LED1/PHYAD1LED2/RXDLYLED0/PHYAD0

CLOCKRESET

LED

ININININ

IN

INBI

IN

IN

BI

BIBI

BIBIBIBIBI

OUT

OUTOUTOUTOUT

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

AN[1:0] = 11 (Full auto-negotiation)

RXDLY = 0 (RXCLK transitions with data)

PLACE R3796 CLOSE TO U1400, PIN D24

WF: Marvell numbers, update for Realtek

(19mA typ - Energy Detect)(43mA typ - 1000base-T)

Alias to GND for external 1.05V supply

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher

If internal switcher is used, must place inductor within 5mm

If internal switcher is not used, VDDREG and REGOUT can float

1x 0.1uF caps within 5mm of U3700 pins 44 & 45

If internal switcher is used, must place 1x 22uF &

WF: Marvell numbers, update for Realtek(221mA typ - 1000base-T)

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor

Reserved for EMIper RealTek request

PHY_AD0/LED0

RXDLY/LED2

If false, ENET_RESET_L should be removed

WF: Verify that ENET_RESET_L does not assert when WOL is active

If true, RC and 0-ohm resistor should be removed

Alias to =PP3V3_ENET_PHY for internal switcher

( 7mA typ - Energy Detect)

NO STUFF

10V CERM 402 20%

0.1UF

C3727

1 2

1/16W 402 1%

MF-LF

NO STUFF

R3799

1 2

5%

1/16W10K

10%

402 16V0.1UF

C3705

1 2

CRITICAL

RTL8211CLGRTQFP

30

2 1

5 4

9 8

12 11

27

23 24 25 26

44 45

10%

X5R0.1UF

402

C3706

1 2

10%

4020.1UF

X5R

C3700

1 2

0.1UF10%

402 16V

C3701

1 2

0.1UF10%

X5R

C3702

1 2

1/16W 5% MF-LF

5% 1/16W MF-LF22

MF-LF4.7K

402

2

1/16W 5%

MF-LF4.7K

MF-LF 402

2

1/16W 5%

MF-LF4.7K

402

R3757

1 2

402 MF-LF4.7K5%

2 402

1/16W 5%

MF-LF4.7K

R3751

1 2

10%

402 16V0.1UF

2 10%

4020.1UF16V

X5R0.1UF

2 10%

402 16V0.1UF

2

16V0.1UFX5R 10%

R3731

1

2

37 051-8089

Ethernet PHY (RTL8211CL)

02

SYNC_DATE=03/20/2008SYNC_MASTER=SUMA

109

RTL8211_RSET

RTL8211_CLK125

RTL8211_CLK25M_CKXTAL1TP_RTL8211_CKXTAL2RTL8211_PHYRST_L

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MIN_LINE_WIDTH=0.6 MMPP3V3_ENET_PHYAVDD

MIN_NECK_WIDTH=0.2 MMPP1V05_ENET_PHYAVDD

Trang 33

DS

OUT

D

SG

D

SG

D

SG

D

SG

IN

D

SG

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal

Pull-up is with power FET

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

I(max) = 1.7A (85C)Rds(on) = 90mOhm max

Recommend aliasing PM_SLP_RMGT_L and

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered

10%

402

0.01UF

16V CERM

C3810

1 2

0.033UF10%

402 16V

C3811

1 2

MF-LF 402

MF-LF 5%

1/16W PLACEMENT_NOTE=Place close to U1400

R3840

1 2

10%

402 CERM

0.01UF

16V

C3841

1 2

0.1UF

20%

CERM 10V 402

SOT563

SSM6N15FEAPE

2 1

69.8K

1/16W 1%

402 MF-LF

10K

5%

402 MF-LF

9

10K

402 1/16W 1%

MF-LF

R3841

1 2

38 051-8089

Ethernet & AirPort Support

02SYNC_MASTER=SUMA SYNC_DATE=04/04/2008

Trang 34

BIBI

BIBI

BIBI

ENET_MDI_TRAN_N_3 ENET_MDI_TRAN_P_3 ENET_MDI_TRAN_N_2 ENET_MDI_TRAN_P_2 ENET_MDI_TRAN_N_1 ENET_MDI_TRAN_P_1 ENET_MDI_TRAN_N_0 ENET_MDI_TRAN_P_0

SYM_VER-1

RXTXRXTX

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

- COPY THIS PAGE FROM K36 CSA.39

1357

0.1UF

16V 402 10%

C3900

1 2

75

MF-LF1/16W

R3900

1 21/16W MF-LF

02SYNC_MASTER=SUMA SYNC_DATE=04/04/2008

109

ETHERNET CONNECTOR

051-8089 39

Trang 35

ATBUSHATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMSTCKREFCLKNPCIE_TXD0P

AVREGCE

CLKREQN

FW_RESET*

FW620*

JASI_ENMODE_ANAND_TREE

OCR_CTL_V12

PCIE_RXD0NPCIE_RXD0PPCIE_TXD0N

SCLSDASE

SM

TDOTPA1N

TPA2NTPA2PTPB0NTPB0PTPB1NTPB1PTPB2NTPB2PTPBIAS0TPBIAS1TPBIAS2

DS0

TPA1P

VDD33VDD10

VREG_VSSVSS

CHIP RESETSCIF

1394 PHY

NCNCNC

NC

ININ

ININ

OUTOUT

OUT

OUT

INININBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

IN

NCNC

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-10 (IPD)

NT-12 (IPD)

(IPD) NT-21 (IPD) NT-20 (IPD) NT-19

110 mA Digital Core

114 mA FireWire PHY

NT-15 (IPD) NT-17 NT-14 (IPD) NT-16 (IPD) NT-13

NT-1 (IPU)

25 mA PCIe SerDes

NT-2 (IPU) (IPU)

0 mA VReg PWR

(OD)

NT-5 NT-OUT

(Reserved)

NT-9 (IPD)

(IPU) (IPD) (IPD) NT-18

NAND tree order.

NOTE: NT-xx notes show

135 mA

NT-6

1%

402MF-LF

FW643E U4100

B13A13A11

A10L13

L2

F12E12E13

D12

K13D1J2K1

J12J13

N8N7N5N6

N4B11

N9N10

D13

L8

G2G1H1F2

N12M11M13

N13

M4N2M1M3

B8A8B5A5B3A3B9A9B6A6B4A4B7C3A2

B10

N1

E1D2

H10 J4 J5 J9 J10 K4 K5 K7D9 K8 K9 L7 K6

D10 E4 E5 E9 F4 F6

C2

G13F13

CERM

22PF

5%

40250V

R4150

1 2

10K

MF-LF5%

1/16W402

1/16W402

1/16W402

R4166

1

2

X5RPLACEMENT_NOTE=Place C4171 close to U1400

402

1UF

CERM10%

24026.3V

C4101

1

2

CERM4026.3V

4026.3V

1UF C4102

1

2

10%

6.3V402

1UF C4103

210%

1UF

CERM4026.3V

C4110

1

2

402CERM10%

1UF C4105

210%

1UF

CERM4026.3V

2

0.1UF

10VCERM402

2

6.3V10%

1UF

402CERM

02 109 051-8089

41

PP3V3_FW_FWPHY_VP25

MIN_LINE_WIDTH=0.4 MMVOLTAGE=3.3VVOLTAGE=1.0V

PCIE_FW_R2D_C_N

PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P

PCIE_FW_R2D_C_P

TP_FW643_OCR10_CTL

FW_RESET_L

FW_P0_TPB_N FW_P1_TPB_N

FW_P2_TPA_N

FW_P0_TPB_P FW_P1_TPB_P

TP_FW643_VBUF FW643_PU_RST_L

TP_FW643_SM

TP_FW643_AVREG TP_FW643_JASI_EN TP_FW643_CE TP_FW643_SE

FW_P2_TPB_N FW_P2_TPB_P

FW_P1_TPBIAS

FW643_R0 FW643_TPCPS TP_FW643_NAND_TREE FW643_REXT

FW_CLK24P576M_XO_R FW_CLK24P576M_XI

FW_P2_TPBIAS FW_P0_TPBIAS

TP_FW643_MODE_A

MIN_LINE_WIDTH=0.4 MMVOLTAGE=3.3V

PP3V3_FW_FWPHY_VDDA

=PP3V3_FW_FWPHY

=PP1V0_FW_FWPHY

FW_CLKREQ_L TP_FW643_VAUX_ENABLE FW643_REGCTL

FW_PME_L

FW643_TRST_L TP_FW643_TMS

Trang 36

V-D

SG

ININ

D

SG

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

Signal aliases required by this page:

- =PPVP_FW_SUMNODE (power passthru summation node)

Late-VG Event Detection

FireWire Port Power Switch

2.0M

1/16W5%

402MF-LF

R4219

1

2

10V603CERM-X5R

0.33UF C4219

MF-LF5%

10K

2

402CERM5%

SOI-HF

NDS9407

CRITICAL Q4260

5678

4123

20%

CERM16V402

0.01uF

25%

402MF-LF

470K R4260

330K R4261

1

23

SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

FireWire Port Power

051-8089 42

PPBUS_FW_FWPWRSW_F

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=12.6V VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mm

=PPBUS_S5_FWPWRSW

FWPWR_EN_L_DIV

FW_PORTPWR_EN SMC_ADAPTER_EN

FWLATEGV_3V_REF

LATEVG_EVENT_L P2V4_FWLATEVG_RC

Trang 37

TPA- TPB+

TPB-GROUND POWER

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

Place close to FireWire PHY

(Common to all ports) for snap-back diodes ESD and late-VG rail

Late-VG Protection Power

to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4390 should be 390 Ohms max for a 3.3V rail

NOTE: FireWire TPA/TPB pairs are NOT

FireWire TPA/TPB pairs to their

(NONE)

PP2V4_FWLATEVG needs to be biased

(NONE)

BOM options provided by this page:

NOTE: This page is expected to contain

the necessary aliases to map the

appropriate connectors and/or to

properly terminate unused signals.

constrained on this page It is

assumed that FireWire PHY page will

provide the appropriate constraints

to apply to entire TPA/TPB XNets.

1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)

Signal aliases required by this page:

"Snapback" & "Late VG" Protection

NOTE: TRACE PPVP_FW_PORT1 MUST HANDLE UP TO 1A

PORT 1

FireWire PHY Config Straps

- 1-port Portable Power Class (0)

1/16W1%

402MF-LF

R4362

1

2

25V5%

402CERM

220pF C4364

1

2

4021%

6.3V

0.33UF C4360

R4360

1

2

X7R10%

BAV99DW-X-G DP4310

4

53

50V402

2

1/16W1%

402MF-LF

332 R4390

1 2

SOT23

CRITICAL MMBZ5227BLT1H D4390

13

MF-LF4021/16W

56

34

SMTCM2010-100-4P

CRITICAL

FL4320

1

23

678

50V402

330K

2

4021/16W

FireWire Ports

SYNC_MASTER=K36B_MLB SYNC_DATE=(MASTER)

109 02

FW_PORT1_TPB_N FW_PORT1_TPB_P

FW_P0_TPBIAS FW_P2_TPBIAS FW_P0_TPA_P

=PPVP_FW_PHY_CPS_FET

FW_P2_TPB_P FW_P0_TPB_P

=FW_PHY_DS0

=FW_PHY_DS1

FW_PORT1_TPB_C FW_P1_TPB_N

Trang 38

IN

D

SG

D

SG

ININ

SYM_VER-1

OUTOUT

SYM_VER-1

ININ

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

SYSTEM (SLEEP) LED FILTER

PLACE R4550 AND C4550 NEAR J4501(TO IR RECEIVER)

NCNCNC

PLACE R4522 AND C4522 NEAR J4501NC

ensure the drive is unpowered in S3/S5.

MF-LF4025%

100K R4595

10%

402CERM

0.068UF

10V

C4595

12

16VCERM402

0.01UF C4596

23456789

4.7UF

6.3V603CERM20%

C4550

12

5%

1/16W402MF-LF

100

R4550

CERM40216V

0.01UF

C4522

12

NO STUFF

0.1UF

16V402

C4590

12

L4501

34

4020.01UF

C4503

1 2

0.01UF402

PLACEMENT_NOTE=PLACE FL4525 CLOSE TO J4500

FL4525

34

FL4520

12

71

16V10%

SYNC_DATE=08/17/2008SYNC_MASTER=K36B_MLB

SATA Connectors

051-8089 45

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N SATA_ODD_R2D_UF_N

SATA_ODD_R2D_UF_P

PP5V_SW_ODD

MIN_LINE_WIDTH=0.6mmVOLTAGE=5VMIN_NECK_WIDTH=0.4mm

SATA_HDD_R2D_C_PSATA_HDD_R2D_UF_P

SATA_HDD_D2R_NSATA_HDD_D2R_C_N

IR_RX_OUT

ODD_PWR_SS ODD_PWR_EN_LS5V_L

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