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 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev 6

SN74LS373/D

SN74LS373 SN74LS374

Octal Transparent Latch

with 3-State Outputs;

Octal D-Type Flip-Flop

with 3-State Output

The SN74LS373 consists of eight latches with 3-state outputs for

bus organized system applications The flip-flops appear transparent

to the data (data changes asynchronously) when Latch Enable (LE) is

HIGH When LE is LOW, the data that meets the setup times is

latched Data appears on the bus when the Output Enable (OE) is

LOW When OE is HIGH the bus output is in the high impedance state.

The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop

featuring separate D-type inputs for each flip-flop and 3-state outputs

for bus oriented applications A buffered Clock (CP) and Output

Enable (OE) is common to all flip-flops The SN74LS374 is

manufactured using advanced Low Power Schottky technology and is

compatible with all ON Semiconductor TTL families.

• Eight Latches in a Single Package

• 3-State Outputs for Bus Interfacing

• Hysteresis on Latch Enable

• Edge-Triggered D-Type Inputs

• Buffered Positive Edge-Triggered Clock

• Hysteresis on Clock Input to Improve Noise Margin

• Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES

Temperature Range

LOW POWER SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SOIC

DW SUFFIX CASE 751D

http://onsemi.com

2500/Tape & Reel

PLASTIC

N SUFFIX CASE 738

20 1

20 1

CONNECTION DIAGRAM DIP (TOP VIEW)

Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs

D0 – D7 LE CP OE

O0 – O7

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

65 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

15 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

(Note a)

LOADING PIN NAMES

NOTE:

The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

18 17 16 15 14 13

1 2 3 4 5 6 7

20 19

8

VCC

OE

O7 D7 D6 O6 O5 D5 D4

O0 D0 D1 O1 O2 D2 D3

9 10

O3 GND

12

O4 LE

18 17 16 15 14 13

1 2 3 4 5 6 7

20 19

8

VCC

OE

O7 D7 D6 O6 O5 D5 D4

O0 D0 D1 O1 O2 D2 D3

9 10

O3 GND

12 11

O4 CP 11

TRUTH TABLE LS373

LS374

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE)

3

LOGIC DIAGRAMS SN74LS373

SN74LS374

D

D

G Q

CP

Q Q CP

OE

OE LE

LATCH ENABLE

O0 O1 O2 O3 O4 O5 O6 O7

D0

14

1

7

11

13

15

VCC = PIN 20 GND = PIN 10 = PIN NUMBERS D

G Q

D1

D

G Q

D2

D

G Q

D3

D

G Q

D4

D

G Q

D5

D

G Q

D6

D

G Q

D7

17 18

19

D0

14 7

1

11

D CP

Q Q

D CP

Q Q

D CP

Q Q

D CP

Q Q

D CP

Q Q

D CP

Q Q

D CP

Q Q

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

All Inputs

All Inputs

or VIL per Truth Table

VIN= VILor VIH

VIN = VIL or VIH per Truth Table

0.1 mA VCC = MAX, VIN = 7.0 V

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits

tPLH

tPHL

Propagation Delay,

Data to Output

12 12

18

C = 45 pF

tPLH

tPHL

Clock or Enable

to Output

20 18

30 30

15 19

28

CL = 45 pF,

RL = 667 Ω

tPZH

15 25

28 36

20 21

28

tPHZ

12 15

20 25

12 15

20

AC SETUP REQUIREMENTS (TA = 25 ° C, VCC = 5.0 V)

Limits

DEFINITION OF TERMS

SETUP TIME (t s ) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to LE transition from HIGH-to-LOW in order to

be recognized and transferred to the outputs.

HOLD TIME (t h ) — is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.

5

SN74LS373

AC WAVEFORMS

Figure 1.

tW tW

LE 1.3 V

OUTPUT

Dn

tPLH tPHL

1.3 V

1.3 V 1.3 V OE

VOUT

OE

VOUT

tPHZ

1.3 V 1.3 V

VOL 1.3 V

VOH

0.5 V

tPZH

0.5 V

SW2

CL* 5.0 k Ω

SW1

VCC

RL

TO OUTPUT

UNDER TEST

Figure 4.

* Includes Jig and Probe Capacitance

AC LOAD CIRCUIT

SWITCH POSITIONS

Closed Open Closed Closed

Open Closed Closed Closed

tPZH

tPZL

tPLZ

tPHZ

SW2 SW1

SYMBOL

AC WAVEFORMS

OE

VOUT

1.3 V 1.3 V

VOL 1.3 V ≈ 1.3 V

0.5 V

SW2

CL* 5.0 k Ω

SW1

VCC

RL

TO OUTPUT

UNDER TEST

* Includes Jig and Probe Capacitance

AC LOAD CIRCUIT

CP

Dn

OUTPUT

tPLH

tWH tWL

1.3 V 1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

ts th

tPHL

Figure 5.

1.3 V

1.3 V 1.3 V OE

VOUT

tPHZ

≥ VOH 0.5 V

tPZH

≈ 1.3 V

Figure 6.

Figure 7.

Figure 8.

SWITCH POSITIONS

Closed Open Closed Closed

Open Closed Closed Closed

tPZH

tPZL

tPLZ

tPHZ

SW2 SW1

SYMBOL

7

PACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE CASE 738–03 ISSUE E

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982

2 CONTROLLING DIMENSION: INCH

3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL

4 DIMENSION B DOES NOT INCLUDE MOLD FLASH

M L

J 20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERS INCHES

A 1.010 1.070 25.66 27.17

B 0.240 0.260 6.10 6.60

C 0.150 0.180 3.81 4.57

D 0.015 0.022 0.39 0.55

G 0.100 BSC 2.54 BSC

J 0.008 0.015 0.21 0.38

K 0.110 0.140 2.80 3.55

L 0.300 BSC 7.62 BSC

M 0 15 0 15

N 0.020_ 0.040_ 0.51_ 1.01_

E

1.27 1.77 0.050 0.070

1

11

10 20

–A–

SEATING

PLANE

K N F

G

D20 PL

–T–

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC 0.050 BSC

D SUFFIX

PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F

20

1

11

10

B

20X

C

A

SEATING PLANE

q

E

D

M

0.25 T A S B S

e

T B

A

DIM MIN MAX MILLIMETERS

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49

C 0.23 0.32

D 12.65 12.95

E 7.40 7.60

e 1.27 BSC

H 10.05 10.55

h 0.25 0.75

L 0.50 0.90

q 0 7

NOTES:

1 DIMENSIONS ARE IN MILLIMETERS

2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

3 DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION

4 MAXIMUM MOLD PROTRUSION 0.15 PER SIDE

5 DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE PROTRUSION SHALL

BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION

_ _

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