MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 15 doc

These are 1 the Level 1 model-a first order model suitable only for long channel devices; 2 the Level 2 model that includes various second order effects present in small geometry devices

SPICE Diode and MOSFET

In this chapter we will discuss the pnjunction diode and MOSFET models,

as implemented in Berkeley SPICE2G and higher versions No attempt will be made to derive the model equations, as that has already been done

at appropriate places in previous chapters Here we will only describe equations used to model different regions of device operation Emphasis will be on model parameters required to run SPICE and how to measure them

Berkeley SPICE has four different MOSFET models of varying complexity and accuracy [1]-[3] These are (1) the Level 1 model-a first order model suitable only for long channel devices; (2) the Level 2 model that includes various second order effects present in small geometry devices, and is considered to be a physical model; (3) the Level 3 model-a semi-empirical model that includes most of the second order effects described in the Level

2 model; (4) the Level 4 model, called the BSIM (Berkeley Short-channel Igfet Model), that is a parameter based model These different models can

be activated by a parameter called LEVEL We will describe all four levels

of MOSFET model equations and their parameters However, first we will describe the diode model parameters and how to determine them

generally assumed for silicon p n junction diodes For other type of diodes

such as SBD (Schotkey Barier Diode), parameter X T Z needs to be changed

In what follows we will discuss extraction for the first seven parameters

11.1 Diode Model 537

Table 11.1 SPICE Diode model parameters

Parameter SPICE

name in parameter Parameter

the text name description

Default value Units

p n junction potential

p n grading coefficient transit time

reverse breakdown voltage band-gap voltage

1.1 eV 3.0

where I,, rs and y are model parameters that can be determined either

using linear regression methods, as discussed in section 9.14 or a nonlinear optimization method (cf Chapter 10) In the latter case we fit the experi-

mental I , versus V, data to model equation (11.1) such that

(1 1.2)

is minimum, where Vexp and Vca, are the measured and calculated V,,

respectively, and 1 is the number of data points The result of this curve

fitting is shown in Figure 11.1 for a typical n + p diode fabricated using a

l p m CMOS process The values for the parameter I,, q and r , for two

types of diodes (n'p and p'n) are shown in Table 11.2 For comparison the parameters obtained using the linear regression method (cf section 10.14) are also shown in this table

Note that extracted parameter values from two different methods are not exactly the same However, for circuit simulation purposes, the parameter

538 11 SPICE Diode and MOSFET Models

DIODE FORWARD VOLTAGE, Vd (V)

Fig 11.1 Plot of log(1,) versus V, for a n’p diode Circles are experimental points

while continuous line is nonlinear least-square lit to Eq (1 1.1)

Table 11.2 Diode parameters I,, n and R,

Linear Optimization Linear Optimization regression method regression method

The parameters C j o , 4 and m describe the junction capacitance due to the space charge in the junction depletion region When the junction reverse voltage vd is less than 4/2, the junction capacitance C j is given by the following equation [cf Eq (2.74)]

(11.3)

where C j o varies from device to device, but is typically of the order of

1.0 x pF/pn2 The barrier potential 4 is usually about 0.5-0.7 V and the gradient factor m is assumed to be between 0.333 (linearly graded

Very often, C j o is also treated as a parameter to be optimized along with

4 and m rather than taking its value from measured data This is because

3 parameters (Cjo, 4 and m) when optimized together give better fit over

the entire data range of interest (see Figure 2.19 and Table 9.4)

Transient Time z, The parameter z, is the diode transit time and is used

to calculate the diode diffusion capacitance C,, [cf Eq (2.77)] when the diode is forward biased Typical values of z, range from 1 to 100 nsec There are different electrical methods to calculate transit time z,, like the voltage decay method, the reverse recovery method, etc [4] However, the simplest method of obtaining z, is to compute it from the reverse recovery

method In this method, we measure the diode storage time t, by switching

the diode from a forward voltage V ’ to a reverse voltage V,, and using the following equation [4]-[6]

.-

(11.4)

where I, and I , are the forward and reverse current, respectively, when the

diode is switched from the forward voltage V, to the reverse voltage V,

Note that this equation requires evaluation of the error function, which is approximately given by [4]

erf(x) = ~ exp ( - z2)dz

h S’ o

Due to the complexity of Eq (1 1.4), the Newton-Raphson method is needed

to compute Z, and is thus fairly involved However, the following simple equation is often used to calculate z,

As shown in Figure 11.2, there is a discrepancy of 30% between the z,

calculated using Eqs (11.4) and (11.6) even when I, >> I, Therefore, it is

advisable to use Eq (11.4) While using Eq (11.6), it has been suggested

that I J > > Z , must be kept in the measurements This way, the affect of

540 11 SPICE Diode and MOSFET Models

Fig 11.2 Plot of t J t t versus IJ/Ir using Eq (11.4) (continuous line) and (11.6) (dotted

line) Continuous line predicts more exact value of z,

1 + Ir / I f

Fig 11.3 Plot of t , versus (1 + I f / I , ) for a n'p diode using Eq (11.6) Circles are

experimental points while continuous line is linear regression of Eq (11.6)

recombination in the heavily doped region is entirely eliminated [4] Under these conditions, the plot of t , versus ln(1 + If/Ir) will be a straight line (see Figure 11.3) the slope of which gives 7, The plot will be highly curved

if the condition I , >> I, is not met and then a unique value of lifetime can

no longer be extracted

HP 7550A PLOTTER

- - - - -

Fig 11.4 Test setup for measuring storage time using reverse recovery method

Equipment required for measuring z, are (1) a fast pulse generator such as

an HP8116A, (2) a fast oscilloscope, such as a Tektronix 7854 or an HP54111D with dual trace plug-in, and (3) an X-Y recorder (optional) The advantage of the HP8116A function generator is that it can supply an asym- metric pulse waveforms However, if not available, two pulse generators are needed to adjust the voltages Vr and V , independently The test configu- ration is shown in Figure 11.4 The time delay due to connectors and series resistance in the circuit should be carefully minimized The resistor R,

(350 a) is chosen such that the DC current flowing into the diode is limited within the range of f 15 mA for voltages between Vr = 8 V (forward bias) and V, = - 3 V (reverse bias) and the RC delay time introduced by this

resistor is negligible as compared to the diode transit time

During forward bias (at t = 0-), a positive voltage (Vs = 8 V) at f = 100 Hz was applied to the circuit The current was then calculated by dividing the

Fig 11.5 Storage time t, as a function of input pulse for n'p diode

542 1 I SPICE Diode and MOSFET Models

Table 11.3 Diode transit time t,

calculation using nS nS

Error function Eq (1 1.4) 241.3 415

Log function Eq (1 1.6) 339 -

voltage measured on resistor R, (50 0) At t = 0, a negative voltage is applied

to the diode; the input pulse changes from + 8 V to - 3 V at t = 0 The

diode storage time was measured as the time from beginning of the reverse current transition to the time when the reverse current begins to

decay toward its leakage current value (see Figure 11.5)

The lifetime z calculated using the above method for both n + p and p + n

diodes are shown in Table 11.3 Note the difference between z, calculated

using Eqs (1 1.4) and (1 1.6)

11.2 MOSFET Level 1 Model

The level 1 model is often referred to as the Shichman-Hodges model It

is the simplest of the four MOSFET models in SPICE and is accurate onZy for long channel devices

11.2 MOSFET Level 1 Model 543 Note that the channel length modulation factor, I , is included in both the linear and saturation regions, so as to make the current and its first derivative continuous, as was explained in section 6.4.1 Also note that the subthreshold current is zero

In addition to the intrinsic MOSFET DC current equations described above, one needs to model the source/drain (S/D)-to-substrate pn junctions

Since in the normal operation of the device these junctions are reverse biased, the only DC parameter of the S/D junction which is of interest is

the saturation (leakage) current I , In SPICE this is specified as J,, the

saturation current per unit area, or I,, the total saturation current If J , is

specified then one needs to specify the source and drain areas A , and Ad,

respectively

11.2.2 Capacitance Model

The parameters of the dynamic model are the source/drain junction capacitances, the overlap capacitances, and the intrinsic MOSFET capaci- tances The junction capacitances are the sum of both the bottom-wall (area) capacitance and side-wall (periphery) capacitance The source diode capacitance C,, is computed as follows [cf Eq (3.26)]

(11.10)

where A , and P , are the area and periphery of the source-to-bulk pn junction,

respectively, and Cjo and Cjswo are the junction capacitance per unit area

and per unit periphery, respectively, at zero back bias A similar equation

holds for the drain-to-bulk junction capacitance CBD These equations are used for all SPICE models

The intrinsic device capacitances (also sometimes referred to as gate oxide capacitances) are based on the Meyer model (see section 7.1.1) There are only three intrinsic capacitances C,,, C,, and CGB in the Meyer model Their values change with bias conditions as follows:

Strong Inuersion Region In the strong inversion region when V,, > Vth, the gate capacitance is calculated using the following relations:

Linear Region: In this case Vgs > (vth + Vd,)

(1 1.1 la)

(1 1.1 1 b) (1 1.1 lc)

544 11 SPICE Diode and MOSFET Models

Saturation Region: In this case V,h < V,, < (V,h + V&)

The overlap capacitances C,,,, CGD0 and C,,, are then added to C,,, CGD

and C,,, respectively, in different regions of device operation and are calculated from the following equations:

In addition to the model parameters shown in Table 11.4, the device parameters shown in Table 11.5 are also required These device parameters

546 11 SPICE Diode and MOSFET Models Table 11.5 Device parameters

Parameter SPICE

wm W Drawn Channel width (mask dimensions) m

As

A d AD Drain diffusion area 0.0 m2

PS Perimeter of the source diffusion window 0.0 m

ps

P d PD Perimeter of the drain diffusion window 0.0 m

- NRS Number of squares in the source diffusion 1.0 m

~ N R D Number of squares in the drain diffusion 1.0 ~

electrical parameters will always override the value computed from

process parameters, if also specified Thus, if V T O , N S U B and T O X are

input, the threshold voltage will assume the value entered as V T O , while

G A M M A will be computed from N S U B and T O X Similarly, if K P is

not specified but UO is specified, then K P will be computed using either

the specified value of T O X or its default value, if not specified

If V T O is not an input parameter then one needs to specify N S U B ,

T O X and T P G , which are then used to calculate V,, using Eq (5.15) The last parameter T P G denotes the type of the gate and can take any

of the following three values

+ 1 for gate type opposite to the substrate

T P G = - 1 for gate type same as the substrate (11.16)

and is used to calculate Qms and hence V,,(= Q m s - qN,,/C,,) [cf

Eq (4.14)], as follows:

I 0 for aluminum gate

- 0.5 - 0.5E, - 0.54, for TPG = 0

f o r T P G = - 1

where E , is the energy gap for silicon [cf Eq (2.3)]

SPICE sets all parameters to the default values if negative values are

input by the user, with the exception of V T O , T P G and N S S Thus, if

G A M M A is specified as a negative value, then SPICE assumes it to be zero, which is the default value

0 For a p-channel enhancement and an n-channel depletion device V T O

is negative, while it is positive for n-channel enhancement devices Recall that p-channel depletion devices are not fabricated, but if simulated, their

V T O will be positive

Qms = 1 - 0.5E, 0.5E, - - 0.54, 0.54, for TPG = 1 (11.17)

11.2 MOSFET Level 1 Model 541

0 The default value of T O X = lo-’ m (1000 A) is valid for the Level 2 and

higher level models If T O X is not specified for LEVEL = 1, then T O X

acts as a flag and “turns off” the use of process parameters resulting in the omission of intrinsic capacitance calculations

0 The parameter LAMBDA in the Level 1 model defaults to zero if it

is not specified However, this is not the case in the Level 2 model as

we will see later

Some parameters in the model may be specified in more than one way For example, reverse or saturation current of the junction can be specified

either as I S or J S Whereas the first is an absolute value, the second is

multiplied by AS and AD to give the saturation current of the source and drain junctions, respectively However, the advantage of specifying

J S is that the resulting value of the saturation current becomes specific

to each junction of each transistor; unlike giving I S , which will result in the same value of the saturation current for all sourceldrain junctions Similarly, the zero-bias depletion capacitances can be specified by C J ,

which is multiplied by AS and A D , and by CJSW which is multiplied by

PS and PD specific to each single device Or, they can be set by CBD

and CBS, which are absolute values

The parasitic ohmic resistances of the source and drain junctions can be specified either by RD and RS which are the absolute values, or by R S H

which is multiplied by N R S and NRD

If both I S and J S are specified, I S overrides JS

Model Parameter Determination Determination of all Level 1 parameters, except that of K (KP) and 2 (LAMBDA) have been discussed earlier The

parameter LAMBDA is a saturation region parameter and can be determined from the slope of the I d , versus v d , curve in the saturation region

(V,, > Vd,,,) by dividing the slope value by the y-intercept The slope in the saturation region is very small, and therefore care must be exercised in its determination The parameter K P can be determined either from the slope

of the linear region plot of I d , versus Vgs at low Vd, or from the slope of

a typical 2pm CMOS technology, the value of K P obtained from linear region data is 27 pA/V2, while the corresponding value obtained in saturation is 22pA/V2 Clearly, the value of K P obtained from the two methods is different because the mobility degradation due to the gate field

is not taken into account in this model Since SPICE allows only one value

to be used for both linear and saturation regions, it is more appropriate to use an optimizer to extract K P along with other parameters

548 11 SPICE Diode and MOSFET Models

11.3 MOSFET Level 2 Model

The Level 2 model incorporates many of the second order effects for small size devices It can model a reasonable range of device sizes, but is

computationally quite complex

11.3.1 D C Model

The threshold voltage equation for the SPICE Level 2 model is

' r h = V T o - Y + ?/FIJm + F w ( 2 4 f + 'sb) (1 1.18)

where F , is the short channel factor based on Yau's modified model as

given by Eq (5.94) and Fw is the narrow width factor based on a simplified thick field oxide model [cf Eq (5.91)] given by

(11.19)

Linear Region Current The drain current in the linear region is given by

zds=Ijeff[('gs- v , * , - ~ r ] V ~ s ) ' ~ s - ~ ? / F l { ( V ~ s + 2df + Vsb)3i2

- (24f + ' s b ) 3 i 2 11 (11.20) where

(1 1.21a)

(1 1.2 lc)

(1 1.21e) (11.21f) and L, is the drawn channel length, while Ldif is the side diffusion [cf

Eq (3.31)] Note that the channel length modulation (CLM) factor /z is

used for both linear and saturation regions of device operation, so as to make the current and its first derivative continuous from linear to saturation region, as was explained in Chapter 6

Saturation Voltage The saturation voltage V,,,, is calculated in one of two ways If the maximum carrier drift velocity u,,, is assumed zero, then V,,,,

549 11.3 MOSFET Level 2 Model

is calculated Using a pinch-off model (i.e., I d s / I / d s = 0 at Vds = Vdsa,, as discussed in section 6.4.1), otherwise i t is calculated using the velocity saturation model

Vdsat using the pinch-off model: In this case VdSa[ is calculated from the following equation:

Eqs (1 1.25) and (1 1.21e) However, SPICE uses the following closed form

solution by making the approximation that Leff = L in Eq (1 1.25) With

this approximation one can write Eq (11.25) in a somewhat more manage- able form, if the following substitutions are made

(1 1.26a)

550 11 SPICE Diode and MOSFET Models

(1 1 26~ ) (1 1.26d) With this substitution, Eq (1 1.25) becomes:

(1 1.27)

It is clear that the above equation can be written as a fourth order

polynomial equation in X as:

Equation (11.27) is solved for X using a closed form method known as

Ferrari’s method Once X is known, it is a trivial matter to obtain Vd,,,

from Eq (11.26d) Since Eq (11.27) is a fourth order polynomial equation,

it has four possible solutions The smallest positive solution is taken to be the valid solution If no positive real roots are obtained, then vd,,, is evaluated using the pinch-off model, Eq (1 1.22)

Leff Calculation The Leff is calculated using Eq (11.21e)

and depends upon whether or not the CLM term il has a finite value If 2 = 0 is input to the model parameter file, then channel length modulation

is not taken into account and Leff = L However, if 1 is not input then it

is calculated internally Depending upon the value of urnax, il is calculated

from either of the following two equations:

If u,,, 2 0 , V,,,, is calculated using the pinch-off model, Eq (11.22), while the effective channel length is evaluated using the following

11.3 MOSFET Level 2 Model 551 equation:

Note that X , used in Eqs (11.30) and (1 1.31) are different This is because

Eq (1 1.30) does not provide an accurate description of the output

conductance in saturation and Neff has to be used as an empirical factor

to change the substrate doping to NeffNb The larger the N e f f , the smaller

the output conductance becomes The range of Neff is normally between

1 and 5

Saturatioiz Region Current In this region, V,, > v&,, and current is calculated

using Eq (11.20) with VdS replaced by Vdsat

Subthreshold Current The current in the subthreshold region is calculated using the following equation:

(1 1.32) where

V,, makes the transition from weak to strong inversion regions

The DC parameters for Level 2 model are shown in Table 11.6 In this table only those parameters are included which are in addition to the Level

1 parameters shown in Table 11.4

552 1 1 SPICE Diode and MOSFET Models Table 11.6 S P I C E Level 2 model parameters These are in addition to those shown in Table I I .4

Parameter SPICE

name in parameter Parameter

the text name description

Default value Units Level

1

0.0 0.0 0.0 0.0 0.0 0.0

1

0.0

1 .0

1 1 0 4

Note the following:

The parameter LD accounts for the diffusion effects in the device length

direction giving an effective channel length L as

L = L, - 2Ldi,

The UC Berkeley implementation of the Level 2 model does not

have the parameter WD( = AW) for calculating the effective device width from drawn dimensions resulting in W, = W

The parameter U T R A (cf Eq 11.21~) does not exist in the Berkeley version, but it is included here because it exists in most of the Level 2

models in commercially available implementations of SPICE

If X J is not specified, the narrow channel effect is neglected

If N F S is not specified, the subthreshold current is not calculated

If N F S is not specified, Vo, = Vth

If V M A X is not specified, the velocity saturation effect is neglected

11.3.2 Capacitance Model

The MOSFET source and drain junction capacitance models are the same as for Level 1 However, for MOSFET intrinsic capacitances there are two models available The first model, which is also the default model,

is the Meyer model as described for Level 1; the only difference being that

F h is replaced by Van The second model is the charge controlled model of Ward and Dutton [9] The parameter X Q C is associated with partioning

11.3 MOSFET Level 2 Model 553

Table 11.7 Charge sharing for Level 2 capacitance model

Source Charge Qs Drain Charge QD

Saturation Region X Q C ’ Q I (1 - XQCIQi

of the charge (see section 7.2) In the Level 2 model the following scheme

is used to partition the channel charge Q I into the source and drain charges,

Qs and Q D , respectively, (see Table 11.7) The X Q C 2 0.5 is user input model parameter and indicates portion of the charge attributed to the drain It also acts as a flag; X Q C = 1 invokes the Meyer model The parti- tioning scheme causes discontinuity at the boundary of the linear and saturation regions, except when X Q C = 0.5 Note that when X Q C = 1, then

in saturation Q D = 0

Model Parameter Determination The parameters of this model may be divided into two parts; (1) basic parameters which are basically long channel model parameters like VTO, KP, GAMMA and PHI and (2) parameters relative to second order effect not included in the basic model, and describe narrow and short channel behavior We have already discussed parameters

in the first part which are linear region parameters extracted using linear regression methods However, the linear regression method to calculate the saturation region parameters, such as VMAX, or short-channel and narrow-

width parameters, are not straight forward It is best to determine these second order parameters using an optimizer as discussed in Chapter 10 The presence of the parameter NFS permits calculation of the subthreshold

current in the model The parameter can be calculated using Eq (6.102)

and (6.11 3) For long channel device

(11.33)

where S is the subthreshold slope The parameters y and 4f need to be

known and can be determined from V,, versus V,, measurements The

extracted value is normally very high ( N f s = 9.3 x 10” cm-*), although fast surface states for the process are less than 10’0cmp2 The NFS is treated simply as a fitting parameter This model does not insure good correlation with measurements

The Level 2 model, though physically based, has various drawbacks For example, the transition from linear to saturation regions is not smooth, particularly for short-channel devices, and there is a small discontinuity in the transition from subthreshold to saturation region

554 1 1 SPICE Diode and MOSFET Models

11.4 MOSFET Level 3 Model

The Level 3 is a semi-empirical model that includes second order effects due to short-channels and narrow-widths The model is computationally efficient compared to the Level 2 model, but the empirical model parameters become geometry dependent

11.4.1 DC Model

The threshold voltage equation for the SPICE Level 3 model is

(11.34)

where F , is a short channel factor based on Dang’s model, as given by

Eq (5.73), F , is a narrow width factor as in Level 2, except that the factor of 4 is replaced by 2, and CT is the DIBL parameter given by [cf Eq

11.4 MOSFET Level 3 Model 555

Saturation Voltage VdSat is calculated from one of the following equations (see section 6.7.2)

(if u,,, specified)

and Idsat is the drain current at saturation obtained by replacing V,, with

VdSat in Eq (11.35) and Gdsat is the drain conductance at saturation The

fitting parameter accounts for the fact that the voltage across the depleted

surface of the channel, of length l,, is less than V,, - V,,,,

Gdsat = _

d V d , , ,

Subthreshold Region Current It is given by the same equation as for the

Level 2 model [cf Eq (11.32)] except that I, now is calculated at V,, = V,,

using Eq (11.35)

The SPICE Level 3 DC model parameters are shown in Table 11.8 These parameters are in addition to the Level 1 parameters shown in Table 11.4,

except for the parameter LAMBDA, which is not used in Level 3

The model parameters are generally extracted using an optimizer Often the value of VMAX is 3-5 times higher than the physical value To get a more realistic value, it has been suggested [13] to introduce one more

556 11 SPICE Diode and MOSFET Models

Table 11.8 SPICE Level 3 model parameters These are in addition t o those shown in Table 11.4

Parameter SPICE

name in parameter Parameter Default

I

0.0 0.0 m 0.0 cm-* 0.0 V - ' 0.0

VMAX of the Level 2 model, the VMAX parameter in level 3 is used in a very different form and is fairly easy to extract from a linear regression method

The capacitance model (intrinsic and extrinsic) is the same as level 1 model

11.5 MOSFET Level 4 Model

The MOSFET Level 4 model is generally known as BSIM and is in fact

a modified form of CSIM (Compact Short-channel Igfet Model) [2] This

is a parameter based model whose parameters are generally extracted using automated extraction procedures using linear regression [ 101 Since the model has many parameters which are bias dependent, care must

be taken in extracting these parameters

11 S.1 DC Model

In this model, threshold voltage is expressed as [cf Eq (5.46) and (5.96)]

yh = vJb + 24f + Y J m + Kl(24f + vsb) - Ovds (11.41)