MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 7 doc

The small geometry V,, model for n-channel MOSFET with fully recessed isolation oxide will be [67] 5.116 5.4 Temperature Dependence of the Threshold Voltage The threshold voltage of l

while

where

and V i s is given by Eq (5.101) The above model for V,, shows an approxi-

mately inverse quadratic dependence on channel length L and an inverse dependence on oxide capacitance Cox It should be pointed out that the

weak dependence of the short-channel effect on the junction depth X j has

not been taken into account In normal enhancement devices, this effect is

small Figure 5.26 shows the V,, variation with drain bias for two different

back bias ( K b = 0 V and V,, = - 2 V) Continuous lines are experimental data while dashed lines are based on Eq (5.102) As can be seen, agreement between the experimental data and the model is fairly good

Empirical Approach Very often in actual devices, the exponential depen-

dence of the DIBL effect on L is not observed In such cases an empirical

approach is often used, assuming the surface potential to be constant along the length of the channel, even for short channel devices This assumption results in a very simple expression for cr, which can be derived as follows [79]:

When V,, is small (< 0.1 V), the substrate depletion region width X , , may

be calculated using the Poisson equation When V,, is large, an additional

potential will be imposed in the region already depleted Since no additional charge appears in Poisson’s equation, this additional potential satisfies the Laplace equation:

d2V,

~ = 0

Under the simplifying assumptions that (1) source/drain junction depths are small compared to the channel length, and (2) using the approximate boundary conditions that I/, = 0 at the source region and I/, = V,, at the

drain region, we can solve Eq (5.103), resulting in the following expression for the field E , at the source end 1791

and N b The exponent m of L varies in the range 1-3 The back bias

dependence of m has also been proposed [83], but for circuit models, it is

more appropriate to take m as constant as is done in almost all empirical

models [SO] SPICE Level 3 model uses Eq (5.106) with m = 3, CJ, = 0 and

o0 as a fixed constant value, not a fitting parameter The threshold voltage

as a function of drain bias for a typical n-channel 1 pm CMOS technology

at two substrate bias is shown in Figure 5.29 Symbols are experimental data while dashed and continuous lines are based on Eq (5.106)

Based on a 2-D solution, Masuda et al [ S 2 ] have proposed the following

DRAIN VOLTAGE, Vd, (VOLTS)

Fig 5.29 Variation of threshold voltage with drain voltage at two different back bias V,, = 0 and 3 V with channel length as a parameter for a typical n-channel 1 pm CMOS process

A slightly different form for the back bias v,b (through C,) dependence has also been proposed [84]

(5.109)

where cd is the depletion capacitance and is obtained by differentiating the bulk charge Qb For example, for a uniformly doped substrate, we can write

functional dependences on the channel length L Thus,

the charge sharing models show a v,, dependence of 1/L,

the empirical models show v,, dependence of 1/L" (1 < n < 3),

the 2-D models show V,, dependence of exp( L/Lo)

The dependencies are quite different and do cause confusion as to which model is valid Obviously, the model to choose depends upon the process technology It has been found that for circuit models Eq (5.106) is fairly

general and fits most of the technology data the author has come across

5.3.4 Small-Geometry EfSect

When both the device width W and length L are small, that is, when both

W and L are of the same order of magnitude as the depletion width X d m ,

then the device is called a small geometry device." For example, in a 2 pm

geometry device A first order estimate of the threshold voltage induced

by small-geometry effect can be obtained by superposing the short-channel and narrow-width effects such that

AVfh = AKhJ + AVth,W

so that the total threshold voltage at low V,, for small-geometry devices becomes

(5.112)

This is the approach used in most of the circuit simulators, including SPICE However, Eq (5.112) overestimates AVth due to the small-geometry effect This is because short-channel and narrow-width effects are not really independent as assumed in Eq (5.112) In fact, there is a coupling between

these two efects which results in a compensating e f e c t This is because

both W and L determine the gate controlled charge and the volume of the charge must be properly identified Therefore, mere addition of the two effects does not accurately predict Kh

We will develop a simple model for small small-geometry devices based

on Yau's charge sharing approach which will illustrate this compensating effect on Vth Figure 5.30 shows one side of the extra charge AQJ2 in the

depletion region due to the narrow width effect for an assumed triangular region Since the short-channel effect reduces the bulk charge, the resulting geometry indicated by the dotted line shows the amount of the extra charge induced due to short-channel effect The volume V of the extra charge that is responsible for AVth,W is obtained by first finding the wedge volume and then subtracting the volume of the pyramid shape regions shown by

l o A device with minimum L and W allowed by the process technology is referred to as

the minimum size device for that technology

where the factor of 2 accounts for both sides of the device and X , is given

by Eq (5.65) The compensated depletion charge due to width effect becomes

(5.113)

Comparing this equation with Eq (5.88) clearly shows the effect of the

short channel on the extra charge in the width direction From Yau’s model [cf Eq (5.66)] we have

so that AV,, due to the small geometry effect is obtained by adding Eqs (5.113) and (5.114) as

Clearly, the change in threshold voltage due to the small geometry effect

is reduced by the extra term that originates due to the compensating effect This is basically the model proposed by Merckel [S7] Note that the value of

the fitting parameter G, will be different when used with Eq (5.88) Others

[89] have also proposed models for the small-geometry effect, but they are not very different from the above model

The small geometry V,, model for n-channel MOSFET with fully recessed

isolation oxide will be [67]

(5.116)

5.4 Temperature Dependence of the

Threshold Voltage

The threshold voltage of long channel implanted MOSFETs is given by

Eq (5.63) and is determined by device physical parameters, such as flat band voltage Vfb, bulk Fermi potential 4,, and body factor y Since both

4 , (cf section 2.4) and V,, (cf section 4.7) are temperature dependent,

V,, is also temperature dependent In fact temperature dependence of

V,, is primarily governed by the temperature dependence of 4, and V,,

[30], [90]-[93] Recall that the magnitude of both g5f and V,, decreases with

increasing temperature, therefore the magnitude of V,, also decreases with

increasing temperature for both n- and p-channel devices Typically, the

curve (e) is for depletion type device All devices have n+ polysilicon gates The temperature

coefficient of V,, (dVth/dT) is shown on each curve

2 2 2 5 Threshold Voltage temperature coefficient of threshold voltage I dl/,h/dTI lies in the range 1-3mV/degree depending upon the type of MOSFET and its physical parameters such as gate oxide thickness to,, substrate concentration N , , etc

Measured values of the threshold voltage as a function of temperature for

different types of long-channel MOSFETs are shown in Figures 5.31 and

n-channel enhancement type devices, while curve (e) is for n-channel deple- tion type device; all these devices are with n+ polysilicon gates While curves (a), (b) and (c) are for channel implanted devices, curve (d) is for uniformaly doped device Although both curves (b) and (c) are for enhance-

ment devices, curve (b) has higher t0,(300A), and lower surface concen-

tration (3 x ~ m - ~ ) compared to curve (c), which has to, = 105 A and

N , = 3 x 10l6 ~ m - ~ The temperature dependence of V,, for p-channel

devices is shown in Figures 5.32; curves (a) and (b) are for n+ polysilicon

gates while (c) is for p + polysilicon gate The 1 dK:,/dTI is shown on each curve Note that in all these devices V,, varies linearly with the temperature This

linear dependence of V,, on temperature is valid down to 5 0 K [94,95] The temperature behavior of V,,, can easily be predicted from Eq (5.63)

Remembering that the temperature dependence of Vfb is governed by the temperature dependence of a,,,,, the work function difference between the

gate material and the substrate [cf section 4.7.11, differentiating Eq (5.63)

Fig 5.32 Measured threshold voltage variation with temperature for different types of

p-channel enhancement type MOSFETs Curves (a) and (b) are with n + polysilicon gate,

while curve (c) is with p + polysilicon gate

Tuth, of a MOSFET depends upon the following parameters:

The substrate concentration N , ; the higher the N , , the higher the $f, and therefore, the higher the Tuth At lower-temperatures 4f increases; therefore,

d will be reduced further and consequently, substrate sensitivity (change

lower the temperature, the lower the substrate sensitivity

The gate oxide thickness Lox; the higher the to,, the higher the body factor

y and hence higher the at term In other words, thicker gate oxides result

in higher Tuth

The back bias Vsb; the higher the Vsb, the lower the sd term, and con- sequently Tot,, becomes smaller at higher vsb This is evident from curve (a) and (b) (Figs 5.31 and 5.32) which are for Vsb = 3 V and 0 V, respectively

n-Channel Devices (nMOST) For n-channel enhancement devices (n'

polysilicon gate and p-substrate) &D,,/dT is given by Eq (5.120a) Since

Eqs (5.119) and (5.120) when used in Eq (5.117) almost compensate each other, it is the last term in Eq (5.117) that mainly contributes to the

temperature coefficient of Vth Furthermore, for implanted devices, V , and

224 5 Threshold Voltage

24f almost compensate each other, therefore d according to Eq (5.118) has a relatively larger value compared to unimplanted devices where V , is zero This explains why unimplanted devices have a lower temperature coefficient compared to the implanted devices (see curves (b) and (c) in

Figure 5.31) Since V,, increases d , Turh decreases (compare curves (a) and (b) in Figure 5.31) For n-channel depletion devices (n' polysilicon gate

and n-silicon surface), Eqs (5.120b) for a@,,/aT and (5.119) for a@,,/aT

when used in Eq (5.117), do not compensate each other, but rather add

up Therefore, all three terms of Eq (5.117) contribute to Tot,, resulting in

a higher temperature coefficient compared to enhancement devices (curve

e, Figure 5.3 1) For curve (d), higher Tuth is also due to higher to, ( = 420 A)

compared to 300w for curve b)

p-Channel Devices (pMOST) For p-channel devices with p + polysilicon gates, the situation is similar to that of n-channel enhancement devices

with n+ polysilicon gates and therefore, Tofh is almost the same as that of

CHANNEL LENGTH L ( pm) (a)

Fig 5.33 Variation of the temperature coefficient of threshold voltage To,,, as a function of

(a) channel length, (b) channel width, for a typical 1 pm CMOS process (After Arora [30].)

n-channel enhancement devices However, for p-channel compensated devices (n’ polysilicon gate and n-type concentration at the silicon surface), the situation is similar to n-channel depletion devices and therefore, T,)th

in this case is higher compared to that of surface channel p-devices (see curves (a) and (b) Figure 5.32)

For short channel devices, part of the gate induced charge is depleted from

the source and drain resulting in the effective body factor ( y F , ) being smaller

compared to the long channel value; recall that F , is less than unity for

short-channel devices [cf Eq (5.67)] Furthermore, since .d is directly proportional to y, Eq (5.1 18) predicts that Tvth will decrease with decreasing channel length This behavior is indeed observed experimentally as shown in Figure 5.33 where the dots are experimental points and the continuous

lines are based on the Eq (5.1 17)

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6 MOSFET DC Model

The MOSFET model required for circuit simulation consists of two parts: (a) a steady-state or DC model, where the voltages applied at the terminals of the device remain constant, that is they do not vary with time; (b) a dynamic

or AC model, where the device terminal voltages do not remain constant

but vary with time In this chapter we will discuss only DC MOS transistor models for different regions of device operation In the next chapter we will deal with the dynamic models

We will first develop a rigorous drain current model for long channel devices We then simplify the model and derive a first order model based

on various assumptions This first order simple model is important in itself because it could be used for hand calculations of the drain current in a MOSFET circuit This simple model will be improved upon as we remove some of the assumptions The long channel model is then extended to short- geometry devices This will be followed by studying the effect of temperature

on the drain current characteristics

6.1 Drain Current Calculations

Let us consider an n-channel device with uniformly doped substrate of

concentration N , (cm ~ 3), the structure and dimensions of which are shown

in Figure 6.1 For the sake of simplicity we will assume this to be a large geometry device so that the short-channel and narrow-width effects can

be neglected The static and dynamic characteristics of a device under the influence of external fields in general can be described by the following three sets of coupled differential equations:

1 The Poisson equation (2.41) for the electrostatic potential 4,

2 The current equation (2.35a) for electrons,

drift diffusion

(6.2a)

which is the sum of two terms, drift due to the field & and difusion due

to the concentration gradient Similarly, for holes, we have

where (P, and q p are the electron and hole quasi-Fermi potentials,

respectively The total current density J = J , + J ,

3 The continuity equations (2.38)

Fig 6.1 Schematic of a n-channel MOSFET (nMOST) showing voltages and reference

direction The x , y and z directions are the distances into the silicon, along the channel

and width of the device, respectively

232 6 MOSFET DC Model

are fairly complex; one could solve exactly only using numerical techniques,

as is done in 2-D device simulators such as MINIMOS [l], PISCES [a], etc However, in order to obtain approximate analytical solutions for use

in circuit simulators, we generally invoke assumptions that, though not rigorously true, do help to simplify these equations substantially

Assumption 1 Let us assume that the variation of the electric field 6, in

variation of the field €x in the x direction That is, the gradual channel

have developed threshold voltage models (cf section 5.1) As was pointed out in section 5.1, with this approximation the Poisson equation (6.1) becomes one-dimensional, that is we need only to solve

Using 2-D numerical analysis, it can be verified that the GCA is valid for most of the channel length However, it does fail near the drain region, where the longitudinal field 8, is comparable to the transverse field &x even

for long channel devices In spite of its failure near the drain end, the GCA

is used as it reduces the system to a 1-D current flow problem The fact that we have to solve only a 1-D Poisson's equation means that the charge expressions developed in chapter 4 for an MOS capacitor could be used for

a MOS transistor, with the modification that charge and potential will now

be position dependent in the y direction

operation of the n-channel device, V,, 2 0 and V,, 5 0 It should be pointed out that holes do become important in describing the device behavior in the avalanche or breakdown region, where impact ionization can create electrons and holes Since the current equation we are going to derive will not include breakdown regions, the drain current model needs to consider

and if one considers only the static characteristics of the device, as is presently the case, then the continuity equation (6.4) reduces to

This means that the drain current density is an electron current of vanishing

' Electrons are neglected for pMOST so that the current flow is assumed due to holes only, therefore, we need to consider only the hole current density J,

divergence, that is the total drain current Id, is constant at any point along

the channel

dx = 0, that is, q, is constant in the x direction Such assumptions have

been used even in 2-D simulators and the results are very satisfactory 131

Thus, the current density J, [cf Eq (6.3)], which consists of both drift and diffusion components, is given by

Since the cross-sectional area of the channel in which the current flows is

the channel width W times the channel depth, integrating the above

equation across the channel depth (x direction) and width ( z direction)

gives the drain current Id, at any point y in the channel as:

Zds(y) = - W l : [ qn(x, y)p,(x,

It is important to note that p , in the above equation is the electron surface channel mobility (for nMOST), often referred to as the surface mobility p ,

in order to distinguish it from the bulk mobility, the mobility far away from

the surface that was discussed in section 2.5.1 The value of ps for electrons

is in the range 400-700cm2/V.s, while for holes it is in the range 100- 300cm2/V.s, and depends on both the gate and drain fields as discussed

in section 6.6 Since the electron to hole mobility ratio is 2 to 3, this results

in nMOST's being faster (higher current) than pMOST's In the rest of the discussion we will replace p , by ps to emphasize that the mobility we are dealing with is the surface mobility

In a MOSFET, the application of source and drain voltages relative to the substrate results in lowering of the quasi-Fermi level Fn (or potential

q,) at the source end by an amount qV,b, and at the drain end by an amount q(Vd,+ VSb), relative to the Fermi level E , in the substrate (see

Figure 5.1) It is the difference in qn between the source and drain that drives the electrons down the channel If we define Vcb(y) as the channel potential at any pointy in the channel [cf Eq (5.2)], then (see Figure 6.2)

Eq (4.33b), i.e., p = N,e-@(y)i"t

Using Eq (6.9), the I,, Eq (6.8) can be written as

(6.1 1)

Assumption 5 Although ls depends on both 6TX and &y, as we will see later

in section 6.6, for now we will assume that p3 is constant, taken at some

average gate and drain field With this assumption ps can be taken outside

the integral in Eq (6.11) If we define Qi as the mobile charge density, that

is,'

(6.12)

All the charges discussed in this Chapter are charge per unit area, as was the case with the MOS capacitor, and are represented by Q with appropriate lower case subscript For example, gate charge density will be represented by Q,(C/cm2)

then Eq (6.1 1) becomes

Assuming the GCA is valid along the whole length of the channel, then

integrating Eq (6.13) along the length of the channel ( y direction) we get

(6.14)

Thus, to calculate the current Ids, we need to calculate the mobile charge

density Q i Different current models have been developed depending upon

different estimations for Qi(y) We will now discuss these models

6.2 Pao-Sah Model

In this model Q i ( y ) is calculated numerically by integrating the electron

concentration in the x direction Equation (6.12) can be rewritten as

where 4s is the surface potential (4 = 4s at x = 0) and is position dependent due to the voltage applied between the source and drain terminals Note the lower limit of integration is 4 This is because electron charge comes mostly from the area where electron concentration exceeds the hole concentration, the inversion layer therefore ends at a point where 4 = 4,-

In the equation above &x is the field in the x direction and is obtained by

solving the Poisson equation (6.5) In analogy with an MOS capacitor [cf

Eq (4.47)], the Poisson equation for a MOSFET can be written as

The only difference between Eq (6.16) and the corresponding Eq (4.47)

for the MOS capacitor is the presence of the potential Vcb(y) in the exponent

and the position dependence of 4 ( y ) in the y direction [cf Eq (6.10)]

Integrating Eq (6.16) in the x direction, and following the same procedure

as was used in solving Eq (4.47), we get the field €x in silicon for the case

of a MOSFET as

(6.17)