MOSFET MODELING FOR VLSI SIMULATION - Theory and Practice Episode 5 ppsx

The band bending potential 4 x must satisfy Poisson’s equation 2.41 and is used to calculate the induced charge Q, within the space charge region of width X , at the surface, also call

ACCUMULATION

METAL

OXIDE

HOLE DENSITY

Fig 4.10 Effect of applied voltage on a p-type MOS capacitor; (a) negative voltage

V,, = (V, -_ yfb) causes hole accumulation at the surface; (b) positive voltage depletes holes

from the silicon surface; and (c) a large positive V,, causes inversion, forming an n-type

layer at the silicon surface

charged acceptor ions In other words, a positive charge on the gate induces

a negative charge Q , at the silicon surface Since holes are depleted at the

surface it is referred to as the depletion condition This is analogous to the depletion region in p n junctions discussed in section 2.5 Since hole

concentration decreases at the surface, we see from Eq (4.15) that (Ei - Ef)

4.2 MOS Capacitor at Non-Zero Bias 137

must decrease resulting in Ei coming closer to E , thereby bending the

bands downward near the surface (Figure 4.10b) Thus in

Let us now calculate the depletion layer charge The band bending potential

4 ( x ) must satisfy Poisson’s equation (2.41) and is used to calculate the induced charge Q, within the space charge region of width X , at the surface, also called the depletion width We refer to this induced charge in the depletion region as the bulk charge denoted by Qb Applying Gauss’ law

we have [cf Eq (4.18)]

Under the depletion approximation (cf section 2.5.2) n = p = 0 (no free carriers) and the assumption that the substrate is p-type (uniform concentra- tion N, cm- ’) so that No( = Nb) >> N,, the Poisson equation (2.41) becomes

I Q, < O

(4.24)

Integrating the above equation twice from the interface (x = 0) to the

depletion edge ( x = X , ) and using the boundary conditions

Note that the depletion width given by the equation above is the same as

that obtained for one sided step pn junction under the depletion approxima- tion [cf Eq (2.53)] This shows that we can treat the silicon surface/silicon

bulk system as a one sided step junction

The depletion or bulk charge Qb can now be obtained from Eq (4.23) using

Eqs (4.26) and (4.27) giving

where we have made use of Eq (4.27) for X, For n-type silicon, Qb, given by

Eq (4.29), is a positive quantity

Note that Eq (4.27) for X , is in terms of surface potential $s Since $s itself

is a function of gate voltage V, [cf Eq (4.20)], one can also write X , in

terms of V, Thus, by substituting $s from Eq (4.27) and Qs( = Q b ) from

Eq (4.29) in Eq (4.20) and solving the resulting quadratic equation in X ,

we get, under the depletion approximation

doping but instead by inversion of the original p-type substrate due to the applied gate voltage This is referred to as the inversion condition and is

4.2 MOS Capacitor at Non-Zero Bias 139

shown in Figure 4.10~ Thus in

Vg >> V f b j

The surface is inverted as soon as E , > E j This is called the weak inversion

considerably above Ei If we further increase Vg,, the concentration of

electrons at the surface will equal, and then exceed, the concentration of the holes in the substrate This is called the strong inversion regime One may ask, where these electrons (minority carriers) in the p-substrate come from when inversion sets in Physically speaking these electrons come from the electron-hole generation, within the space charge (depletion) region, caused by the thermal vibration of lattice phonons The rate of thermal generation depends upon the minority carrier life time zo which

is typically in p e c (lO-%ec) This means that minority carriers are not immediately available when an inverting gate voltage is applied The time

tin" required to form an inversion layer at the surface is approximated by

for the holes (majority carriers) topow from or to the silicon surface which

is of the order of picoseconds (i.e the dielectric relaxation time associated with the substrate.)

The inversion layer is important from the MOS transistor operation point

of view It is the nature of the inversion layer, that is, number of carriers

in the inversion layer (i.e inversion layer charge Qi), the mobility of

the carriers in the layer etc which determines the current in the transistor The inversion layer charge Qi can be calculated by including the electron concentration n in Poisson's equation (4.24) Let us first calculate n Rewriting Eq (4.4) as ni = N , e - 4 f l v t and substituting ni in Eq (2.10) we get

and

At the surface 4 = 4s and therefore, from Eq (4.33a), the electron concen-

tration n, at the surface is given by

(4.34) When 4, = 4f, i.e E i = E,, we see that n, = ni That is, the silicon becomes intrinsic ‘When 4s > g 5 f , we have E , > Ei and the surface is inverted At the onset of weak inversion the surface potential 4, is slightly larger than

4f and in this case the depletion width is given by Eq (4.27) As we further

increase 4, by increasing the gate voltage V,, the depletion width X , widens

and the electron concentration n, at the surface increases (see Eq 4.34) When the gate voltage is such that 4,=24,, n,= N , , i.e., the electron

concentration at the surface becomes equal t o the hole concentration in the bulk When this happens the surface is said to be strongly inverted, and

under this condition, the depletion width reaches its maximum value Xdn,,

which can be obtained by replacing $s = 24, in Eq (4.27) Thus,

n s= N be(4”-24f)/vt

(4.35)

The condition 4, = 24, is often referred to as the classical condition f o r strong inversion When 4, > 24,, the depletion width increases but very slowly This is because the inversion charge immediately adjacent to the oxide-silicon interface shields the interior (bulk) of the semiconductor from any additional charge on the gate

4.2 MOS Capacitor at Non-Zero Bias 141

The thickness of the inversion layer has been calculated using both quantum mechanical and classical approaches These calculation show [ 15,161 that theo average “inversion layer thickness” at room temperature is about

50 A, depending on the substrate doping concentration and gate voltage Although not important from a circuit modeling point of view, it is interesting to consider the differences in the charge distributions calculated using the two approaches The differences are, as shown in Figure 4.11, in two aspects

In the classical case, the electron density has its maximum value at the oxide-silicon interface, and it decreases steadily as we move from the surface into the bulk In the quantum mechanical case, the electron density is zero at the interface, increases to its maximum value, and then decreases with the distance from the surface

In the classical case, the electron distribution is independent of the crystal orientation while it depends on the crystal orientation in the quantum mechanical case

Figure 4.1 1 also shows that most of the electrons are confined in a layer 50 A

thick For this reason, the motion of the electrons in the channel of a

length are not very small (cf section 3.7.7)

We will now return to calculate the inversion layer charge density Qi

Including the electron concentration n from Eq (4.33) in Poisson’s equation

(4.24) yields

(4.36) Integrating once under the boundary conditions (4.25) we get7

’ Multiplying both sides of the Poisson’s equation by Z(d+/dx) and using the identity,

Eq (4.36) becomes

which can easily be integrated to give (4.37)

Using Gauss’ theorem, we get the induced charge density Q, in the silicon

of the inversion charge Qi and depletion charge Q b , that is

Fig 4.12 Variation of inversion layer charge density Q i [Eq (4.41)], bulk charge density Qh

[Eq (4.29)], and the total semiconductor charge density Q,( = Qb + Qi) [Eq (4.39)] versus surface potential ds in all regimes of device operation for a p-type substrate, N , = 5.1015 cm- ’,

to, = 300 A, and V,, = 0 V

4.2 MOS Capacitor at Non-Zero Bias 143

Using Eq (4.29) for Qb and Eq (4.39) for Q,, we get the inversion charge

as a function of 4s These regions are (a) weak inversion and (b) strong inversion Classically, the condition 4, = 24, separates the region between the weak and strong inversion Often, however, the inversion regime is divided into three regions; the third region which lies between the weak and strong inversion is called moderate inversion, defined as the region

between 24, and 24, + 6Vt (see Figure 4.13b) In this scheme the region beyond 24, + 67/, is the strong inversion region [IS]

Weak Inversion Weak inversion sets in when the surface band bending is

4, and it extends to 24r (see Fig 4.13) Within this region, the inversion- layer charge Q i is small compared to the depletion-layer charge Qb, that is

For a small 4s, Eq (4.41) could be simplified* by assuming that the exponential term is small compared to 4s, resulting in the following expression for Q i

E E N

Vte(bs- 2bf)/ “t (weak-inversion) (C/cm2)

(4.43) Thus, in the weak inversion regime Q i is essentially an exponential function

of the surface potential 4, This is plotted as a dashed line in Figure 4.13a

Strong Inversion Strong inversion is defined by the condition that the

inversion layer charge Q i is large compared to the depletion region charge

Q b , i.e

1 Q i I > I Q, I (strong-inversion) (4.44) Here the exponential term in Eq (4.41) is large compared to 4s and thus

Q i in strong inversion becomes

The inversion layer charge is an exponential function of the surface potential with a slope of 1/2V1 (on a log scale) Therefore, a small increment of the surface potential induces a large change in the inversion layer charge

Using Eq (4.39) for Q, in Eq (4.20) we get a relationship between the gate voltage and surface potential as

This is an implicit relation in +s and must be solved numerically (see Appendix E) The result of such simulations are shown in Figure 4.14 At

low gate voltage ( > V,.,) 4s increases reasonably rapidly with gate bias and

so does the depletion width X , under the gate This regime corresponds

to the depletion and weak inversion regions of the device operation At larger gate biases, $s hardly changes; 4s has become pinned The classical condition for the pinning is + , = 2 4 , This pinning occurs when strong inversion sets in The condition when this happens is often called the condition for threshold and the corresponding gate voltage is called thre-

shold voltage Vth It is one of the important device parameter which will

be discussed in more details in Chapter 5

Using the Binomial theorem

terms we have f i = 1 + x/2

= 1 + x/2 - x2/8 + and retaining the first two

4.2 MOS Capacitor at Non-Zero Bias 145

N , = 1.0 x l O I 6 cm- ', to, = 300 A, V,, = OV Cross indicates dS = 24, point which separate

weak and strong inversion region

To summarize, we have calculated separate expressions for the induced charge Q , that are valid in the depletion [ Q b , Eq (4.29)] and inversion [ Q i ,

Eq (4.41)] regime of MOS capacitor operation However, one can easily derive a general expression for Q, that is valid for all the regimes of device operation by including both the holes and electrons and thus solving the Poisson Eq (2.41) Using Eqs (4.33) for n and p and noting that in the

bulk charge neutrality dictates that N , - N , = npo - ppo, npo and p p o being

the carrier density in the bulk ( p p o % Nb and npo z Nbe-2'fiVt), the Poisson

Eq (2.41) becomes

d x 2 E~E,(

d2Q, - qNb [I + , ( + - 2 + f ) / V r - e-4ivt - e-26fivtl for 0 1 x 5 x,

(4.47) Integrating the above equation, under the boundary condition (4.25), results

in the following expression for Q, which includes both holes and electrons

1613 c121,

+ Vre-@J"t - ~ ~ 1 ' ' ~ (C/cm2) (4.48) The charge expression (4.48) is valid in all the regions of MOS capacitor operation-accumulation, depletion, and inversion It should be pointed out that in the literature Eq (4.48) is also written in terms of npo and p p o

INVERSION ACCUMULATION

'DEPLETION

-9

'-0:2 O' : 012 ' 0:4 ' d.6 ' Ol8 IlO SURFACE POTENTIAL, pSC V >

Fig 4.15 Variation of the induced charge density Q, in silicon versus surface potential q5s

for p-type substrate in all regimes of device operation obtained using Eq (4.48)

N , = 5 x 10'5cm-3, to, = 300A and V f b = OV

where L, is the Debye length defined as

When 4s < 0, the MOS structure is in the accumulation mode The term

that predominates in Eq (4.48) is e-4s/vt and therefore in this regime

Q, varies as

Q, - ec4s/2vt (accumulation) (4.5 1 a)

4.3 Capacitance of MOS Structures 147

Table 4.2 Definition of silicon surface parameters

- +

Eq (4.48) is 6 and therefore Q, varies as

b When 4s > 24 f , the structure is in the strong inversion mode The

Note that the accumulation, depletion and inversion conditions described

by Eqs (4.21), (4.22), and (4.31) are for p-type substrates However, for

n-type substrates these conditions will be reversed as shown in Table 4.2

predominant term in Q, varies as

4.3 Capacitance of MOS Structures

In the previous section we developed relationships between the charge and

potential under different gate voltage conditions across a MOS capacitor

Now we will see how the capacitance of the MOS system varies with the applied voltage The capacitance of any system is the ratio of the variation

in charge to the corresponding variation in the small-signal applied voltage

Thus the capacitance C , of a MOS structure is

Substituting the value of V,, from E q (4.19) in Eq (4.16) we get

The quantity - dQs/d4, can be interpreted as the capacitance per unit area,

C , associated with the silicon depletion or space charge region, i.e

Similarly, the capacitance per unit area C , associated with the interface

charge density Qo can be defined as

4.3 Capacitance of MOS Structures 149

Fig 4.16 Equivalent circuit of an MOS capacitor R , is the resistance associated with the

interface charge capacitance C o

resistance associated with the interface charge capacitance C, and is in parallel with the silicon capacitance C, The fixed positive interface charge density Q, is independent of the surface potential and if it is assumed that

no voltage dependent trapping mechanisms are occurring at the Si-SiO, interface, then C, will be zero and C, will be given by

1

(4.61)

Combining Eqs (4.20), (4.57), and (4.61) gives a complete description of an

MOS capacitor as a function of gate voltage Vg Thus, to calculate the MOS

Capacitance-Voltage (C-V) curve we first choose a set of 4, values com- patible with the silicon band gap For each value of 4, we in turn

0 calculate C,, the space charge region capacitance, using Eq (4.57),

0 calculate C,, the total MOS structure capacitance, using Eq (4.61),

0 calculate Q,, the charge contained in the silicon space charge region,

0 finally determine the gate voltage V , using Eq (4.20) for a given value

For each value of 4, chosen we can draw one point of coordinate (V,, CJ

The set of chosen 4, values allows us to plot the C,-V, curve point by point

Note that if we assume Vf!=0, the resulting C-V curve is called ideal

C-V curve and is shown in Figure4.17 Depending upon the applied

voltage, the MOS capacitor will either be in accumulation, depletion or

inversion Let us now consider these cases

using Eq (4.49),

of Vfb

accumulation there are excess carriers (majority holes) at the surface In

this case, the applied voltage V, < Iffb and the surface potential 4s is

GATE VOLTAGE,Vg Fig 4.17 Capacitance-voltage (C-V) curve of a MOS capacitor under (A) accumulation, (B) depletion, and (C)-(E) inversion Curve (C) is at low frequency and (D) at high frequency

(After Sze [4], slightly modified.)

negative Recall from Eq (4.51a), Q, and hence C, in accumulation is proportional to e-$s'"t, which means that for negative +s, C, becomes very large Therefore, as can be seen from Eq (4.61), the total MOS capacitance

C, is approximately Cox Thus, in accumulation

This is plotted as curve A in Figure 4.17

Depletion As the negative voltage is reduced sufficiently so that V, > Vsp,

a depletion region of width X , is formed near the silicon surface This

depletion width acts as a dielectric in series with the oxide Consequently

the silicon capacitance C , decreases and according to Eq (4.61) the total

capacitance decreases resulting in the following expression for the capaci-

4.3 Capacitance of MOS Structures 151

tance in depletion

where C, is the capacitance per unit area associated with the depletion region at the surface General expression for C, is given by Eq (4.57) However, a much simpler expression for C, can be obtained using the

depletion approximation As was mentioned earlier, the silicon-surface/

silicon-bulk system may be approximated by a one sided step junction in

depletion or inversion Therefore, from Eq (2.70) we have

Eq (4.64) we get space-charge capacitance c , , d in depletion mode as

so that the gate capacitance C, in depletion becomes

(4.65)

(4.66)

This is plotted as curve B in Figure 4.17 The MOS capacitor follows this

curve until inversion sets in From Eq (4.66) it is clear that for a given

voltage V, - V f b , the capacitance in the depletion region will be higher f o r

higher N b and/or low Cox (larger tax) Further, note that at V, = v f b (flat band condition, 6 = 0), we have C, = Cox However, in a real MOS capacitor

at the flat band, C , is less than Cox (see Fig 4.17) This is because the transition between the accumulation and depletion regions is not abrupt

as is assumed in the depletion approximation on which Eq (4.66) is based

To solve for the MOS capacitance at flat band, called thepat band capaci-

tance C f b , we need to use Eq (4.48) for Q , or Eq (4.57) for C, For 4 < 0

we have e - + s >> e C 2 + f > e - 2 + f + 6 s and therefore, E q (4.48) can be approxi- mated as

(4.67)

which on differentiation gives’

Inversion If the gate voltage ( V , - V,,) is sufficiently positive such that

4, > df, an inversion layer is formed at the surface of the silicon Recall that this inversion layer is formed from the generation of minority carriers (electrons in our example of a p-type substrate) The concentration of minority carriers can change only as fast as carriers can be generated within the depletion region near the surface This limitation causes the MOS

capacitance in inversion to be a function of frequency of the AC signal used to measure the capacitance If the AC signal frequency is sufficiently low (typically less than 10 Hz) so that the inversion charge carriers (minority carriers) are able to follow the AC bias voltage and the DC sweeping voltage, then the resulting C-V curve is know as a low-frequency (LF) C-V

plot.” However, if the AC bias signal frequency is too high (typically above

Using the expansion ex = 1 + x + x2/2 + x3/6 + x4/24 and retaining its first 5 terms we get from Eq (4.67), after some algebra,

which could further be simplified using Binomial expansion of

4.3 Capacitance of MOS Structures 153

lo5 Hz) so that the inversion charge carriers do not follow the AC voltage, the measured C-V curve is called the highfrequency (HF) C-V plot

It is worth noting here that the calculations leading to MOS capacitance

variation of 4s This means that Eq (4.57) is valid only for low frequency

C-V curve In order to derive a general expression for the high frequency capacitance we first evaluate the charge contained in the space-charge layer

by neglecting the contribution of minority carriers in Eq (4.48) We then determine the equivalent thickness of the depletion layer possessing the same integrated charge and then calculate the corresponding capacitance using Eq (4.64) [2, p 247, Pt I]

Note that in the accumulation and depletion mode the M O S capacitance

C , is independent of the frequency f o r all frequencies of practical interest

This is because in this region minority carriers are negligible and so do not contribute to the total charge, which is governed by majority carriers The latter have transport time of the order of picoseconds (see section 4.2.3) Thus, depending upon the frequency of the AC signal and measurement conditions, three types of C-V plots are generally obtained

4.3.1 Low Frequency C-V Plots

In this case the D C gate voltage and the AC signal voltage are changed very slowly so that the MOS capacitor always approaches equilibrium This means that the signal frequency is low enough so that the inversion layer carriers can follow it In this case the capacitance C, is just that associated with the charge storage on either side of the oxide Thus, in inversion at low frequency (LF)

Under these conditions a plot of measured capacitance versus gate voltage follows curve C in Figure 4.17 Starting from the value of C,, in accumula- tion, the capacitance decreases (as the depletion region is formed) and goes through the minimum and then increases moving back to Cox as the surface becomes strongly inverted Note that the increase in the capacitance depends upon the ability of the minority carriers to follow the AC signal

It can be shown that the space charge capacitance at low frequency C,,,,

The discussion above assumed that the MOS system was in a dark enclosure

so that no external source of minority carriers generation other than thermal generation was available However, if the surface is illuminated, the surface carrier generation rate will increase resulting in an increase in the low frequency capacitance

If the AC measuring signal frequency is so high that the inversion layer charge density Q i cannot follow the high frequency (HF) variation in the gate voltage, Q i can be assumed to be constant for a given DC bias Under this condition the depletion region charge density Q b and the width X , of

the depletion region will fluctuate around the quiescent value Qbmax and

X d m respectively In this case the capacitance of the depletion region is given by

The minimum of C,,,, can be obtained by differentiating Eq (4.57) with respect to &,

equating the resulting equation t o zero and then solving for cjs = &,,in The algebra

could be simplified if one writes Eq (4.57) in terms of normalized potentials U,( = $,/Vt)

and Us( = $JK) as

JZL, [cosh(U, - U,) + U,sinh(U,) - ~osh(U,)]'~"

C , = -

At U s = Usmin, dC,/d$, = 0 which gives Usmi" x 2 U , - In (4U, - 4) Substituting value

of U s = Usmin in C, gives Eq (4.71) It should be pointed out that a n approximate expression for C,,, (min) is given as [17]

&eOEsi

C,(Min, LF) x -

5L'i

4.3 Capacitance of MOS Structures 155 where we have made use of Eq (4.35) for Xdm Thus, the gate capacitance

in inversion at H F becomes

and is constant independent of bias because Xd, is constant This is shown

in Figure 4.17 as curve D Note that C, given by the above equation is

also Cmin at HF

Experimentally, at H F more rapid saturation of capacitance to its minimum

is observed than is predicted by the above equation This would be expected

if minority carrier redistribution is taken into account Since the inversion layer is not infinitesimally thin, a redistribution of the carriers within the inversion layer at the AC measurement frequency will cause capacitance

to saturate more abruptly As a further consequence, the saturation capaci-

tance will be larger than predicted by the above equation Several authors have taken into account the redistribution of minority carriers and have used a more accurate estimation of the space charge layer However, an excellent approximation for the asymptotic behavior of C,,,, at inversion is due to Berman and Kerr [18] which gives

(4.75) C,,,,(Min, HF) = J' €0 E s i q N b

2Vt(2U,- 1 +1n[1.15(UJ- l)])'

It should be reiterated that though the inversion layer of a MOS capacitor cannot follow the high frequency signal, this is not the case with MOS

transistors which are capable of operating at much higher frequencies This

is because the heavily doped source region of the MOS transistor will

always be in contact with the inversion layer and thus can supply the charge required to follow the high frequency gate signal

4.3.3 Deep Depletion C-V Plot

If a MOS capacitor is swept from the accumulation to the inversion region

at a relatively fast rate (about 10 V/s and higher) so that there is not enough

time for the thermal generation of the inversion charge carriers (minority carriers), the capacitance will continue to drop following the depletion curve This is a non-equilibrium situation in which the depletion width

widens (to balance the increased gate charge) past its maximum value X,,

and c d does not reach a minimum This is shown as curve E in Figure 4.17 This expansion of the depletion region deep in the silicon bulk is referred

to as deep depletion The capacitance in the deep depletion is given by

Eq (4.65) The deep depletion curve is obtained when the DC voltage

sweep rate is high, independent of the frequency of the AC signal voltage