Bài giảng điện tử môn tin học: Field Programmable Gate Arrays doc

Electronics in High Energy Physics Winter Term: Introduction to Electronics in HEP Field Programmable Gate Arrays... Programmable Logic• Programmable digital integrated circuit • Standar

Electronics in High Energy Physics

Winter Term: Introduction to Electronics in HEP

Field Programmable Gate Arrays

Part 2

– Introduction – Examples

• Design Flow

– Entry Methods – Simulation

– Synthesis – Place & Route

Programmable Logic

Programmable Logic

• Programmable digital integrated circuit

• Standard off-the-shelf parts

• Desired functionality is implemented by configuring

on-chip logic blocks and interconnections

• Advantages (compared to an ASIC):

– Low development costs

– Short development cycle

– Device can (usually) be reprogrammed

• Types of programmable logic:

– Complex PLDs (CPLD)

–

Architecture and Examples

PLD - Sum of Products

C B A C

B A

f1 = • • + • •

C B A B

A

f2 = • + • •

Programmable AND array followed by fixed fan-in OR gates

Programmable switch or fuse

CPLD Structure

Integration of several PLD blocks with a programmable interconnect on a single chip

PLD Block

PLD Block Block PLD

PLD Block

PLD Block Block PLD

PLD Block

Stefan Haas, 1 F

eb 2005

CPLD Example - Altera MAX7000

EPM7000 Series Block Diagram

CPLD Example - Altera MAX7000

EPM7000 Series Device Macrocell

FPGA Architecture

FPGA - Generic Structure

FPGA building blocks:

• Programmable logic blocks

Implement combinatorial and

sequential logic

• Programmable interconnect

Wires to connect inputs and

outputs to logic blocks

• Programmable I/O blocks

Special logic blocks at the

periphery of device for external

– DSP blocks:

• Hardware multipliers, adders and registers

– Embedded microprocessors/microcontrollers – High-speed serial transceivers

FPGA – Basic Logic Element

• LUT to implement combinatorial logic

• Register for sequential circuits

• Additional logic (not shown):

– Carry logic for arithmetic functions

– Expansion logic for functions requiring more than 4 inputs

LUT

Out Select

A B C D

Stefan Haas, 1 F

eb 2005

Look-Up Tables (LUT)

• Look-up table with N-inputs can be used to implement any

combinatorial function of N inputs

• LUT is programmed with the truth-table

LUT

A B C D

Z

A B

C D

Z

Truth-table Gate implementation

LUT implementation

X1 X2

X3

F

Configuration memory

cells

Stefan Haas, 1 F

eb 2005

Programmable Interconnect

• Interconnect hierarchy (not shown)

– Fast local interconnect

– Horizontal and vertical lines of various lengths

Matrix Switch Matrix

Switch Matrix Operation

• 6 pass transistors per switch

matrix interconnect point

• Pass transistors act as

programmable switches

• Pass transistor gates are driven

After Programming Before Programming

– Eliminate clock skew between external clock input

and on-chip clock

– Low-skew global clock distribution network

Configuration Storage Elements

• Static Random Access Memory (SRAM)

– each switch is a pass transistor controlled by the state of an SRAM bit

– FPGA needs to be configured at power-on

• Flash Erasable Programmable ROM (Flash)

– each switch is a floating-gate transistor that can be turned off by

injecting charge onto its gate FPGA itself holds the program

– reprogrammable, even in-circuit

• Fusible Links (“Antifuse”)

– Forms a forms a low resistance path when electrically programmed – one-time programmable in special programming machine

– radiation tolerant

Example: Altera Stratix Series

Floorplan

Stefan Haas, 1 F

eb 2005

Logic Element

Logic Array Block (LAB)

• LAB regroups 10 logic

elements with a fast

local interconnect

• Interconnect structure

– Direct link between LABs

and adjacent blocks

Example: Xilinx Virtex-II Pro

Logic Slice Architecture

• Two 4-input LUT, can also

be used as:

– 16-bit synchronous RAM

– 16-bit shift register

• Two flip-flops/latches

• Carry logic for arithmetic

circuits (e.g adder)

• Fast width expansion logic

– Implement logic functions with

more than 4 inputs

• Connections for carry

logic and shift register

mode

Xilinx: Embedded Multipliers

Stefan Haas, 1 F

eb 2005

Altera: Embedded DSP Blocks

Altera: Embedded DSP Block

Stefan Haas, 1 F

eb 2005

3.125 Gb/s per pair

32b @

Virtex-II Pro Virtex-II Pro

Xilinx: Rocket I/O

Virtex 4: 11.1 Gbps !!!

FPGA Vendors & Device Families

version for cost-critical applications

• QuickLogic

– ViaLink-based FPGAs

– Lower cost per function (LUT + register)

– Smaller and faster transistors: Higher speed

• System speed up to 500 MHz

– Mainly through smart interconnects, clock management, dedicated circuits, flexible I/O

– Integrated transceivers running at 10 Gigabits/sec

• More Logic and Better Features:

– >100,000 LUTs & flip-flops

– >200 embedded RAMs, and same number 18 x 18 multipliers

• 1156 pins (balls) with >800 GP I/O

– 50 I/O standards, incl LVDS with internal termination

• 16 low-skew global clock lines

– Multiple clock management circuits

• On-chip microprocessor(s) and multi-Gbps transceivers

Latest Devices: Capacity & Features

Electronics in High Energy Physics

Winter Term: Introduction to Electronics in HEP

Field Programmable Gate Arrays