Design, simulate and install 4-bit Ripple Carry Adder IC7483: 2.1 Design Diagram of 4-bit Ripple Carry Adder Schematic Design based on Full Adder circuit designed in question 1:... Desi
Trang 1FACULTY OF COMPUTER SCIENCE & ENGINEERING
TP.HCM
Laboratory Manual
Digital Systems Experiment Lab 4
Group
Ho Chi Minh, 11/2022
Trang 21 Design and simulate Full Adder circuit from Half Adder circuits
1.1 Logisim design:
Half Adder diagram:
Full Adder diagram:
t—E—]
C-OUT
z
Trang 3Truth table:
Input A
0
0
1.2 Logisim simulation:
Demo video link:
2 Design, simulate and install 4-bit Ripple Carry Adder IC7483:
2.1 Design
Diagram of 4-bit Ripple Carry Adder (Schematic Design) based on Full Adder circuit designed in question 1:
Trang 4A3 B3 A2 B2 A1 Bí AO; BO!
GS FulAdder | C2 Full Adder ΠFullAdder |, C0 Full Adder Gn
|
Fill in the truth table with given value (Given AO, BO, SO are LSB):
O A= =,B= =,withCin=0
O A= =,B= =,withCin=1
O A= =,B= =,withCin=1
O A= =,B= =,withCin=0
O A= =,B= =,withCin=1
O A= =,B= =,withCin=1
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2.2 Simulation
Designed IC 7483 circuit on Logisim:
1C7483 on Logisim demo video link:
Trang 623 Installation
IC 7483 circuit on DS Kit:
ne 3u|tlu|sltlsja[e,
IC 7483 circuit on DS Kit demo video link:
https://drive.google.com/file/d/11XIbPdtItESew DkHEomn|ZgHpcykry28/view ?usp=drivesdk
Trang 73 Design, simulate and install a MOD-10 Asynchronous Up Counter using D
FlipFlop or JK FlipFlop:
3.1 Design
Design the circuit under these demands:
O Step 1: Define the circuit: Asynchronous/Synchronous Counter | UP/DOWN Counter
O Step 2: Define the circuit: J-K FlipFlop / D FlipFlop / T FlipFlop
Positive / Negative Edge Trigger O_ Step 3: Define number of flipflops need to perform:
o Suppose nis the number of FlipFlops need to be done, thus we have - 1 number of possible states which FF could count
o Thus the number of demanded states O - 1
o Number of circuit’s state: 10
0 So the circuit has to have 4 FFs to work
O_ Step 4: Define State need to perform:
State table:
Trang 8
O_ Step 5: States’ modification:
0000, (initial) O 0001, 0 0010, O 001120 0100, 0 0101, 0 0110,0 0111.0
10001 1001;[1 0000;(initial)
O Step 6: Connection of output Q with initial value (CLEAR) — Draw the circuit diagram:
Circuit diagram
QA ——
QB ———
Q
Combinational Logic
MOD-10 Asynchronous Up Counter circuit diagram:
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3.2 Installation
Circuit image:
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Circuit’s function demo video link:
; Ndi | RIe/d/1GUO7d ibF7C0SjoY 5Bw _6jirsQeWit/view2
usp=drivesdk
3.3 Logisim simulation
Logisim circuit image:
10
Trang 11
Circuit’s function on Logisim demo link video:
4 Answer the question:
4.1 What is the difference between asynchronous and synchronous
counter?
triggered with same clock simultaneously
In asynchronous counter, different flip flops are triggered with different clock, not simultaneously
asynchronous counter in operation
synchronous counter in operation
11
Trang 12
Synchronous Counter does not produce
any decoding errors
Asynchronous Counter produces decoding
error
Synchronous Counter designing as well
implementation are complex due to
increasing the number of states
Asynchronous Counter designing as well
as implementation is very easy
Synchronous Counter will operate in any
desired count sequence
Asynchronous Counter will operate only in fixed count sequence (UP/DOWN)
Synchronous Counter examples are: Ring
counter, Johnson counter
Asynchronous Counter examples are: Ripple UP counter, Ripple DOWN counter
In synchronous counter, propagation delay
is less
In asynchronous counter, there is high propagation delay
Synchronous Counter is also called
Parallel Counter
Counter
4.2 What is the procedure to design a synchronous counter?
1 Find the number of flip flops using 2n>=N, where N is the number of states and n is the number of flip flops
2 Choose the type of flip flop
3 Draw the state diagram of the counter
4 Draw the excitation table of the selected flip flop and determine the excitation table for the counter
5 Use K-map to derive the flip flop input functions
12
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