Lab 3 digital systems group

How many minimum D Flip-flops are required to build a circuit in which the output frequency is 16 times less than the Clock In frequency?.b. Answer Question a: Circuit Phenomenon The cir

p VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY

TP.HCM

LAB 3

DIGITAL SYSTEMS

GROUP:

INSTRUCTOR: NGUYEN THANH Loc

K2024- 241

Google drive link (Examination of Circuit Operations):

REFERENCES

Exercise 2.3

EXERCISE 2.3

e Exercise 2.3.1: Design, simulate and implement a D Flip-flop using J-K Flip-flops (allowed to use other logic gates if necessary)

SOLUTION

|¬ | 4

1 2 {3 |¢ 5 6 |?

CLK1 CLR1 K1 Voc CLK2 CLR2 J2

Figure 5: IC 7473 Connection

5404/7404

Hex inverter

[us] fis] fie] fu] fio] fo} fe]

b Design

1.DFlip-Flop

1|1|1 |XỊ0

3 K-map for J-K Flip-Flop

D/Q|O} 1

D/Q|0|1

0 X|1|=>K=PD'

c Logic design

473

7404

e Set-up list

ORDER NUMBER FIRST HEAD OTHER HEAD

5V

GND

8 CLK pin 1 (7473)

f Truth table

J | KJ] CLK] CLR} Q’|]Q

110 1 0 |1

0|1 1 1 |0

g Video: 2.3.1

e _ Đxercise 2.3.2: Design, simulate and implement the following logic circuit Observe the operation

of circuits and answer the following questions

1L CLK > CLK > CLK

DFF1 QL DFF2 QL DFF3 Q

a Assume that QA, QB, QC are connected to the LEDs What is the phenomenon of LEDs? What is the

difference among LEDs?

b How many minimum D Flip-flops are required to build a circuit in which the output frequency is 16 times less than the Clock In frequency?

difference among LEDs?

a CHOOSE ICs: IC 7474 (D Flip-flops)

Pin Assignments for DIP, SOIC, SOP and TSSOP

Figure 3: IC 7474 Connection

b Logic design

QA

uw

c Logisim design

QA

QB

d Set-up list

ORDER NUMBER FIRST HEAD OTHER HEAD

5V

GND

SW1 (CLR)

12 pin 5 (7474A) pin 11 (7474A)

13 pin 9 (7474A) pin 3 (7474B)

14 pin 2 (7474A)

LEDO

LED1

17 pin 12 (7474A)

LED2

CL | QA] QB} QC

K

0 |0 |0

1 |0 |0

0 |1 |0

1 |1 |0

0 |0 |1

1 |0 |1

0 |1 |1

1 |1 |T1

f Video: 2.3.2-a 2.3.2-b

f Answer

Question a: Circuit Phenomenon

The circuit implements a frequency divider using a series of D Flip-Flops (DFFs)

1 First D Flip-Flop (DFF1):

o QAis connected to D and Q' of DFF1

o This setup creates a toggle flip-flop With each clock pulse, QA toggles its state (from 0

to 1 or from 1 to 0)

o QAoutputs a clock signal at half the frequency of the input clock signal

2 Second D Flip-Flop (DFF2):

© The Q output of DFF1 is connected to the CLK input of DFF2, so DFF2 receives a clock signal that is half the frequency of the original clock

o DFF2 will similarly toggle QB each time it receives a clock pulse from DFF1, resulting in

QB toggling at one-quarter of the original clock frequency

signal that is one-fourth the frequency of the original clock

o DFF3 will toggle QC at one-eighth the frequency of the original clock

Since QA, QB, and QC are connected to LEDs, each LED will blink at a different frequency:

¢ §QA blinks at half the input clock frequency

¢ = QB blinks at one-fourth the input clock frequency

¢ QC blinks at one-eighth the input clock frequency

The difference among the LEDs is that they blink at progressively half frequencies

Question b: Minimum D Flip-Flops for 1/16 Frequency Output

To divide the clock frequency by 16, use a circuit that produces an output toggling at 1/16 of the original clock frequency Each D Flip-Flop divides the frequency by 2 (explained in question A), so the number of DFFs needed can be calculated as follows:

2"= 1ó =>n=4

4D Flip-Flops are required to create an output frequency that is 16 times less than the input clock frequency