Nearly every block in an OpAmp contains at least one current source.
The important parameters of a current source are the following:
- output resistance (or variation of the current in the output voltage range);
- output capacitance;
- saturation voltage (or how close the output voltage can swing to the supply rail);
- power supply rejection (or variation of the current in the power supply range)
- noise.
Usually most of the current sources are obtained by mirroring from the primary biasing core units (considered above). Using the cascoded current mirrors provides increased output resistance.
In bipolar circuits no current sources should be mirrored from the same core if one of them can enter in saturation, even briefly (for example, on start-up). Existing models are not sufficient for adequate simulation of saturated bipolar transistor, and the simulation results may be different from the silicon operation if saturation is not prevented.
The practical gate bias voltage sources always have some source impedance especially noticeable at high frequencies. Every transistor has a parasitic capacitance between its gate and drain. These two factors may cause high-frequency signal leakage between the loads of different current sources mirrored from the same origin. To avoid this, a good practice is to add a bypass capacitor across the cascode gate bias voltage source (C0 in fig.
3-11).
Figure 3-11. Set of cascoded current sources
The gate bias voltage source for cascode transistors can be created using the current Icsc and a diode-connected Mcsc (fig. 3-11) For low voltage
designs, and for better control over temperature of the drain-source voltages of mirror transistors Morg-Mxi, a more complicated cell [31], as shown in fig.
2-6b, may be recommended.
To minimize noise, the transconductances of mirror transistors (Morg, Mxi
in fig. 3-11) must be small [108]. This results in longer channel devices operating in strong inversion, and having larger parasitic capacitances. At the same time, the current source should introduce as little of parasitic capacitance as possible in the unit where it is used. The cascoding transistors (M0-Mn in fig. 3-11) isolate large parasitic capacitances of the mirror transistors from the load. Transistors M0-Mn should be as small as possible to decrease their parasitics (i.e., they should be of minimal allowed length and minimum possible, for a given current and chosen Vgs width).
Impact ionization leakage current between the drain and body of CMOS transistors becomes noticeable even with a relatively small (1 V) drain- source voltage (see fig. 1-7). Such drain-body leakage decreases the output impedance and accuracy of the current source. This effect can be especially damaging in 2-stage amplifiers with an open-loop gain defined as the product of a transconductance and equivalent impedance at the current summing node. To eliminate this effect, it is desirable to connect the body of cascode transistors to their sources; in this case the total output current of the source will still be equal to the drain current of the mirror transistor.
The body to source connection is not possible for single-well processes where the bodies of all NMOS transistors are inherently connected to the substrate (or of all PMOS for the process with N-type substrate). Two structural design solutions (applying dedicated feedback) for this problem are shown in fig. 3-12.
Figure 3-12. Decrease of the impact ionization leakage effects in the current source.
In fig. 3-12a [35], in order to reduce the drain voltage of M1 and simultaneously to preserve the high output impedance we organize a local
feedback loop including M3 and amplifier A1. The current of M3 is compared with the drain current of M1, and the high loop gain provides equality of these two currents. At the same time, due to the fact that the second input point of A1 is at the gate of M1, the drain-source voltage of M1 will be equal to its gate-source voltage. This minimizes impact ionization in M1. The PMOS transistor M3 has its body connected to the source and impact ionization effects in this transistor do not change Iout.
The circuit of fig. 3-12b utilizes compensation of the leakage by a current derived from the leakage measurements in the reference transistor. It is the feedback loop that detects the amount of the leakage current and then subtracts it from the initial current source. The leakage detection feedback loop consists of the current source M1i/M0iwhich matches M1/M0, transistor M2 which keeps the drain voltage of M1iapproximately equal to the drain voltage of M1 (with Vgs difference), the reference current Iorgi which matches the original current Iorg (and the desirable current Iout of the source) and the current mirror M4/M5/M6. M4 and M5 are matched, but M4 and M6 have a large ratio of their aspect ratios so there is a considerable gain in the M2-M6- M4 feedback loop. As a result, the current of M4 is close to the drain-body leakage of M1i and the matching current of M5 is providing necessary compensation for the leakage in the current Iout of transistor M1.
Another factor decreasing the output impedance of the cascoded current source is the finite output impedance of both transistors. The internal feedback loop existing in these sources may have not sufficient gain to provide the high output impedance. This effect can be somewhat diminished by increasing the channel length of both mirroring and cascoding transistors, but, as has been mentioned, the cascoding transistor needs to be as short and as small as possible to decrease the parasitic drain capacitance. In this case an additional local feedback loop can be a solution.
In this respect the circuit of fig. 3-12a is also one of the ways to apply feedback in order to improve the output impedance of the current source.
Two more ways to apply the local feedback and improve the current source output impedance are shown in fig. 3-13. The circuit of fig. 3-13a was developed for the OpAmp gain boosting [38] but it can be used to increase the current source output impedance as well. The feedback loop A1- M1 keeps the drain voltage (and, consequently, ID) of M0 constant and equal toVds (this voltage is set by V0andM2) regardless of VIout variation, as long asVIout is below VDD−Vds.
The circuit of fig. 3-13b comprises the feedback loop A2-M5. It keeps the Vds voltages of M4 and M5 equal. It ensures that the drain currents of M4 and M5 are equal as long as there is gain in the feedback loop and Vds of M4/M5 is larger than the offset voltage of A2.
A regular cascoded mirror source also has a significant trioding voltage (250-400 mV). When the drain voltage decreases below this level the output
impedance sharply drops. Trying to use a long channel device to increase the output impedance increases this voltage and reduces the available swing headroom. The minimal output voltage of the current source shown in fig. 3- 12a should not be less than VgsM3. In this respect the circuits shown in fig. 3- 13 are improving the output impedance without using long-cannel devices and at the same time decrease the minimum output voltage.
Fig. 3-14 shows how the circuit of fig. 3-13b can be implemented in 0.6u CMOS process. The implemented circuit uses the current-input amplifier.
The output current versus voltage characteristic of this circuit may be compared with the characteristic of a regular cascoded current source, both designed for the same Iout = 10 uA, V1=1.3 V. Using the feedback loop improves the current source output resistance in about 50 times and decreases the trioding voltage from 350 mV to 60 mV. Both parameters can be improved further by increasing the gain of the amplifier M7/M8.
Figure 3-13. Improvement of the current source output impedance
Figure 3-14. Output currents of the regular and improved current sources versus voltage
The current source of fig. 3-14 can be used as a tail current source of the OpAmp input stage. It provides a wider common-mode voltage range and improves CMRR (chapter 5) in comparison with using an ordinary cascode current source.
Another structural design solution for the tail current source is shown in fig. 3-15. Here the feedback loop comprises the sensors (transistors M0aand M1a) that are matching M0/M1of the OpAmp input stage. The gain booster A1
andM2, M3are providing the required loop gain.
The feedback loop sets ID0a+ID1a =I0(R0−R1)/R1 (it is assumed that I0 = I0a). The loop does not need compensation in CMOS implementation but with bipolar components a compensating capacitor in parallel with I0a
may be required.
Figure 3-15. Tail current source for the OpAmp input stage
The circuits of fig. 3-12 to 3-15 illustrate the main principle of the structural design: when parameter is important for the circuit operation it should be controlled by a dedicated feedback loop. Then this parameter will be defined by the quality of the parameter sensor and by the gain in the loop.