Voltage gain boost is the generalization of the cascode approach to increase the output impedance of transistor. In terms of the structural design, it is the use of active feedback loop to reduce the influence of parasitic feedbacks which are affecting voltage or current gain in the amplification stage. The block diagram of a popular voltage gain boost circuit [38], and its signal flow graph are shown in fig. 4-7.
Figure 4-7. Voltage gain boost
The sequence of horizontal branches in this graph represents the transmission of the input signal to the output in the cascode connection of M0
and M1. To boost the output impedance of M1, it is placed in the negative feedback loop in conjunction with amplifier A. If A is very high, then any AC finite value signal appearing after the amplifier requires that the AC signal at the amplifier input is nearly zero (we will write, for simplicity, simply zero). This requires that the AC component of Vd0be zero, and that the AC component of Id0 also be zero. Hence, the AC signal Id1
isId1 =gm0Vin, and the AC component of Vout is Vout = gm0ZeqvVin. The voltage gain is gm0Zeqv. Here Zeqv is the equivalent impedance at the node out, and it consists of the parallel connection of load, RL, inner impedance of the current source I0, and drain impedance of M1. If the load is the gate of the next amplification stage, and the current source is designed as suggested in chapter 3, and has very high inner impedance, then Zeqv is dominated by the drain impedance of M1.
Transistor M0 has a parasitic feedback link γ0. Yet, because the AC component of Vd0 is zero, this link is not operable. Transistor M1 also has an
internal feedback γ1 (finite output impedance, short-channel effects, etc.) that affects its Vgs1 as the drain voltage changes. Again, as Vd0 is zero, this parasitic link is suppressed, and Vgs1 =Id1/gm1 as long as A(s) is high.
Fig. 4-7c shows the gain/frequency response of the stage without and with the gain boost. The last dependence has a smooth -20dB/dec slope. No doublets are present as long as the load capacitance is larger than the sum of the parasitic capacitances of M1 and I0. The circuit not only improves DC and low-frequency gain (by the value of A), but also the high-frequency gain of the stage: the gain in the A-M1 loop decreases the voltage Vd0, and, hence, the impedance seen at the source of M1. This impedance is the load for M0, and a smaller load means a smaller time constant of M0 associated with Cgd
(suppressed Miller effect).
Figure 4-8. Implementations of the voltage gain boost
Some implementations of the circuit of 4-7a are shown in fig. 4-8. The circuit of fig 4-8a is the simplest one, with the amplifier A implemented by a single transistor M2. The minimum output voltage for this circuit is equal to (Vgs+Vsat).
The circuit of fig. 4-8b employs the current-input amplifier M2/M3. This circuit can have an output voltage as small as 2Vsat.
Fig. 4-8c shows the “gain boosted” gain boost amplifier comprising a differential pair M2/M3 with current mirror M4/M5 and gain stage M6 boosted by the cascode transistor M7. Such circuit can achieve 120 dB or more of voltage amplification.
Unless the body of M1 can be connected to the source, the feedback loop through A does not affect the M1 drain to body leakage (impact ionization current). This leakage can significantly reduce Zeqv, especially at high temperatures and large drain voltages. One of the solutions to eliminate this effect is shown in fig. 4-8d with the cascoding transistor M1 of opposite type [35].
Current gain boost is, in structural design terms, the use of an active feedback loop to suppress parasitic feedbacks in the amplification stage in order to decrease the stage output conductance. It is less known but no less useful, especially in the case of bipolar amplifiers because it also boosts the stage’s input impedance.
Figure 4-9. Current gain boost
The circuit block diagram and the signal graph for current boost in a common-collector amplification stage are shown in fig. 4.9. The series of the horizontal branches represent the transmission of the input signal in an ordinary emitter follower. Introducing the negative feedback loop with the high-gain amplifier −Y, one achieves that AC component of IC of Q0 is zero.
As one can see from the characteristics of fig. 4-9c, the amplifier improves the output bandwidth in the case with a capacitive load and the input impedance of the emitter follower by Y.
Several implementations of the structure given in fig. 4-9a are shown in fig. 4-10.
Figure 4-10. Current gain boost implementations
The circuit of fig. 4-10a is the simplest implementation with the amplifier Y implemented as a single transistor Q1. In the circuit of fig. 4-10b the amplifier Y comprises an additional current boost amplifier Q2/Q3 for larger gain. The circuit of fig. 4-10c is a class AB boosted follower that can both sink and source current to the load.
All of these circuits can be redesigned with CMOS transistors.
The circuit of fig. 4-9a does not suppress the parasitic feedback,γ ,caused by variation of the collector-base voltage (base width modulation). This limits the input impedance regardless how large the gain Y is. As shown in fig. 4-9c, the input impedance levels at low frequencies have the same values for both boosted and nonboosted followers.
This deficiency can be fixed if the voltage bias input of the current amplifier Y is connected to the follower input as shown in fig. 4-11. In this case the collector voltage of Q0 will follow its base voltage, so no internal feedback occurs. As show the normalized simulation results (fig. 4-11b) the input resistance characteristic does not level off at low frequencies as in fig.
4-9.
Figure 4-11. Current boost without limitation of the input resistance