Some current sensors implementations are shown in fig. 7-7.
Figure 7-7. Current sensors
The voltages Vbe and Vgs are monotonic functions of the collector or drain current, and they can be used for measurement of current (7-7a, b) [45]. A matching transistor of a small area with the gate-source connected in parallel to the output device is an accurate current sensor (fig. 7-7c). To improve power efficiency, a resistor, Rs, can be inserted in the sensor source wire to decrease the sensor current, Is, even further (fig. 7-7d). The voltage drop on this resistor can also be used for current sensing. The direct measurement using a small resistor in the current bus is shown in fig. 7-7e where Is=ILRs/R1.
Single-stage and current input amplifiers are preferable in the class AB circuit feedback loops as well as in other local feedback loops. This helps to avoid the compensation problems (subchapter 2-4).
Nonlinear cells should provide a function similar to the minimum selector circuits [45] with their output signal F1,2 ≈min(in1,in2). The requirements for these cells are the following:
- output is monotonic versus either of inputs,
- good accuracy versus temperature and process variations at the point where both inputs are equal,
- output does not go to zero when both inputs are non-zero.
These nonlinear cells in bipolar amplifiers often employ the logarithmic dependence of Vbe on the collector current as in the circuit of fig. 7-5. The voltage difference between the bases of QNand QP is defined as the product of their collector currents. In the rail-to-rail bipolar stage, one of the Vbe voltages can be voltage-shifted as shown in fig. 7-8a [10, p. 169].
Other realizations of nonlinear cells are shown in fig. 7-8b [80], 7-8c [45, p. 79] and 7-8d [32].
Figure 7-8. Nonlinear cells for class AB circuits
The cells of fig. 7-8b, 7-8c can employ either bipolar or CMOS transistors. The cells shown in this figure do not exhaust all possible solutions. More circuits can be found in [32, 82, 83].
Figure 7-9. NPN class AB output stage
An example of a class AB output stage for a micropower bipolar amplifier with NPN output devices is shown in fig. 7-9 [81, 88]. This stage was designed by direct implementation of the structure shown in fig. 7-3a.
The stage uses the current sensors of fig. 7-7c (QPs, QNs), the nonlinear cell of fig. 7-8b (R1, R2, Q1, Q2) and the differential stage Q1-Q4as a feedback loop amplifier with the current mirror Q6/Q7 and transistor Q5 providing additional gain. Transistors Q1 and Q2 of the non-linear cell are reused as part of the feedback amplifier. The quiescent current reference is formed by I3andR3,where R3 should match R1= R2.
Another example of a class AB output stage is the rail-to-rail CMOS output stage shown in fig. 7-10a. This Class AB stage is also designed by direct implementation of the structure shown in fig 7-3a. It consists of the current sensors of fig 7-7c (MNs, MPs), the nonlinear unit of fig. 7-8d and the transistor MA as the feedback amplifier G.
Figure 7-10. CMOS rail-to-rail class AB stages
If the input signal is applied to both gates of MN and MP, then the class AB circuit may be symmetrical as shown in fig. 7-10b.
For lower supply voltage, the amplifier MA of fig. 7-10a can be replaced by the differential stage MA, MB (fig. 7-10c), or a more complicated low- voltage amplifier.
Numerous realizations of the structure 7-3a for rail-to-rail output stages can be found in [10, pp. 169-176, 45, subchapter 3.5].
The implementations of the structure shown in fig. 7-3b do not require a minimum-like function units as shown in fig. 7-8, but they need a cells with a transfer function similar to limiting rectifiers. The transfer characteristics FN and FP of these cells allow one to switch off one of the local feedback loops when the current of one of the output devices increases above the Iq
level. At this time the opposite side transistor current drops significantly
below Iq and this transistor is not providing gain any more. Both feedback amplifiers G should have a differential output.
The simplest current limiting cell is a transistor in the common-gate configuration (fig. 7-11a), where the current can flow in only one direction (it can be called a current rectifier). The simplest voltage rectifier is a diode- connected transistor (fig. 7-11b). Accuracy of the limitation can be improved using an amplifier (fig. 7-11c and 7-11d), with the penalty of amplifier delay. The current-input amplifier of fig. 7-11e has a smaller delay but its biasing current runs through the load.
Figure 7-11. Limiting cells
In the stage of fig. 7-6a, the output devices themselves provide the current sensing (as it is suggested by fig. 7-7b). Transistors MNs and MPs also provide a limiting function as in fig. 7-11a as well as switching (when an input voltage turns on MNs and it starts to drive MP, the transistor MPs will be off). Both MNs and MPs are reused as feedback amplifiers with their source and drain acting as differential outputs (splitters). This is probably one of the most elegant implementations of the class AB output stage. It does, however, have the following drawbacks:
- large minimum supply voltage (Vdd >VgsP + VgsN + Vsat ≈ 2.5V);
- strong dependence of Iq on the supply voltage, especially using short- channel transistors;
- low input impedance of the stage caused by the drain-body leakage of MNs or MPs when implemented in a single-well process and with large supply voltage.
This low input impedance can limit the open-loop gain of a two-stage amplifier (for example, in the OpAmp of fig. 4-21). Transistors MNs and MPs of fig. 7-6a may have large drain voltages causing impact ionization in the drain region and high drain to body currents. If the body can be connected to the source then this leakage does not create any problems. But in a single- well process, the body of at least one transistor is connected to the substrate.
For instance, in most of the 0.6 um processes this leakage would limit the open-loop gain to 80-90 dB in a two-stage OpAmp with a 5V supply voltage.
Figure 7-12. Improvement of the input impedance of Class AB output stage
A solution to this problem is shown in fig. 7-12 [35]. The stage has the same structure as that of fig. 7-6, yet includes an additional dedicated local feedback loop. This loop comprises the amplifier M1, M2, M3 and controls
N
dMns V
V ≈ eliminating the impact ionization effects in MNs. The bulks of MPs and M3 are connected to their sources, so the drain leakage in these transistors does not affect the equivalent input resistance that is limited now by the output resistance of the signal source and the current source I0.
The poles in the OpAmp transfer function, which are located far in the left half-plane and limit the OpAmp maximum achievable bandwidth, are defined largely by the size of output devices. For example, increase of the MN and MP channel length from 0.6 um to 1.8 um, while increasing the width to keep the same current capability, decreases the achievable GBW by 5 times. This means that in order to improve the OpAmp speed, the output devices should be as short as possible.
The Vgs voltage in short-channel transistors is strongly dependent on Vds. This correlation causes a significant error in Iq measurements. This is valid not only for the stage of fig. 7-6, but for any other stage using the same current sensing approach, i.e. where the output devices also act as the current measuring devices. As a result, the variation of Iq versus supply voltage in the stage of fig. 7-6 can be up to 2 times different when the transistors MN and MP have a length of L=0.6 um. This error is much larger for finer geometries.
This problem can be solved by controlling the reference voltage sources VN and VP. The circuit of fig. 7-13 [118] shows VN generation depending on the Vds variation in the sensor devices.
The voltage VN =(VgsM1+VgsM2) is generated here in the feedback loop M1-M3-M2. In this loop, M1 matches MN, and M2 matches MNs. The voltage VdsM1 now tracks VdsMN as the gate of M3 is connected to Vout. The transistor
M4 prevents the current source 2I1 from saturation when Vout approaches the positive rail. The currents through M1 and M2 are equal to I1.
Figure 7-13. Improvement of the Iq versus supply voltage stability
The mismatch of the Vds voltages for M2 and MNs does not produce any significant error as these transistors may have a longer channel and therefore less variation of Vgs versus Vds.
Using the circuit 7-13 for the generation of both VN and VP voltages ensures a stability of Iq versus supply variations of better than 5%, even with a 0.5 um channel length of the output devices [87].
Fig. 7-14 shows another example of the class AB output stage implemented in accordance with the structure of fig 7-3b. The stage is capable of operating with the supply voltage of Vdd ≥Vgs+2Vsat ≈1.3 V [85]. The Iq control feedback loop for the output transistor MN consists of the current sensor MNs, reference current INq, diode-connected limiting transistor D1 and amplifier with differential output at the drains of M3 and M4. The resistor R0 defines the gate potential of M2 when this feedback loop is not in operation, and decreases the excessive loop gain. Transistor M4 is wider than M3, and this mismatch defines the control range.
When the drain current of MNs drops below INq, the difference of these currents starts to flow through D2 and creates a voltage drop across R0. The amplifier M3/M4 steers more current to the gates of MN/MNs. This increases the gate potential of the MN/MNs parallel connection. Hence, the value of the MNs current is kept stable, and defined by INq, R0 and the size ratio between M3 and M4. One may notice that any current that is added or subtracted from the gate of MN is subtracted or added to the gate of MP. Hence, the operation of this loop does not affect the overall stage gain.
The operation of the feedback loop for MP (this loop includes MPS – D2 – M1/M2) is identical as for MN.
Figure 7-14. Low voltage supply class AB output stage with two separate feedback loops
This stage was used in the nanopower (Iq≈1uA) OpAmp [86]. To avoid large resistor values and the loading of V1 and V2,R0 was implemented as an active circuit shown in fig. 7-14b, which is providing R0 = 1/gm. Transistors M2 and M3 were reused as part of the folded cascode stage preceding this class AB stage. Currents I1 are the outputs of the current mirrors of this folded cascode.
The examples considered above demonstrate the main points of the structural design methodology procedure: start from the general structure and its equivalents; generate a set of circuit solutions based on the elementary cell library; improve the important parameters using additional local feedback loops.
8.