Implementation of the chosen structure (two-stage OpAmp) starts from the sizing of the input differential pair and output devices and simulations of the simplest possible OpAmp (fig. 9-4) to find the minimal achievable noise
and the maximum bandwidth within a given current budget (or, inversely, one can find the minimal current to realize these two required parameters).
In our example, 1σ of the offset voltage, Voff, should be 5/3 = 1.6 mV = Vmtch/ WL. The input devices area should be (WL) > (Vmtch/1.6)2 > 250 um2.
Tail current can initially be set at 10% of the total budget, i.e. to 10 uA or 5 uA in each of the input transistors. Using the curves from fig. 9-1 for L=2 um, and assuming operation in weak inversion, one can scale and find that, with 5 uA of the ID, the required W/L ratio of PMOS input transistors should exceed 300 and of NMOS exceed 100. One may choose PMOS device with W/L = 300/1 (15 devices with W/L = 20/1) and NMOS device with W/L = 200/2 um (10 devices with W/L = 20/2),to satisfy both gm and overall area requirements.
Now let’s look at the output devices. The maximum Vgs for the output devices with a 2.2 V supply voltage can be around 1.5-1.6 V while running 5 mA of ID. For the smallest overall size, these devices should be of minimum length, L = 0.5 um. To achieve 5 mA current with 1.5 V of Vgs, their W, in accordance with the curves of fig. 9-2, should exceed 600 um (30 of 20/0.5 devices) for PMOS and 200 um (10 of 20/0.5 devices) for NMOS (the calculations in this and previous paragraphs are done with some margins).
These values may be doubled to ensure the sufficient output current capability versus temperature and process variations.
Figure 9-4. Circuits for estimation of maximum achievable bandwidth
Simplified circuits shown in fig. 9-4a and 9-4b include only the input pair and only one output device (MN or MP). Final circuit will include a class AB output and other circuits, but this will be added later. Quiescent current, Iq, of the output stage can be set initially to 50% of the total budget, i.e. to 25 uA.
Simulations at this step include the open loop gain and phase frequency responses for these simplified circuits, and it is rational to obtain results for the circuits with and without compensation (fig. 9-4c). Point where the phase response of uncompensated amplifier is crossing 0o (approximately 30-40 MHz in fig. 9-4c)) is defined by the parasitic capacitors, delays in transistors and by the feedforward through Cgd of the output device. This figure indicates 3 to 5 times the maximum OpAmp bandwidth achievable for the chosen output device size and bias currents.
Figure 9-5. Stability deterioration with capacitive load
With a 1pF Miller compensation capacitor, the amplifier has a 6 MHz bandwidth with 65o phase margin (without any capacitive load). Results of AC simulations for the load capacitance in the range of 1pF to 300 pF (with the step of two values per decade) are shown in fig. 9-5. OpAmp bandwidth starts to diminish noticeably even for 30 pF load capacitance. The amplifier remains stable for any load capacitance in the chosen range. However, for the load of 300 pF, the phase margin is only 6o.
Simulations of small-step (say, 10 mV) transient responses (fig. 9-6) should verify these results.
OpAmp tolerance to the load capacitance improves with a larger current in the output device. An improvement (limited in practice) can also be achieved using the cascoded Miller compensation [50]. Another way to improve the speed and capacitive load tolerance is to change the OpAmp gain structure from two-stage to single-stage. Regretfully, there is no known
way to combine the rail-to-rail output capability and voltage (high input impedance) input in the single-stage OpAmp.
Figure 9-6. Small-signal step transient responses for the range of capacitive loads
At this design step, the designer must realize that if a better tolerance to a load capacitance is required, and there is no available current budget, then the only means left is to slow down the amplifier using a larger CM or a smaller transconductance of the input stage.
If the design involves a high-speed OpAmp (with more than 200 MHz bandwidth) then the ESD cells and wirebond macromodels should be added at this first step, and their impact on high-frequency gain and phase response should be evaluated in the same manner.
OpAmp noise is another parameter whose achievable boundaries are determined at this design step. Simulated input-referred noise for the amplifier of our example is shown in fig. 9-6.
Figure 9-7. Spectrum density of the input-referred noise
This noise characteristic is flat at high frequencies and becomes proportional to 1/f at low frequencies. High-frequency noise is defined by the gm of the input devices [10, p. 85]. In our example, with 10 uA tail current, it is 40 nV/ Hz. This value is only about two times larger than the corresponding figure for a bipolar transistor pair carrying the same tail current. An advantage of a MOS transistor is the absence of input current, so
the tail current can be increased as necessary to reduce the high-frequency noise.
The flicker (1/f) noise corner in this example is around 70-100 Hz.
Contrary to the common opinion [10], CMOS transistors in modern processes can be competitive with bipolar ones in terms of the noise performance. Flicker noise is inversely proportional to WLof the input devices and can also be reduced. The trade-off for smaller flicker noise is increased parasitic capacitances at the drains of input devices. An excessive increase of their area may limit the OpAmp speed.
The OpAmp slew rate, in absence of a slew enhancing circuit, is dVout/dt
≈ gm1/CM and can also be determined at this design step. If this value is not satisfactory, then the OpAmp topology should be changed and design of slew enhancement circuits (chapter 8) should be planned.