consequences for legal theory and practice

... Chicago, the So-cial Philosophy and Policy Center of Bowling Green State University, theAmerican Society for Political and Legal Philosophy, and the Institute forPolitical Studies of the Portuguese ... distinctions between pluralism and monismand between comprehensive and freestanding conceptions, I suggest thatthere are four main types of political theory: 1 freestanding/monist John Rawls’s Political ... is an understanding of liberalism that givesdiversity its due This understanding is expressed in public principles,institutions, and practices that afford maximum feasible space for theenactment

Ngày tải lên: 30/03/2020, 19:32

... reduced, and forward body bias (in this example, NMOS forward body bias) can be applied to further increase the performance This combination reduces the guardband needed for maximum temperature and, ... using a static technique and are typically guardbanded using either reduced frequency or higher supply voltage This guardbanding is expensive in terms of performance and power and is becoming prohibitive ... 3.4GHz at 1.4V, and total power consumption at 1.2V is 1.3W for a high-activity test Frequency can be increased by 9–22% through application of NMOS and PMOS forward body bias FMAX and power measurements

Ngày tải lên: 21/06/2014, 22:20

... , and I , for the two different structures as a function of voltage and knowing A,, P a , A , and P , for the two structures, we can calculate I,,,, and Iperi using Eq (2.81) respectively for ... (2.76) for Qdif and Id is given by Eq (2.82) Using Eqs (2.74) and (2.75) for Cj we get IOVd vd ' Fc($bi (2.86) Trang 964 2 Basic Semiconductor and p n Junction Theory The variables F,,F, and ... temperature SPICE assumes E , = 1.1 1 eV for silicon, 0.67 eV for Germanium, and 0.69 eV for SBD The temperature exponent factor p equals 3 for silicon and germanium while for SBD its value is 2 From Eq

Ngày tải lên: 13/08/2014, 05:22

... substrate n-type for pMOST and p-well for nMOST) Another alternative is to form two separate wells (n-well for pMOST and p-well for nMOST) in the primary substrate so that n- and p-device characteristics ... effects on device behavior For increased current drive and hence circuit speed a large W and small L is required It is important to understand what device L and W stand for from the modeling point ... the contact via and the channel region, p , is the sheet resistance per square (n/o) and W is device width For a typical 1 pm CMOS technology, p , = 30 and 6 0 R / O for n+ and p + regions,

Ngày tải lên: 13/08/2014, 05:22

... expression for Q, that is valid for all the regimes of device operation by including both the holes and electrons and thus solving the Poisson Eq (2.41) Using Eqs (4.33) for n and p and noting ... which Eq (4.66) is based To solve for the MOS capacitance at flat band, called thepat band capaci- tance C f b , we need to use Eq (4.48) for Q , or Eq (4.57) for C, For 4 < 0 we have e - + s ... device operation for a p-type substrate, N , = 5.1015 cm- ’, to, = 300 A, and V,, = 0 V Trang 84.2 MOS Capacitor at Non-Zero Bias 143 Using Eq (4.29) for Qb and Eq (4.39) for Q,, we get the

Ngày tải lên: 13/08/2014, 05:22

... charge and hence threshold voltage However, such complex models are not suitable for use in circuit simulators For this reason they are not discussed here and details of the equations for Qb and ... (5.37) Solving Eqs (5.38) and (5.39) for N , , and using Eq (5.36) for X , , yields (5.40) where q5i is given by Eq (5.35) This value of N , , is used for N , in Eq (5.29) for the body factor term ... , becomes a function of back bias, and therefore y is no longer a constant but is bias dependent For a uniformly doped substrate N , equals N , , and therefore Eq (5.40) gives N , , = N , Thus,

Ngày tải lên: 13/08/2014, 05:22

... A H Marshak and R Shrivastava, ‘On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate’, Solid-state Electron., 1361 M Nishida and M Aoyane, ... evident from curve (a) and (b) (Figs 5.31 and 5.32) which are for Vsb = 3 V and 0 V, respectively n-Channel Devices (nMOST) For n-channel enhancement devices (n' polysilicon gate and p-substrate) ... channel implanted devices, curve (d) is for uniformaly doped device Although both curves (b) and (c) are for enhance- ment devices, curve (b) has higher t0,(300A), and lower surface concen- tration

Ngày tải lên: 13/08/2014, 05:22

... 4, by q5s, and have made use of Eq (6.23) for y and Eq (6.22) for Vq! Remembering that Vcb(y = 0 ) = V,b and Vcb(y = L ) = V,b+ V,,, the inversion charge Q i s and Qid at the source and drain ... calculated and measured drain current for an n-channel depletion device fabricated using an NMOS Fig 6.20 Measured and calculated transfer and output characteristics at different back bias for an ... reality this is not true and I,, has small but finite values for V,, < V r h For the device shown in Figure 6.5 this current is of the order A when V,, approaches Vr, and then decreases exponentially

Ngày tải lên: 13/08/2014, 05:22

... Eqs (6.142), (6.174) and (6.204) for p,, Vds,, and ld, respectively The corresponding I d , - Vd, and I,, - Vgs characteristics for n-channel device are shown in Figures 6.34b and 6.34c, respectively ... drift and diffusion currents simultaneously without distinguishing between the weak and strong inversion regions However, this leads to a more complicated equation for the current Therefore, for ... Vgxl and VgX2 between weak and strong inversion, is modeled by a third order polynomial of the following form [112] I d s J = I d s , w + Ids,s (6.2 1 6) where the coefficients a, b, c and d

Ngày tải lên: 13/08/2014, 05:22

... integration formula Note The subscript j stands for G, S, D or B for the charge Q and capacitance C, as we are now dealing with the total charge or total capacitance However, for current and voltage, ... Figure 7.14 for Qs and QD with and without velocity saturation, Fig 7.14 The normalized source and drain charges, Qs and Qd, respectively, as a function of Vds for different Vgs, with and without ... The equations for C,, and C,, are obtained by differentiating Q, [Eq (7.55a)l with respect to V, (or V,,) and Qc [Eq (7.58)] with respect to Vd (or V,,), respectively, and using d and &7 defined

Ngày tải lên: 13/08/2014, 05:22

... quasi-static application of Eq (8.35) for nMOST [8], [41] and Eq (8.37) for pMOST [47] Thus, for example, zAC for nMOST is given by (8.38) where T is the full cycle time, I , and I d are the currents at ... between the model and data validates Eq (8.30) 8.3 Correlation of Gate and Substrate Current Since the hot electrons responsible for the gate current and those responsible for the substrate ... V,,(V) Fig 8.8 Gate and substrate currents I , and I , , respectively, as a function of gate voltage V,, for different drain voltage V,, for a nMOST (After Takeda et al [ 2 6 ] ) for different drain

Ngày tải lên: 13/08/2014, 05:22

... where the + and - signs are for n- and p-substrate, respectively, and c h f o and CLfo are values of c h f and C k , respectively, at V, = V,, (9.1 1) This method of determining Cox, and hence ... (4.63) and (4.64) as (9.19) Although Eqs (9.18) and (9.19) are derived for uniform substrate doping, they remain valid for the case of nonuniform doping These are the basic equations for measuring ... Combining Eqs (2.15) and (4.74) and solving for the substrate concentration N yields (9.13) where A, is the MOS capacitor gate area This is a transcendental equation for N and therefore must be solved

Ngày tải lên: 13/08/2014, 05:22

... = W,,, - A W [cf Eq (3.33)] It is the L and W and not L, and W , which are used for modeling MOSFET devices (cf section 3.7) This in turn requires AL and A W to be known In this section we will ... proposed by Terada and Muta 1601, was reformulated by Chern et al [61] and later slightly modified by many others [62]-[68] It is the most commonly used method for determining AL and has become widely ... following equation where Q 1 and d2 are the values for (do/po + R,) for the devices with channel length L,, and Lm2, respectively In a method proposed by Suciu and Johnston [79], the quantity

Ngày tải lên: 13/08/2014, 05:22

... two minima (at p = 1 and p = 5 ) one of which is the global (at p = 5 ) for finding the global minima of an arbitrary function [20], in practice values for the parameters and observing the parameter ... effort for calculating the Hessian H in order to solve for Ap In general, the Hessian matrix H is difficult to solve with sufficient accuracy For this reason approximations are often used for ... other words, these models have separate equations for linear, saturation and subthreshold regions of the device operation with explicit formulations for threshold voltage, saturation voltage, etc

Ngày tải lên: 13/08/2014, 05:22

... fabricated using a l p m CMOS process The values for the parameter I,, q and r , for two types of diodes (n'p and p'n) are shown in Table 11.2 For comparison the parameters obtained using the ... by switching the diode from a forward voltage V ’ to a reverse voltage V,, and using the following equation [4]-[6] .- (11.4) where I, and I , are the forward and reverse current, respectively, ... - 1 for gate type same as the substrate (11.16) and is used to calculate Qms and hence V,,(= Q m s - qN,,/C,,) [cf Eq (4.14)], as follows: I 0 for aluminum gate - 0.5 - 0.5E, - 0.54, for TPG

Ngày tải lên: 13/08/2014, 05:22

... sources of leakage current, and each of these has a different dependence on both voltage and temperature [17] Understanding of the relation between leakage and both voltage and temperature requires ... current is due to band-to-band tunneling in the presence of high electric field and traps in the band gap If the electric field is high enough, carriers can simply tunnel across the band gap However, ... Core for Low-Power and High-Performance Applications,” IEEE Journal of Solid-State Circuits, Vol 36, pp 1599–1608, November 2001 [2] M Meijer, F Pessolano, and J P de Gyvez, “Limits to Performance...

Ngày tải lên: 21/06/2014, 22:20

... determine power-performance trade-offs and leakage reduction factors with AVS and ABB Each ring-oscillator uses minimum-sized standard-cell inverters as delay elements and a nand-2 gate for enabling ... Power and Frequency Tuning The ultimate use of the AVS and ABB schemes is for performance tuning with performance being the optimal combination of frequency and power, i.e the lowest power for ... Figure 2.5 Frequency scaling and tuning for the 65nm LP-CMOS ringo Let us now investigate the frequency-scaling and tuning ranges offered by AVS and ABB in 65nm LP-CMOS For this purpose, we determined...

Ngày tải lên: 21/06/2014, 22:20

... useful for power and delay tuning in the state-of-the-art CMOS technologies We observe the benefits of AVS primarily for low power and of ABB for performance tuning For instance, for a 65nm LP-CMOS, ... previous results for compensating process-dependent frequency and leakage spread The values for frequency, power supply voltage, and leakage current are plotted for reference and tuned process ... Nair, D Antoniadis, A Chandrakasan, and Vivek De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage”, IEEE Solid-State...

Ngày tải lên: 21/06/2014, 22:20

... energy References [1] V Gutnik and A Chandrakasan, “Embedded power supply for low-power DSP,” IEEE Trans VLSI Syst., vol 5, no 4, pp 425–435, Dec 1997 [2] A Sinha and A Chandrakasan, “Dynamic power ... analysis and optimization for VLSI: timing and power,” New York, Springer, pp 79–132, 2005 Chapter Adaptive Supply Voltage Delivery for U-DVS Systems 121 [11] B Zhai, S Hanson, D Blaauw, and D ... equation: V − VDD τN = BAT VDD τP (5.4) where τN and τP are the NMOS and PMOS ON-times and VBAT is the battery voltage Thus, by fixing τP, the values of τN for specific load voltages can be predetermined...

Ngày tải lên: 21/06/2014, 22:20

... essentially an FET wire; and NAND and NOR gate paths consisting of a series of 4-high NAND and 3-high NOR gates respectively Simulations were performed at two frequencies, F and F/3 where F was 4.5 ... important to understand these processes and their effect on the number and location of critical path monitors Chapter Sensors for Critical Path Monitoring 149 7.3.1 Process Variation Random, uncorrelated ... the capacitance/width of the drain, and Rw and Cw are the resistance and capacitance per unit length of the wire For buses, the value of l is large, while for dense logic, the value of l can...

Ngày tải lên: 21/06/2014, 22:20