Tài liệu Phần mềm xác định radio P5 pdf

For a junction of 0.3 £ 0.3 mm, this isabout 0.1 ps.A design consideration for Josephson junctions in RSFQ circuits is that they be sufficientlydamped to prevent hysteresis upon exceedin

5.1 Introduction

The speed and flexibility enabled by superconductor microelectronics seems well matched tothe goals of proposed software radio architectures For the purposes of this work, we will only

1 ‘Pure’ software radio, as distinct from ‘pragmatic’ software radio, incorporates the concept of signal digitization

at the antenna Such concepts are introduced in Chapter 1 by Walter Tuttlebee in Software Defined Radio: Origins, Drivers and International Perspectives, Tuttlebee, W (Ed.), John Wiley & Sons, Chichester, 2002 Chapter 2 by Wayne Bonser in that volume also provides excellent background on the defense motivations, systems, and experi- ence of software radio alluded to later in this chapter.

Edited by Walter Tuttlebee Copyright q 2002 John Wiley & Sons, Ltd ISBNs: 0-470-84318-7 (Hardback); 0-470-84600-3 (Electronic)

examine the field of low temperature superconductors – specifically niobium (Nb), whichhas a critical temperature (Tc) of 9.23 K Digital niobium circuits are operated between 4.2and 5 K and generally employ an IC fabrication process for implementing the rapid singleflux quantum (RSFQ) logic family [1] The kinds of circuits we assume can be made in thistechnology are data converters and digital signal processing (DSP) type circuits Thisassumption is based on the fact that there have been many groups, in both industry andacademia, which have successfully demonstrated these types of circuit However, for currentpurposes, we will take the liberty to assume that such chips can be made with greatercomplexity than yet achieved and can be manufactured with a reasonable yield Fabricationtechniques, discussed later, are not dissimilar from those used today for silicon ICs, so this isnot an unreasonable assumption, although timescales for such a scenario will be investmentdependent Given these caveats, we can begin a discussion of the application of such super-conductor circuits to both commercial wireless and defense communications.

The title of this chapter refers to an approach called ‘digital RF’ By this we mean that thesuperconductor logic gates will directly process digital signals at RF or multi-GHz frequen-cies This might be Mbps digital data modulated on an RF carrier, or it might be a digitalGigabit data stream of samples from an analog-to-digital converter (ADC) In the followingsections, we show examples, on both the receive and transmit sides, of how such RSFQcircuits can benefit: (1) a CDMA-type base station for commercial wireless; and (2) militarysystems with their varied and disparate requirements of frequency, bandwidth, and protocol

It is the performance characteristics of RSFQ that can enable the kind of flexible, high datarate applications that are being talked about as third and fourth generation, 3G and 4G,wireless services The need to embrace legacy systems, while building in flexibility, indefense applications is an even more formidable task However, such ideal ‘software radios’may only be possible if implemented using a digital RF architecture with superconductors

5.1.1 Superconductivity and the Josephson Effect

We begin by briefly reviewing the phenomenon of superconductivity [2] Although mostreaders will be familiar with the trait that superconductors exhibit zero resistance whencooled below a critical transition temperature (Tc), fewer may recall the second (and perhapseven more remarkable) feature – superconductors can contain magnetic flux only in certaindiscrete quantities Called ‘flux quantization’, and illustrated in Figure 5.1, this behavior can

be exploited to construct a variety of circuits that have no dual in the semiconductor realm

If a closed section of superconductor material is subjected to a magnetic field, screeningcurrents will orient themselves such that the flux threading the closed section is quantized.This amount of magnetic flux F threading the loop is given by integrating the normalcomponent of the incident field B over the area A of the closed section F ¼R

BdA ¼ nF0where n is an integer and F0¼ h=2e ø 2:07 £ 10215Webers (We) is called the ‘flux quan-tum’ or ‘fluxon’

In order to create digital circuits, an active superconductor component is needed – theJosephson junction (JJ) As shown in Figure 5.2, a JJ consists of two Nb electrodes separated

by a thin insulator (typically Al2O3) Denoted in a circuit diagram by a cross, the JJ’s principalparameter is its critical current Ic When a bias current I , Icis applied from base to counterelectrode, the device exhibits no resistance However, when I Icis applied, the JJ becomesbriefly resistive The time scale of this event is dictated by the capacitance of the thin

insulator For a junction of 3 £ 3 mm, this is about 1 ps For a junction of 0.3 £ 0.3 mm, this isabout 0.1 ps.

A design consideration for Josephson junctions in RSFQ circuits is that they be sufficientlydamped to prevent hysteresis upon exceeding the critical current, so that the junction quickly

Figure 5.2 Josephson junction and SQUID configurationsFigure 5.1 The phenomena of superconductivity: zero resistance and magnetic flux quantization

returns to the zero voltage state As we show below, this rapid voltage pulse corresponds to asingle flux quantum F0, and forms the basis for RSFQ logic As illustrated in Figure 5.3, this

is generally analyzed in terms of a shunted junction model, in which the ideal Josephsonjunction of capacitance C is shunted with a linear resistance R [3] The junction itself can becharacterized as a nonlinear inductor of magnitude given by the Josephson inductance LJ ¼

F0/2pIc Such a parallel network has two characteristic times, RC and LJ/R If the former time

is larger, the junction is underdamped; in the other limit, it is overdamped

If we embed the resistively shunted junction of Figure 5.3 into the closed superconductorloop of Figure 5.1, we obtain a superconducting quantum interference device (SQUID),illustrated in Figure 5.2 The inductive loop provides the quantization of magnetic flux,and the junctions provide a switching mechanism for loading and unloading flux into andout of the loop This SQUID configuration, known for many years now, is the basis of allsuperconductor electronics

5.1.2 Established Applications of Superconductors

In the past few years, superconductor microelectronics has started to emerge into the cial arena from university and industry R&D laboratories, providing unsurpassed performancecharacteristics [4] Superconductor magnetoencephalography (MEG) systems for imaging thehuman brain are commercially manufactured by several companies and over a hundred of thesesystems are in use today The extreme sensitivity of these instruments allows diagnosticmedical data to be gleaned from neuron dipole moments down to a few nA-m2

commer-Figure 5.3 Hysteretic and nonhysteretic Josephson junction behaviors

Even the Systeme Internationale (SI) unit of the Volt is defined by a superconductorintegrated circuit HYPRES, Inc (Elmsford, NY) currently offers commercial productsbased on superconductor integrated circuits, packaged with a small mechanical refrigerator

to provide temperature regulation, allowing this standard volt to be reproduced anywhere inthe world with quantum mechanical accuracy Simply put, these are applications that cannot

be performed with any other technology; therefore the motivation to accept the uniquecharacter of cryogenic operation is strong As a consequence, these applications have driventhe state of the art in cryopackaging to the point where all cryogenics have become invisible

to users of such products

5.1.3 Emerging Applications – Software Defined Radio

As the ‘cryophobia’ associated with superconductor microelectronics is overcome, the range

of possible applications continues to widen In communications, dispersion-free, ultra-high

Q superconductor microwave filters for cellular base stations are today offered from severalcompanies in the United States, Europe, and Japan Close to a thousand such units havebeen purchased and installed around the United States, with orders pending from majorcarriers in Europe The use of superconductor material allows the very high Qs to bemaintained, while microminiaturizing the overall filter size The ultra-sharp filter ‘skirts’that result enable increased channel selectivity and, with a cooled LNA, yield increasedsensitivity as well

Recently, wireless telephony has been shifting from voice/narrowband data to widebanddata, along with demands for significant increases in capacity These have become theindustry’s major drivers, with the major obstacles becoming air interface compatibilityand bandwidth allocation An increasingly embraced solution to surmount these obstacleslies in the concepts of software radio [5] However, realization of software radio systems

Table 5.1 Demonstrated RSFQ digital circuit performance

with 6 £ 32 bit on-chipmemory buffer

presents a host of challenges – chief among them the unprecedented requirement on to-digital converter (ADC) performance [6] This is the area where superconductor micro-electronics represents an emerging solution With demonstrated ADC, DAC, and DSPcomponents, this technology may well become a key enabling technology for softwareradio [7] Table 5.1 summarizes the performance already achieved with such superconduct-ing devices to date Unlike commercial systems, which are primarily cost/performance-driven, defense applications tend to be primarily performance driven, with cost as a closesecond In addition, military radio requirements are far more demanding than those forcommercial systems.

analog-5.2 Rapid Single Flux Quantum Digital Logic

By now the reader may be wondering why a digital superconductor IC technology has notalready been established In fact, there were two large digital superconductor programs – onethat ran at IBM from 1969 to 1983 and another in Japan from 1981 to 1990 Rather thanrelying directly on quantized bundles of magnetic flux as bits, those efforts (and others at thetime) attempted to use the voltage state of the JJ as a ‘1’ and the superconducting state as a

‘0’ Many fully functional circuits were demonstrated, culminating with a 1 GHz 4-bit processor by NEC [8] However, it was this choice of logic convention which ultimately led

micro-to the conclusion of the program A reset effect called ‘punchthrough’ limited the speed ofoperation to just a few GHz In contrast, very large scale integration (VLSI) RSFQ circuitsshould operate up to 250 GHz Power consumption was another issue A typical latching gatedissipated about 3 pW Although this sounds small, RSFQ technology dissipates only onetenth of this, at 0.3 pW/gate The need to distribute an AC power supply was also a problemand made timing issues extremely complex

5.2.1 Circuit Characteristics

5.2.1.1 Circuit Structures

In RSFQ circuits, it is not a static voltage level, but the presence or absence of quantizedmagnetic flux (fluxons) that represents information bits The basic RSFQ structure is a super-conducting ring that contains one Josephson junction plus a resistive shunt outside it (seeFigure 5.4)

Suppose a current is already a circulating around the loop, supporting one fluxon At a certaincritical current level (about 100 mA for typical designs), additional DC current across the loopcauses the fluxon to be ejected, with the Josephson junction acting as a briefly opened exit.Rather than use the escaping flux directly, RSFQ relies on the fact that the movement of afluxon into or out of this loop induces a very short voltage pulse (known as an ‘SFQ pulse’, forsingle flux quantum) across the junction If the Josephson junction were a square, 1 mm on aside, this SFQ pulse would be <1 ps long and 2 mV in amplitude The SFQ pulses becomenarrower and greater in amplitude as the junctions decrease in area but, because theirmagnetic flux is quantized, the voltage–time product of the pulse always remains thesame: 2 mV-ps, i.e 2 £ 10215Wb The energy consumed each time an SFQ pulse passesthrough a junction is just the circulating current of about 100 mA times the amount of flux F0,

or only ~2 £ 10219J

These SFQ pulses are used to form RSFQ digital logic gates composed of only a few basic

circuit structures These building blocks allow the generation, transfer, storage, and tional routing, or ‘switching’, of SFQ pulses Shown in Figure 5.5, the three basic structuresinclude an active transmission stage (JTL or Josephson transmission line), the storage loop,and the decision making pair (or comparator).

condi-5.2.1.2 Fabrication and Packaging

RSFQ integrated circuits are made with standard semiconductor manufacturing ment; however, there are many fewer mask layers (typically about ten) and the actualprocessing involves much less complex depositions [9,10] Because RSFQ logic is an all-

equip-Figure 5.4 Physical realization of a resistively shunted Josephson junction

Figure 5.5 The three basic structures of RSFQ logic

thin-film technology, there are no doping profiles to calculate, no high temperature ins, no epitaxial growths, or chemical vapor depositions These differences are expected

drive-to translate directly indrive-to reduced costs in the large scale manufacture of RSFQ nics

electro-Architectures containing both front end analog circuitry, as well as digital processingblocks, are fundamental SDR requirements This configuration presents extraordinary diffi-culties for semiconductors, due to ‘crosstalk’ – problems of interference between the analogand digital sections of the same chip Because of the unique reliance on single quanta ofmagnetic flux to convey information, RSFQ are inherently more immune to this sort ofcrosstalk

The RSFQ technology also has a clear path to extend performance Unlike semiconductordevices, the speed of RSFQ ICs comes from inherent physical phenomena, not ultra-smallscaling This means that existing lithography techniques can be employed and, more impor-tantly, existing equipment can fabricate circuitry that surpasses conventional limits of perfor-mance Because RSFQ logic uses the lossless ballistic transmission of digital data fluxons onmicrostriplines near the speed of light, the wire up nightmare that silicon designers face issubstantially reduced This scenario also allows the full speed potential of individual gates to

be realized

Other features of this technology that make it suitable for growth into the traditional marketinclude its compatibility with existing IC packaging techniques These include compatibilitywith optical (fiber) signal input and output, a maturing multichip module (MCM) technologywith multi-Gb/s digital data transfer between chips, and simple interface circuits to convert toand from both ECL logic and CMOS logic levels

5.2.2 Example RSFQ Logic Gate – RS Flip Flop

To transfer SFQ pulses as information bits, a clock may be used to provide a steady stream oftiming pulses (one per clock cycle), such that the presence of a data pulse within the clockcycle denotes a logic (1), while the absence of one denotes a logic (0) Combinations ofJosephson junctions can then be interconnected to achieve SFQ pulse fan-in and fan-out andcreate a variety of logic structures Although all common binary logic primitives (like AND,

Figure 5.6 Basic building blocks of an RSFQ gate

OR, or XOR) can be fashioned, it is often more convenient to create gate macros directlyrather than from lower logic primitives This technique maximizes speed and minimizesjunction count The operation of an RSFQ reset–set flipflop gate provides a simple example(see Figure 5.6).

If a set pulse arrives, J1 transmits it into the quantizing inductance loop, where it becomestrapped as a circulating current – the 1 state This current biases J3, so that when a clock/resetpulse arrives at the gate, it causes J3 to transmit the stored fluxon to the output, thus resettingthe flipflop to the 0 state Alternatively, if no set pulse input has occurred during the clockperiod and a clock/reset pulse arrives, the unbiased J3 cannot transmit the pulse and J2 isforced to let the fluxon escape the circuit, so no pulse appears at the output

5.2.3 RSFQ Data Converters

5.2.3.1 Analog to Digital Converters

The quantum precise periodic transfer function of the superconducting quantum ence device (SQUID) makes superconductor circuits an excellent choice for data conversionfrom a continuous time to a discrete time format [11] Figure 5.7 shows a block diagram and achip photo of an RSFQ ‘high resolution’ ADC based on a phase modulation/demodulationarchitecture [12]

interfer-This superconductor ADC design is especially linear, because the quantization thresholdsare set by a ratio of fundamental physical constants (h/2e) in the SQUID in the front end Thisleads to an enhanced spurious free dynamic range (SFDR) in comparison to semiconductorADCs, whose thresholds are set by the matching of device characteristics Common perfor-mance metrics for ADCs are the SINAD and the SFDR.2 SINAD is a signal-to-noise and

Figure 5.7 Phase modulation/demodulation ADC: block diagram and chip photograph

2 These metrics are described generally in Chapter 2, and, in the context of ADCs, in Chapter 4.

distortion measurement, and represents the dynamic range of the signal with respect to alldigitization artefacts SFDR is the spurious free dynamic range, reflecting the linearity of theADC process by indicating the ratio of signal to the highest spurious signal in the Nyquistband.

Demonstrated performance for the first HYPRES RSFQ ADC (shown in Table 5.2) is aSINAD of 58.2 dB (9.4 effective bits) and an SFDR of 278.7 dBc at 100 MS/s Nyquist ratesampling The same chip also provides 14.5 effective bits (a SINAD of 89.1 dB) with anSFDR of 2100 dBc for a DC to 2.3 MHz band at 5.5 MS/s

The circuit consists of two major parts: a differential code, front end quantizer and a digitaldecimation low pass filter The front end is composed of an analog phase modulator and adigital phase demodulator The phase modulator consists of a single-junction SQUID, biased

by a DC voltage from a special voltage source, which is stabilized by an internal clockfrequency The phase demodulator consists of a time-interleaved bank of race arbiters(SYNC) followed by a thermometer to binary encoder (DEC)

In order to obtain a binary differential code from the thermometer code outputs of thesynchronizer bank, the encoder block adds up these outputs and subtracts N/2 each clockperiod The differential code from the output of the front end is passed to a digital decimationlow pass filter (DSP), which uses a standard cascaded integrator comb (CIC) architecture withtwo integration stages The first integration stage restores the signal from the differentialcode, and the second one provides first-order low pass filtering

The dynamic resolution, or effective number of bits (ENOB), of this ADC is determined bythe input signal bandwidth (BW), the internal clock frequency fclk, and the number of synchro-nizer channels N and is given [13] by

ENOB ¼ log2 ðNfclk=pBWÞ 1 1=2 log2ðfclk=2BWÞ ð1ÞThe first term in this formula accounts for a slew rate limit (i.e limited by the signalderivative), while the second one comes from standard oversampling gain Here, the BW

is assumed to be half the output sampling rate (i.e at the Nyquist limit) Therefore, (1) gives abandwidth-to-resolution trade-off ratio of 1.5 bits per octave, as expected for a first-orderoversampling ADC

5.2.3.2 Digital-to-Analog Converters

A number of different so-called ‘programmable Josephson voltage standards’ have beenproposed [14,15] Each of these designs consists of a superconductor digital-to-analogconverter (DAC) based on the properties of flux quantization When a quantized SFQ

pulse is used to represent digital data, the AC Josephson effect3(i.e frequency-to-voltagerelationship) gives access to a method for directly transferring back into the analog domain.The fact that a SFQ DAC uses the same fundamental physics that define the unit of the Volthas some profound consequences [16] For instance, any instantaneous voltage generated bythe DAC will be precise to the accuracy of the definition of the Volt Further, every waveformcycle generated will be exactly the same, with quantum precision The small time constantsassociated with Josephson junctions may make it possible to extend such performance tomany GHz, although very large arrays of JJs may be necessary to achieve useful levels ofoutput voltages suitable to drive high power amplifiers (HPAs).

An RSFQ DAC design based around a voltage multiplier (VM) block was first shown bySemenov [17] This DAC (seen in Figure 5.8) uses each bit of an N-bit RSFQ digital word todrive an RSFQ digital to frequency converter (DFC) (sometimes noted as ‘SD’)

A DFC is designed to output a stream of SFQ pulses at a frequency that is proportional toits reference clock frequency, only when the bit value at its input is ‘1’ By arranging a series

of N DFCs with reference frequencies fN that decrease as 22N, one can effectively create abinary weighted set By switching different DFCs in and out of the series with the digital inputword, any of 2Ncombinations can be chosen The VM is an inductively coupled SQUID chainused to transform the DFC streams of flux quanta into time-averaged voltages, then sum them,creating a corresponding output voltage with N-bit resolution By updating the N-bit inputword periodically, at a rate slower than the slowest DFC reference frequency, one creates aDAC The voltage at the output of the DAC during a single sampling period is given by Vout¼

MF0f0, where f0is a readout or sampling clock frequency, and M is the total number of SFQpulses driven through the VM by all the DFCs The LSB of the output voltage is nF0f0, where

3 When using fluxons, F 0 , as data bits, a time-averaged voltage measurement serves as a direct measurement of the bit rate according to the relation kVl ¼ F 0 /s, where the measurement accuracy is determined by the uncertainty limit

on the voltage measurement apparatus.

n is the number of stages in the smallest stage of the VM The output dynamic range is

2NLSB, where N is the resolution of the DAC in bits

Many bits of dynamic range are possible, because the initial reference clock can be veryhigh The chip in this figure is a 22-bit DAC Experimental results of an 8-bit design havebeen shown The differential nonlinearity (DNL) of the DAC is ,0.1 LSB With the propermicrowave engineering of the VMs, a multi-GHz output rate (effective bandwidth) could beachieved, while maintaining significant dynamic range The update clock and output clockare synchronized to prevent spikes during code transitions

5.2.4 RSFQ Scaling Theory

The basic scaling laws for Josephson junctions in RSFQ circuits are well known [18] Thejunction fabrication process defines the thickness of the tunneling barrier d ~ 1–2 nm, which

in turn determines the critical current density Jc, which is exponentially dependent on d Once

Jcis fixed, the primary constraint on the junction scale a is that the junction be large enough toavoid thermal fluctuations, typically with Ic 100 mA for Nb circuits For a large scale digitalintegrated circuit, this constraint assures that the bit error rate is sufficiently small

For RSFQ circuits, the high frequency performance is determined primarily by the width ofthe SFQ pulse generated by a nonhysteretic Josephson junction (RC , LJ/R) Because thetime-integral of the SFQ voltage pulse is F0 ¼ 2 mV-ps, the pulse height is roughly Vc<2IcR, and the pulsewidth is t < F0/2IcR [1] By decreasing the scale of a Nb junction, the pulsecan be made narrower until around a < 0.3 mm, where Vc< 4.8 mV andt < 0.4 ps Forjunction sizes a, above this limit, external shunt resistors are employed to ensure that (RC ,

LJ/R)

Although JJs are the central elements of RSFQ circuits, they are not the only elements.Equally important are inductors and resistors These can also be scaled down in size in aconsistent way [19] In this case, the speed of complex RSFQ circuits should scale with thereciprocal pulse width 1/t In particular, it is a rough rule of thumb that the maximum clockfrequency of a synchronous RSFQ circuit is approximately

Table 5.3 RSFQ scaling theorya