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Special cases of direct sampling are whenthe carrier signal frequency of the analog signal is 1/4 of the sampling rate, allowing for asimplified digital down-converter implementation [2]

Data Conversion in Software

Defined Radios

Brad Brannon, Chris Cloninger, Dimitrios Efstathiou,

Paul Hendriks, Zoran Zvonar

Analog Devices

Data converters are one of the key enabling technologies for the software defined radio(SDR) Regardless of the interpretation of the definitions – software radio, software definedradio, software based radios – the challenge of moving the analog-digital boundary closer tothe antenna is the critical step in establishing the foundation for increasing the content andcapability of digital signal processing (DSP) in the radio SDR technologies have providedthe incentives for the breakthrough in converter technologies pushing the state-of-the-art [1]

In this chapter we review the foundations and technologies of data conversion from theperspective of their usage in SDRs, exploring capabilities, constraints, and future potential

4.1 The Importance of Data Converters in Software Defined Radios

The use of converters in SDR depends upon the overall radio architecture A summary ofsampling techniques for the various receiver architectures described in Chapters 2 and 3 isgiven in Table 4.1

Table 4.1 Summary of sampling strategies for SDR receivers

Direct sampling (Nyquist sampling) satisfies the conditions of the sampling theorem forbandlimited analog signals, requiring that the sampling rate is at least two times the highestfrequency component of the analog signal In practical realization, direct sampling imple-mentation is closely coupled with anti-alias filtering realizations Oversampling of the signalusually eases requirements on the anti-alias filter Special cases of direct sampling are whenthe carrier signal frequency of the analog signal is 1/4 of the sampling rate, allowing for asimplified digital down-converter implementation [2].

In quadrature sampling the analog input signals are split into in-phase and quadraturecomponents, each occupying only half of the bandwidth of the original signals Quadraturesampling thus reduces the sampling rate by a factor of two, at the expense of needing twophase-locked analog-to-digital converters (ADC) instead of one [3]

Intermediate frequency (IF) sampling (or subsampling) of the bandpass signal requires thesampling frequency to be at least two times the bandwidth of the signal With this approach,the bandpass signal content is repeated at integer multiples of the sampling frequency and one

of the spectral replicas can be selected This operation also provides the down-conversion ofthe signal of interest

4.1.1 ADCs for SDR Base Stations

The realities of the wireless industry have moved the idea of SDR into new applications.Having in mind economics, with direct implication on size, power consumption and complex-ity, SDR concepts are finding initial acceptance and usage primarily in base station applica-tions Several variations on the SDR theme (or combinations of the solutions listed below)can be identified in current base station designs:

† Single carrier base stations with IF sampling and digital downconversion

† Multicarrier base station approach for a single standard The usual way is to providemulticarrier operation where the whole band of interest is sampled This approach elim-inates multiple radios (for different carriers) in favor of a single, high-performance, wide-band, radio per antenna, where each carrier is processed in the digital domain

† Multimode solution supports several radio standards, and SDR is the cost- effective way toestablish multimode solution This approach minimizes multiple radio functions (fordifferent standards) in favor of a multimode high performance radio per antenna Thesignal for each standard is processed in the digital domain This type of solution providesthe often necessary upgrade capability from legacy systems to new standards

† Reconfigurable base stations provide software and possibly hardware (programmablefilters, field programmable gate arrays (FPGAs), systolic arrays) reconfiguration based

on the air interface

In all cases, ADC is critical for the system operation Base station architectures may takeinto consideration either quadrature baseband sampling or IF sampling For a given frequencyband (dependant on the air interface) the analog front end can be optimized; it is, however,kept fixed, which is more cost effective today than having a frequency agile and bandwidthprogrammable front end SDR implementation The system clock is fixed, providing uniformsampling of the analog signal

The analog front end has a direct impact on the ADC dynamic range [4] Wideband IF

sampling front end linearity is critical for intermodulation generation, and selectivity issignificant for blocking attenuation Requirements of the given wireless air interface signifi-cantly impact ADC specification in terms of dynamic range and spurious free dynamic range(SFDR) Factors influencing the dynamic range of the converter in wireless systems includestatistical properties of the input signal, peak to average ratio, level of the interference,frequency of the interfering signal compared to aperture jitter, fading margin, etc [5] Selec-tion of the bandwidth to be digitized depends on the maximum sampling rate and dynamicrange of an ADC Approximately one bit of the resolution is lost for every doubling of thesampling rate [1].

Base station designs rely on best available converters in the class with highest resolutionand widest operating bandwidth Available state-of-the-art ADCs for wireless applicationsare 14-bit resolution devices operating in excess of 100 MHz, but there is an increaseddemand from base station manufacturers for 16-bit ADCs operating in excess of 120 MHz.These ADCs maintain 100 dB SFDR over the Nyquist band and a typical signal-to-noiseratio is 75 dB Fourteen-bit ADCs allow weak cellular handset signals to be demodulated inthe presence of strong ones These devices have low sampling jitter in order to allowdigitization of IF up to 250 MHz analog input Dither is used to improve ADCs’ SFDR

In principle, data converters with higher sampling frequencies can capture wider parts ofradio frequency (RF) spectrum Converters with higher bit resolutions can process higherdynamic ranges Unlike single carrier IF sampling solutions, it is much more difficult toplace the spurious content out of the band of interest in a multicarrier solution, because ofthe large number of carriers The aliased spurs of one carrier are likely to fold back on thesame carrier or another carrier This occurrence places a greater requirement on the SFDR

of the ADC than a single carrier does Thus, the SFDR is usually the limiting factor for awideband system

4.1.2 ADCs for SDR Handsets

Following the technological advances in key areas, including RF, converter technology, DSPtechnology, and programmable hardware approaches, SDR ideas are making their way interminal designs Having in mind the strict power limitation of handsets, different approacheshave been applied to the design of ADCs for such usage:

† bandpass sampling for single standard terminals

† reconfigurable converters reusing hardware blocks for multimode terminals

Dual band and tri-band phones for a single wireless standard already exist In the past onecould not find a strong argument to extend the wireless terminal into a fully SDR type devicesince the commercial mobile systems worldwide fall into a relatively small number offrequency bands and are primarily single mode However, the introduction of the thirdgeneration (3G) wireless standards are increasing the importance of multimode terminals.The focus of design will be on multimode radios with some sort of reconfigurable converterthat can provide performance/complexity trade-off

4.1.3 DACs for SDR Applications

While the SDR concept heavily focuses on ADC performance, transmit path requirements are

usually given less attention, although the problem is of comparable complexity [6] Highperformance digital-to-analog converters (DACs) are specifically used in the transmit (Tx)signal path to reconstruct one or more carriers that have been digitally modulated More of thesignal processing in these new generations of communication equipment is being performed

in the digital domain for multiple reasons (i.e higher spectral efficiency thus higher capacity,improved quality, added services, software programmable, lower power, etc.) Furthermore,many of these DSP functions are being integrated with the DAC itself to enhance its perfor-mance and to enable new transmitter architectures These DSP functions may range fromdigital interpolation filters, which reduce the complexity and cost of the required analogreconstruction filter, to complete application specific digital modulators for quadrature orspread spectrum modulation schemes

Synthesizing communication signals in the digital domain typically allows the istics of a signal to be precisely controlled However, in the reconstruction process of adigitally synthesized signal, it is the DAC and its nonideal characteristics which oftenyield unpredictable results In some cases, it is the performance of the DAC which actuallydetermines whether a particular modulation scheme or system architecture can meet thespecification Unlike high speed video DACs, the performance of DACs in wireless systems

character-is often analyzed in the frequency domain, with secondary consideration given to the timedomain and DC specifications Selecting the optimum DAC for a given wireless systemrequires an understanding of how to interpret various specifications and an appreciation oftheir effects on system performance Achieving the optimum performance while realizingother system objectives demands careful attention to various analog interface issues.Much design effort has gone into improving the frequency domain and static performance

of these devices while meeting other system objectives such as single supply operation, lowerpower consumption, lower costs, and ease of digital integration To that extent, severalsemiconductor vendors realizing the significance of the above stated objectives as well asindustry trends have elected to focus much of their effort on designing high -performanceDACs on a digital CMOS process State-of the-art DACs are 14-bit devices with SNR higherthan 80 dBc and sampling rate of 400 Msamples/s Third-order intermodulation distortion issmaller than 280 dBc up to 30 MHz output

Before addressing data converter performance issues in SDR applications, it is important todiscuss the most commonly used data converter architectures in order to understand theirpotential applicability to SDRs

4.2 Converter Architectures

Over the last 20 years there has been a tremendous amount of research and developmentinvestment to improve ADCs Although there are many converters on the market, most arebased on one of a few core architectures As new architectures evolve, there is a trend towardhigher integration, lower power, and increased performance It is essential to understand each

of these architectures so that the best converter can be selected for a given communicationssystem

4.2.1 Flash Converters

One of the first data converter architectures was the flash converter A flash or parallel

converter, as they are often called, consists of 2N2 1 comparators, where N is the number ofdigital output codes One input of all of the comparators is tied to the analog input via buffers,track-and-hold circuits, or other conditioning elements The other inputs are tied to successivesteps on a resistor ladder The top and bottom of the ladder are tied to reference voltages thatrepresent the input range of the flash.

Therefore, as the input voltage increases, each of the comparator outputs in the chainsequentially goes true, producing what is often called a ‘thermometer code’ Since the normaldesired output is binary, the thermometer code must be converted to binary through lookuptables and/or reduction logic

Flash converters have many benefits Because of the straightforward design, this ture offers extremely fast conversion times For low resolution applications, premium perfor-mance can be obtained at a minimum cost This has made flash converters attractive forapplications where dynamic range requirements are minimal

architec-The biggest drawback to this architecture is that as the number of bits increases, the size ofthe chip, costs, and complexity increase at an exponential rate of 2N Although not impossible

to design and build, in practice there are very few flash ADCs larger than 10 bits because ofthe relatively large die sizes Beyond this point they are too big and complex to manufactureefficiently, thus adversely impacting on cost To overcome the complexity problem, different

Figure 4.1 Typical flash ADC architecture

architectures have been developed which use fewer comparators such as in folded flash orpipelined architectures.

In addition, as the number of comparators increases, the reference voltages get smaller andsmaller As the reference voltage is reduced, the offset voltage of the comparator isapproached Once this happens, the linearity and overall performance of the converter iscompromised

Finally, as more comparators are connected to the analog input, the input capacitanceincreases With the increased capacitance, the effective signal bandwidth is reduced, defeat-ing the high speed benefit of the parallel converter

In addition to these impediments, there are several anomalies associated with the flasharchitecture The first is basic linearity The overall linearity of a flash converter is determined

by the linearity of the resistive ladder If not properly constructed, the differential nonlinearity(DNL) and integral nonlinearity (INL) requirements of the converter will not be met Addi-tionally, because comparators have input leakage currents, these additional currents in theladder can affect both the DNL and INL of even a perfectly constructed ladder As discussedlater, both of these converter parameters can adversely affect the performance of a receiver(Figure 4.1)

4.2.2 Multistage Converters

Another popular architecture used in high speed, high resolution ADC is the multistagearchitecture One of the key advantages of this architecture is its scalability The end resolu-tion can be manipulated easily by increasing and decreasing the bit precision of each stage.Obviously there are trade-offs in doing this, but conceptually it is possible to extend thisarchitecture up to 16 bits and beyond Because of the ability to construct high resolutionconverters, this is a popular architecture used in many SDR applications Shown in Figure 4.2

is an ADC suitable for SDR applications which uses three stages and has 14 total bits ofresolution

Multistage converters operate by the redigitization of residual signals The original analoginput is presented to the first track-and-hold (TH1) On the first positive clock edge this signal

is held This output is then presented to both the second track-and-hold (TH2) and the firstconversion stage For this example, the first conversion stage consists of a 5-bit ADC (ADC1)

Figure 4.2 Multistage subranging ADC

and a 5-bit DAC (DAC1) which requires 16 bits of precision TH2 remains in track mode untilthe falling edge of the clock This held signal is then subtracted from the DAC1 output Theresidual signal is then amplified (A2) and fed into TH3 The output of TH3 is digitized byanother conversion stage consisting of a 5-bit ADC (ADC2) and a 5-bit DAC (DAC2) DAC2requires 10 bits of precision so that it will not dominate the precision of the remainingconverter stages The output of the second conversion stage is then subtracted from the output

of TH4 and feeds the residual into TH5 The output of TH5 feeds the final 6-bit ADC (ADC3).The output of the three conversion stages is combined and digitally corrected to generate thefinal 14-bit output word It should be noted that the total number of bits involved is actually

16 The extra 2 bits (1 bit per error stage) are used to digitally correct for gain and offset errorswithin the chip

When comparing a multistage ADC with a single stage flash or pipeline ADC, manyadvantages exist The main advantage over CMOS pipeline architectures is that very highprecision can be achieved without the associated pipeline delays In the multistage architec-ture above, the output data represents the current analog input after four or fewer clock cycles

A similar precision pipeline ADC would take up to 10 clock cycles These delays constitutelatency, which can be important in many communications applications, especially those thatuse adaptive techniques in the digital signal processing

In comparison to single stage flash converters, much less die area is used because far fewercomparators are required This results in a smaller die with improved yield, lower power, andlower overall cost

Although a multistage ADC has many advantages, it does have some very challengingdesign requirements As mentioned above, this architecture places strict requirements on thefirst conversion stage DAC (DAC1) Because this DAC (DAC1) represents the reference forthe entire ADC, it must have a resolution greater than the overall number of bits for the entireADC With today’s technology, it is possible to achieve up to 16 bits of resolution for thistype of DAC

4.2.3 Sigma-Delta Converters

The sigma-delta (also known as delta-sigma) ADC is a highly innovative and relatively newidea in ADC technology In wireless applications the SD ADC can offer integration withother RF/IF functions to build highly optimized integrated circuit (IC) devices

As shown in Figure 4.3, the SD ADC consists of an analog filter, a quantizer (comparator),

a decimation digital filter circuit, and a DAC An n-bit comparator tells the output voltage in

Figure 4.3 Sigma-delta ADC

which direction to go, based upon what the input signal is doing It looks at the input andcompares it with its last sample to see if this new sample is bigger or smaller than the previousone If it is bigger, then it tells the output to keep increasing; if it is smaller, it tells the output

to stop increasing and start decreasing SD modulators work by sampling faster than theNyquist criterion and making the power spectral density of the noise nearly zero in a narrowband of signal frequencies (quantization noise shaping) Oversampling pushes out the noise,but it does so uniformly – that is, the spectrum is still flat [7]; noise shaping changes that.Noise shaping contours the quantization noise Conservation still holds, the total noise is thesame, but the amount of noise present in the signal band of interest is decreased whilesimultaneously increasing the out-of-band noise A series of decimation filters is used toremove any undesirable components (undesirable interferers and/or noise not sufficientlyfiltered in the analog domain) while simultaneously reducing the data rate in accordancewith the target signal’s bandwidth Depending on the modulation scheme, the complex datarate (hence decimation factor) is set to be at least a factor of two greater than the channelbandwidth, to allow for further postprocessing There is no one-to-one correspondencebetween input voltages and output codes, so in this respect SD ADCs are different fromNyquist rate converters Sigma-delta converters are characterized by their SNR; INL andDNL are not meaningful

SD modulators, regarding their front end analog signal frequency, are categorized either aslowpass or bandpass modulators A lowpass SD modulator encodes incoming analog signalsinto a digital sequence of ^1, which is then digitally lowpass filtered A bandpass modulatorconverts the analog input signal into a bit-stream The output is almost equal to the input inthe band of interest A digital filter removes the out-of-band noise and converts the signal tobaseband

The simplest form of an SD ADC uses first-order loop filtering and a single-bit comparator

In a second-order SD modulator, doubling the oversampling reduces the noise power by afactor of 32 and increases resolution at a rate of 2.5 bits per octave

To further increase the bandpass/lowpass signal resolution, higher order modulators can beused in an attempt to further improve the noise shaping An Lth order loop filter furtherimproves the signal to quantization noise in the bandpass/lowpass by improving the high -pass filtering of quantization noise (noise shaping) Stability is not a straightforward issue forhigher order loop filters (for L 2) and stable operation is usually possible only for limitedinput power SNR increases at L 1 0.5 bits/octave for an Lth–order noise transfer function(NTF) Stability is a worrisome problem for L 2, at least in single-bit modulators.The key factors in the development have been low cost and good linearity One of theadvantages of sigma-delta ADCs is that they do not require high precision and accuratelytrimmed analog components In fact, the circuitry of a sigma-delta ADC only requires theanalog components of a comparator and integrators As a result, sigma-delta ADCs can beimplemented with low cost CMOS circuitry using switched capacitor circuits

Due to their noise shaping behavior, sigma-delta modulators offer an attractive approach torealizing high performance analog-to-digital conversion without relying on the use of highprecision and accurately trimmed analog components In addition, oversampling generallyhas two advantages First, the specification of the analog anti-alias filter is reduced from theNyquist specification (i.e the sharp cut-off analog filters required with Nyquist DSP systemscan be replaced with slow roll-off RC circuits) Second, the n-bit resolution obtained fromADC can be increased to n 1 1 bits by oversampling the signal by a nominal factor of 4 and

subsequently digitally lowpass filtering to the Nyquist rate [8] The lowpass filtering canrequire a number of stages of comb filters and multibit finite impulse response (FIR) filters,and is actually an expensive requirement (in digital circuitry terms) The trade-off when usingsigma-delta ADC devices is an increase in the digital processing requirements against areduction in the provision of accurately trimmed analog components and complexity.Sigma-delta ADCs are well suited for use in SDR, either for direct sampling or forbandpass sampling By employing a bandpass loop filter and feedback around a coarsequantizer, bandpass modulators shape quantization noise away from narrowband signalscentered at intermediate frequencies This approach, first successfully integrated in [9],eliminates the need for dual in-phase/quadrature-phase analog mixers and the separate lowpass ADC converters generally used for each quadrature channel Instead, demodulation isnow moved into the digital domain, thereby eliminating the problem of channel mismatch[10] Furthermore, since the conversion is performed directly on the IF signal before mixing

to baseband, the modulator does not suffer the effects of DC offset and low frequency noiseproblems

4.2.4 Digital-to-Analog Converters

Most high speed CMOS DACs (including bipolar and BiCMOS) employ an architecturebased on current segmentation and edge-triggered input data latches to achieve the desirablecode independent settling and glitch impulse characteristics that are necessary to maintainlow distortion Figure 4.4 shows a typical segmentation architecture common among manyCMOS DACs Typically, the upper 4 or 5 binary-weighted bits (MSBs) are implemented asthermometer decoded, identical current sources and switches To optimize DC linearityperformance, each of these identical current sources may consist of an array of unit currentsources The middle binary-weighted bits (LSBs) are implemented using a similar current

Figure 4.4 Example of a segmented current source architecture used for a 14-bit CMOS DAC

segmentation based on these unit current sources The remaining LSBs consist of binaryweighted current sources.

Each of the weighted current sources can be switched either directly or indirectly into one

of two output nodes using high speed, differential current switches as shown in Figure 4.5.The current sources and differential switches are fabricated with PMOS devices, allowing forboth single supply operation and a ground-referenced load These current sources are regu-lated by an internal control amplifier and may be isolated from the differential currentswitches via a cascode device to obtain higher output impedance An external resistor, incombination with both the control amplifier and voltage reference, sets a reference currentwhich is mirrored over to the segmented current sources with the proper scaling factor Thesum of all the currents corresponds to the DAC full scale current, IOUTFS The IOUTFSof manyCMOS DACs may be varied over a 20 dB range (i.e 2–20 mA) for low power operation oranalog gain control

The amount of current appearing at each of the two single ended, complementary currentoutputs, IOUTA and IOUB, is some fraction of the full scale current, IOUTFS, determined bythe digital input code held within the DAC’s internal data register A digital input code of all

‘0’s produces 0 mA of current at IOUTA, while a code of all ‘1’s produces the full scalecurrent of IOUTFS(minus an LSB) IOUTB, being the complement of IOUTA, has the inverserelationship such that the sum of these two currents will always provide a constant currentoutput whose value is equal to IOUTFS (minus an LSB) Note, the difference betweenIOUTA and IOUTB also provides a desirable code dependent fraction of IOUTFSprovidingtwice the signal current, and offering several advantages to be discussed shortly The twocurrent outputs can easily be converted to two single ended or one differential voltage output

by using resistive loads, a transformer, or an op amp

Beyond this common architectural approach lie various differences in the actual mentation, affecting a high speed DAC performance and system requirements For exam-ple, to improve upon their DC linearity performance, many 12- and 14-bit CMOS DACsuse some form of factory calibration technique A typical calibration procedure attempts

imple-to trim the current sources of the MSB segmentation imple-to equal each other, and the sum of

Figure 4.5 Differential switches steer current into one of two output nodes allowing for differential orsingle-ended operation

the remaining current sources (associated with the middle bit segmentation and ing LSBs) to have equal weight as an MSB current source The driver circuitry asso-ciated with each of the differential current switches has a significant impact on ACperformance and often is based on proprietary circuit techniques The objective is toachieve fast, symmetrical switching characteristics with minimum time skew between thedifferential current switches in order to reduce any code vdependent settling time depen-dencies.

remain-4.3 Converter Performance Impact on SDR

In this section the major behavioral characteristics of data converters are summarized,emphasizing their impact on SDR performance, primarily in terms of noise and spuriousgeneration

4.3.1 Noise Sources – Impact on SDR Sensitivity

Noise within a wireless receiver can come from many sources; SDRs are no different Aswith a traditional radio architecture, there are contributions from passive and activeelements such as filters, amplifiers, mixers, and data converters.1 However, unlike thenoise from active and passive elements, the noise within data converters is not alwaysthermal in nature Of course data converters do have thermal noise, which is often asignificant portion of the overall noise In addition to thermal noise, however, convertersalso exhibit noise from quantization (digitization), DNL errors (nonideal quantization),clock jitter, and numerous other sources [11]

4.3.1.1 Quantization Noise

Quantization is the process that a data converter goes through in the digitization of the analoginput Numerically, the process is similar to the process of converting real numbers into eitherinteger notation or fixed precision notation In theory, quantization of an analog input willresult in 2N output levels for the full analog range of the converter In this case, N is thenumber of physical bits that the converter represents

For a flash ADC with linear quantization, input signal with a Gaussian distribution of theamplitude with zero mean and variancesand oversampling ratio OSR, the signal to quanti-zation noise is given by [4]

SNRQ¼ 6:02N 1 10:8 1 10logOSR 1 20log s

Vppwhere Vppis the maximum amplitude range, peak-to-peak voltage The SNR due to quantiza-tion increases by 6.02 dB with every additional bit of resolution and increases by 3 dB with adoubling of the oversampling ratio

For sigma-delta converters, quantization noise analysis is different due to noise shaping.For an Lth order modulator with sinusoidal noise shaping the signal to quantization noise is

1

See Chapter 2 for a more detailed discussion of noise performance design of SDR front ends.

addi-4.3.1.2 Differential Nonlinearity

In practice, quantization levels are never perfect Therefore, differential nonlinearity, orDNL, is the step-by-step variation in quantization or converter step size Traditionally,DNL has been associated with the static or DC performance of a converter However,DNL does affect the noise performance of the converter by increasing the noise level ofthe converter at all frequencies

While the data sheets for most converters do specify the worst DNL errors, they fail toindicate the total noise caused by the sum of all of the DNL errors It is possible to infer thisinformation based on SNR results given in the absence of thermal noise

Because of generally good design practices, most converters have only limited mance reduction due to DNL errors Since DNL errors are ‘local’, as long as the analog input

perfor-to a converter is a large percentage of full scale, errors of one step will make a smallcontribution to overall performance However, as the signal level becomes small relative

to the full scale of the converter, DNL errors can become large with respect to the inputsignal Since most receivers (and transmitters) are AC coupled, small signal performancecenters on the midscale of the converter Therefore, it is very important that DNL at themidpoint of the converter should be very good Codes that deviate from normal size canincrease overall noise and reduce the sensitivity of the receiver In addition to reduced noiseperformance, DNL errors at midscale can cause apparent gain errors to occur, possiblycausing improper power estimation of the desired signal (Figure 4.6)

Figure 4.6 ADC DNL error and associated gain errors

4.3.1.3 Thermal Noise

Another source of noise considered is thermal noise Thermal noise is related to the designand process on which the converter is manufactured Thermal noise can be computed usingthe following equation:

en ¼ ffiffiffiffiffiffiffi4kTRp

where k is Boltzmann’s Constant, 1.38 £ 10223 J/K, T is temperature in Kelvin, and R isresistance in Ohms For each data converter, the associated thermal noise is therefore depen-dant on the design of the converter and the process on which it is manufactured and istherefore fundamentally limited by the device physics of that device An example of thiswould be a bipolar ADC design With this type of process, the thermal noise is related to theparasitic resistance associated with the bipolar transistors within the ADC Specifically it isthe base to emitter resistance (rb) of these transistors which dominates the overall thermalnoise performance

4.3.1.4 Jitter

The final contributor to dynamic specification that is vital to radio performance is ADCaperture jitter Aperture jitter is the sample to sample variations in the clock source Clockpath jitter includes both internal and external jitter sources anywhere between the clocksource and the actual sampling mechanism within the data converter Although low jitter

is important for baseband performance, its effect is magnified when sampling higher analogfrequency signals (higher slew rate) such as those found in undersampling applications Theoverall effect of a poor jitter specification is an increase in the converter noise level as inputfrequencies increase The terms ‘aperture jitter’ and ‘aperture uncertainty’ are frequentlyinterchanged in texts; here they are used with the same meaning (Figure 4.7)

In a sinewave, the maximum slew rate is at the zero crossing At this point, the slew rate isdefined by the first derivative of the sine function evaluated at t ¼ 0:

vðtÞ ¼ Asinð2pftÞd

dtvðtÞ ¼ A2pf cosð2pftÞWhen evaluated at t ¼ 0 the equation simplifies to:

d

dtvðtÞ ¼ A2pfand yields how fast the signal is slewing through the zero crossing of the input signal Theunits of slew rate are volts per second In a sampling system, a reference clock is used tosample the input signal If the sample clock has aperture uncertainty, then an error voltage isgenerated This error voltage can be determined by multiplying the input slew rate by the

‘jitter’ [12]

verror¼ slew rate £ tjitter

By analyzing the units, it can be seen that this yields a unit of volts Usually, apertureuncertainty is expressed in seconds rms, and, therefore, the error voltage would be in volts