Tài liệu Phần mềm xác định radio P7 pdf

Alongside networking of these enhanced capability and flexible systems, theradio frequency processing aspects of the physical layer are required to accommodate aflexible range of differe

Baseband Processing for SDR

David Lunda and Bahram Honaryb

a

HW Communications Ltd.

b

Lancaster University

Many technologies require substantial research and development to facilitate the emergence

of mature and generic software defined radio architectures, as will be evident from a perusal

of the contents of this volume or the other literature in the field Our own chapter focuses uponthe broad ranging topic of baseband processing, an important and central element of sucharchitectures Alongside networking of these enhanced capability and flexible systems, theradio frequency processing aspects of the physical layer are required to accommodate aflexible range of different frequencies, formats, and environments Baseband processing isperhaps one of the most potentially fruitful areas of development anticipated over the nextfew years – indeed, significant progress is already evident

7.1 The Role of Baseband Architectures

The baseband of any radio system is responsible for digitally transforming raw data streamsinto the correct format ready for transmission over a known wireless channel In a transmitterthis simply consists of formatting of the data and introduction of any redundancy required toimprove reception At the receiver, the information from the radio frequency front end has to

be carefully analyzed in order to extract correctly the data which was intended for reception.This requires synchronization, demodulation, channel equalization, channel decoding, andmultiple access channel extraction These, and many more functions, are linked together toform a chain of processing functions, providing a pipeline through which the data and itsassociated overhead are passed

The architecture of this baseband processing chain is structured to reflect the type ofwireless channel and other supporting functions over which data is to be transmitted Differ-ent modulation, channel coding schemes are chosen to maximize throughput over the parti-cular channel, which itself may be influenced by the application (e.g required data rate).Multiple access methods are chosen to maximize the number of transmitters which caneffectively and simultaneously share the spectrum Support functions such as synchroniza-tion, equalization, and spatial diversity algorithms all enhance the basic transmission format

Edited by Walter Tuttlebee Copyright q 2002 John Wiley & Sons, Ltd ISBNs: 0-470-84318-7 (Hardback); 0-470-84600-3 (Electronic)

at the expense of extra processing and power consumption, the latter being particularlyimportant within the context of portable devices.

The majority of today’s air interfaces are subject to a standardized specification whichstrictly defines the transmission formatting for a particular system For example, GSM,UTRA, and IS-95 specify just a few of the individual formats for mobile wireless telecom-munication systems Digital audio broadcasting (DAB) and DVB-T specify formats forterrestrial broadcasting systems and DVB-S for satellite broadcasting Many others definehigh bit rate wireless systems for short range networking, fixed wireless access, and otherapplications A software defined radio may be designed to tranceive using a variety of suchavailable standards It may even participate ad hoc, as and when bandwidth may be available.Any of the standard transmission formats may be chosen which may provide the necessarylevel of service as the users’ application requires

Research in SDR commonly takes a top down approach Evaluation of the market looks atwhat the user requires in terms of application Network developers look at how to providesuch applications and services to the user Equipment developers develop and use compo-nents to build the infrastructure needed to implement the networks and terminals

Equipment developers will frequently take predominantly off-the-shelf component nologies and, maybe after some specific modification, integrate them into infrastructureequipment This is certainly how second-generation mobile equipment has been developed,with GSM terminals commonly containing hybrid application specific integrated circuit(ASIC) devices based upon a particular microprocessor (mP) or digital signal processor(DSP) core

tech-New component technologies are rapidly emerging which complement the now traditional

mP and DSP technologies Field programmable gate array (FPGA) and new reconfigurablefabric processors give an alternative edge to the use of aging mP and DSP technologies.The remainder of this chapter describes a range of technologies and techniques presentlyavailable for implementation of the baseband processing subsystem The concept of flexibleprocessing is introduced to describe the higher level problems associated with using suchtechnology The status of currently available component technologies is described, illustrat-ing the wide range of processing resource already available today These are presented todevelopers of SDR-based equipment, providing insights into how they may be used fordifferent algorithmic purpose

The introduction of new processing technologies also requires development of new designtools and methods The status of such tools is also described with discussion of requirementsnot only for initial design of an SDR system but also its maintenance A discussion of object-oriented methods illustrates how the high level software developer may be given the neces-sary visibility and understanding of the processing resources available With such visibility,SDR operators and maintainers can then allocate the necessary time critical baseband proces-sing chains to a multitude of processing resources with maximum efficiency

7.2 Software Radio – From Silicon to Software

It is important here to recognize the context within which, for the purposes of this chapter, weuse the term ‘software’ and the consequent breadth of the requirement The CambridgeInternational Dictionary of English gives the following simple definition:

Software – ‘the instructions which control what a computer does’

So, for an easy method of translation to the context of software radio systems, which issimply a new advanced method of communication, we could replace the term ‘computer’with the term ‘communication system’ to get:

Software – ‘the instructions which control what a communication system does’

The computer is a relatively simple system which is controlled by relatively simple ware It is clear to see that software in the context of SDR is much more elaborate and can infact be considered to be two-tiered Software (tier 1) is required to define the computation andsoftware (tier 2) is required to control the mode of operation of this computation within thecommunication system.1

soft-Much research is today being carried out in order to determine the best methods toarchitecturally define software radio with its associated reconfigurable systems andnetworks.2Issues such as quality of service, value added service provision, and the hugetask of managing all of this are being defined and will require substantial advances inimplementation level technology to automate these aspects

Quality of service (QoS) guarantees are becoming more and more an important ality for the future of mobile telephony and data transfer services QoS applies a policy to acommunication service to which the system must adhere For example, the resource reserva-tion protocol (RSVP) service is such a method for providing a level of QoS in fixed networkapplications A data transfer session begins by reserving bandwidth through a network or theInternet A route of fixed bandwidth is reserved from the data source to its destination bynegotiating with routers along the way Once the bandwidth is reserved, the data transmissioncan take place with a guaranteed pipeline of fixed bandwidth The application transferring thedata can then guarantee the quality of service supplied to the user QoS is a topic originallypioneered by researchers in computer-based fixed networks As third-generation mobilenetworks are developing, the concept of QoS is emerging as an important requirement forprovision of a wide range of high quality data services to the mobile user

function-Network management is also a hot topic in the quest for improving the mobile and Internetexperience Providing efficiency in the system along with network management allows easydeployment and control of systems and hence efficient service to the user Second-generationmobile networks consist of mobile terminals, base stations, and switching centers Third-generation networks provide much more functionality in order to improve user services.Various domains and strata providing different levels of data access and control are defined,allowing the capability to provide advanced, user specific services across a broad range ofenvironments and across multiple networks [1] Network management of these, alreadymultimode, systems is proving to be a huge task The concept of software radio and theadvent of reconfigurable processing systems makes the organization and management of thenetwork even more complex, as the majority of functionality in the network becomes capable

of being modified with only the actual hardware architecture remaining static

The CAST3project illustrates the need for advanced management methods by focusing on

the use of organic intelligence to cope with the enormous range of situations and scenarioswhich have to be managed Figure 7.1 illustrates how an architecture based on organicintelligence can be used to manage the multitude of reconfigurable elements in a network[6,17,38].

Other approaches to the problem use traditional procedural approaches whereby a fixed set

of rules governs the management operation depending upon the status of the system Itbecomes quite clear when reviewing the different proposed systems that a combination ofintelligence and procedural rules is essential to cope with the immense multitude of operatingscenarios which are available

Overall, the high level visionary architectures of reconfigurable mobile networks place ahuge demand on the technologies which have the responsibility of processing all of this.Combined with greedy demand for data bandwidth and strict QoS restrictions the resultantdemands placed on silicon processing technologies are seen to be growing in an unprece-dented manner

There are two demands made by such systems which quite simply describe the majordevelopments required of the physical processing technology, namely demands for:

† increased processing capability

† increased dynamic capability

These are not, however, just tasks for the silicon engineering industry

Today’s complex semiconductor devices require powerful tools to aid designers in usingthe technology quickly and efficiently The days of Karnaugh maps for logic minimization arenow far in the distant past Modern processing technologies exceed tens of millions of logicgates Manual design, even on circuits which are today considered simple, is impossible.Increasing the dynamic capability of a system not only increases its range of operation, butalso increases its lifetime, extending the system maintenance requirements

To summarize, three major areas of advance are required in order to provide the dynamicprocessing capabilities essential to support future reconfigurable communication systems Anumber of key challenges and questions arise in each of these areas, summarized below It is

the lack of a single simple criterion which restricts evaluation of the many innovative natives proposed today as possible baseband technology solutions.

alter-1 Baseband component technologies

– dynamic capability – how flexible are different processing devices?

– processing capability – how powerful are different processing devices?

– physical constraints – what are their physical limitations?

2 Design tools and methods

– standardized tools and methods – global compatibility and coherence

– specification tools and methods – transferral of design information

– mixed mode capability – mixed component technologies imply the need for mixed toolenvironments

– tool processing requirements – can a highly complex system be simulated?

– compliance to design procedures – design flows for different technologies and nations

combi-– algorithm processing requirements – to provide enhanced automated design decisions.– automated hardware selection for algorithms – also for automated design decisions.– system simulation and emulation – testing methods at different levels

– initial set up and configuration – how is a system initialized?

– automatic intelligent decisions – higher capability requires more complex decisions.– capability classification – knowledge of the processing system is required for in-systemdecision making

– resource allocation – efficiently allocating functions to processing resources

– configuration update procedures – methods of securely controlling and updating mically distributed systems

dyna-It is evident that the advances in silicon technology today are outstanding and provide hugecapabilities However, in order to use these technologies efficiently, more development isrequired in order to support the silicon From the component technologies viewpoint, theevolution of the personal computer has reflected advancement in microprocessor and RAMtechnologies Support and drive has also however been required from providers of operatingsystems, development tools and system maintenance As with the PC, provision of genericreconfigurable systems will not just rely on a small number of technologies Different silicondevices are now essential to provide high capacity dynamic processing It is shown later howsome of these essential new silicon technologies presently lack the required support fromdevelopment tools and maintenance Figure 7.2 illustrates the wider context of the realenabling technology required for software radio

Existing methods of using software to define the function of a processing system are welldefined when using microprocessor-based resources Application and service developers are

able to use this resource, without knowledge of its existence, to provide high quality andefficient desktop based data services such as real time video, radio, and many more Muchdevelopment is required in order to support the increased range of processing media avail-able Software radio systems depend wholeheartedly upon this new multitude of processingresource Allowing the application and service providers transparent access to this newlydefined resource will require substantial development in all three areas described above.The subsequent sections of this chapter are devoted to an examination of the current status

of component technologies, design tools and methodologies, and system design and tenance

main-7.3 Baseband Component Technologies

Until relatively recently, the majority of software radio research had focused mainly on theuse of software and digital signal processors [12] Arguably, this is the simplest technology toimplement, but performance of a system consisting of processor and software only is not yetpowerful enough for the high data rate requirements of systems targetted for third-generation(3G) mobile communications Several recent papers have described the application of FPGAs

in software radio [2,9,10], but few have attempted to tackle the issues relating to the uration and reconfiguration during an online service transmission

config-No single silicon technology is more important than another when it comes to the design ofefficient processing systems Each processing algorithm has a different combination and set

of discrete operations The combination of logic operations, adds, subtracts, multiplies,divides and condition operations is different for each algorithm The first digital signalprocessors (DSP) were optimized mainly for the huge demand of pipelined multiply accu-mulate (MAC) operations which form the basis of most discrete signal processing algorithms

Figure 7.3 illustrates how the FPGA can provide a solution for systems requiring both highperformance and a high degree of function capability At one extreme, hardwired devices,such as an ASIC, can only perform a limited function; they do, however, provide a very highperformance The DSP, being software programmable, can offer an almost unlimited functioncapability, but, of course, the serial processing nature of traditional DSPs does limit perfor-mance.

Figure 7.4 illustrates how the FPGAs processing resource is able to provide this nation of high function with high dynamic capability Any processing algorithm can bedecomposed into subelements which incrementally carry out the computation required bythe algorithm Each of these subelements has dependencies upon the data available as a

combi-result of other subelements’ processing In Figure 7.4, subelement 2 is dependant upon 1and subelement 4 is dependant upon 3 Subelement 5 is dependant upon the result of 2 and

4 A single mP or DSP software based computation of the algorithm must process each element sequentially, satisfying the dependencies, i.e 1 ) 2 ) 3 ) 4 ) 5 or 3 ) 4 ) 1 )

sub-2 ) 5 Improved performance may be gained by using multiple processors to compute 1 )

2 and 3 ) 4 in parallel Multiple processors do, however, result in higher power tion and the requirement for more silicon area The FPGA processing resource is finegrained and can carry out this parallelism to a degree as small as individual logic gateoperations

consump-An important trade-off here is ease of implementation vs performance consump-An FPGA circuitwith currently available design tools is more difficult to configure than the well-establishedprogramming methods of the DSP A small price is also paid in time when reconfiguring.Reconfiguring FPGA logic is much slower than a simple function call in the mP or DSP.The DSP and FPGA devices showcased in the following sections are chosen in order toillustrate the types of processing resources available Although the majority of these devicesare currently large and power hungry, it is their function that is important in order to drawconclusions upon which available resources will be required for reconfigurable communica-tion systems It is the plethora of processing methods used within these current devices which

Figure 7.3 Current enabling technologies for digital processing

is the important consideration today Once the best methods or processing are known, futuresilicon, or other fundamental technologies, will be implemented and used efficiently astargeted to the reconfigurable processing or SDR system.

7.3.1 Digital Signal Processors

The digital signal processor (DSP)4was first introduced in the early 1980s in order to provide

a processing machine optimized for interpreting, manipulating, or even generating discretesignals in the time or frequency domain DSPs provided a method which revolutionized theway in which real physical information is processed The flexibility, accuracy, and reprodu-cibility of analog components was relatively limited and, hence, superseded by the solidlydefined program of the DSP Dynamic range is a problem associated with analog circuitry;this constraint is still present in the vital analog to digital conversion process (ADC) encoun-tered prior to the DSP

The DSP is in essence simply an optimization of the general purpose microprocessor(mP) On a simple mP only basic functions such as memory load, memory store, add/subtract, and logic operations were initially available The DSP’s key innovation whichoptimized its architecture for analog signal manipulation was the inclusion of the multiplyaccumulate (MAC) operation Algorithms for manipulating signals are often based upon themethod of convolution Convolution allows the set of discrete samples to be treated in anequivalent manner to the represented continuous signal Convolution-based algorithmsallow signals to be combined, filtered, and transformed, allowing operations to be imple-mented fully equivalent to the analog case The MAC operation is optimized for execution

in a single DSP clock cycle; indeed, high performance DSPs may even support two or moreMACs per clock cycle

Addressing modes are also optimized in DSP architectures, allowing efficient loading and

4 The newsgroup comp.dsp provides a thorough working analysis of DSPs from which some of this historical and tutorial material is sourced.

storage of discrete data to and from memory circuits Data access is also improved by usingHarvard architectures to allow the DSP to access both data and instructions simultaneously.Functions such as pre/post addressing registers (pointers) store addresses of locations ofdiscrete data They often also incorporate their own arithmetic function to allow for fastupdate of the pointer to quickly address the next required data element Circular addressing isalso common, allowing a pointer to rotate around a defined area of memory to provide acycle-based memory access Along with the MAC, the DSP may also provide execution

(MHz)

Instruments

consumption 0.05 mW/MIPS

and image parallelprocessing

2 BOPS(RISC)

parallel pProcessors

1 32 bit RISC processor

control for fast instruction looping and caching architectures to speed up memory accesstimes Two distinct classes of DSP have emerged – fixed and floating point devices areavailable with a large variety of arithmetic precision.

Nowadays, when considering the DSP devices offered by the different silicon vendors, adistinct focus may be seen on specific market areas based on a core architecture The coreCPU is optimized for either performance or power consumption and then provided with thesupport functions required to address specific markets These core architectures are alsooffered as general purpose devices in their own right

Table 7.1 provides a sufficient summary of offerings from the main providers of DSPsilicon, summarizing their performance and application focus

Performance in Table 7.1 is expressed in line with the manufacturers’ advertised tions, reflecting different approaches in common usage The following defines these whichmany have only subtle differences:

specifica-† MIPS, million instructions per second The maximum number of instructions carried outper second;

† MMAC, million MAC operations per second The maximum number of MAC instructionscarried out per second;

† MFLOP, million floating point operations per second The maximum number of floatingpoint operations carried out per second;

† BOPS, billion operations per second The maximum number of operations carried out persecond

The major difference between operations and instructions depends on the complexity of theinstruction set and the device capability; for example, a particular DSP may be able to carryout more than one operation per instruction

DSP optimizations generally target three major issues:

† control capability – low end devices take advantage of spare silicon area to add extra I/Oand memory resources for use in applications which require the control of physical inter-faces in the context of the user;

† power consumption – to allow usage in an increasing range of portable battery-poweredconsumer (and other) devices;

† performance range – providing ranges of processing performance with differing MIPS andMFLOPS to provide the best cost vs performance trade-off for specific processing require-ments

7.3.2 Field Programmable Gate Arrays

The field programmable gate array (FPGA) was first introduced by Xilinx Inc in 1985 [42].Since then the technology has been enhanced and developed with relatively little interest inits dynamic capability The major application of FPGAs has traditionally been as a low costalternative to the design of application specific integrated circuits (ASIC), particularly for lowvolume applications A brief history and a description of many applications of the devices can

be found in [14]

At present there are many different vendors who provide FPGA devices, hybrid variations,and tools, including those listed below Some of these suppliers represent long established

companies, while others are relative newcomers and start-ups who have sought to bringinnovative technology approaches Many of these already go beyond the limitations oftraditional FPGAs, DSPs, and/or ASICs, specifically to address the emerging softwareradio market opportunity.

A typical FPGA device consists of an array of configurable logic blocks (CLBs) surrounded

by configurable routing Each logic block consists of resources which can be configured todefine discrete logic, registers, mathematical functions, and even random access memory(RAM) A periphery of configurable pads provides connection to other electronic devices.Figure 7.5 illustrates the classic FPGA architecture

The function of all of these configurable resources can be defined at any time during theoperation of the device to form a large logic circuit Configurable logic and routing can beformed together to provide the exact function of a digital processing algorithm Parallel andpipelined data flows are possible, providing an excellent resource for execution of the signalprocessing algorithm The number of configurable gates in such devices has already exceeded

10 million and recent developments have shown that these FPGAs can house most of thebaseband processing required for a 3G system.

New methods of configuration are also being added to these devices to allow fast andsecure download of configuration data to the devices This is an important consideration whendesigning for uninterrupted transmission Partial reconfiguration is another importantenhancement to FPGAs; sections of the FPGA logic can be reconfigured without interruptingany processing being simultaneously carried out in other parts of the same device

When considering the typical FPGA as a processing resource, the important issues toconsider are the CLB architecture, the RAM architecture, the I/O signalling and the clock

Of these, the capabilities of the CLBs are most important as they define the majority of theFPGA processing resource

CLBs are termed as either ‘fine-’ or ‘coarse-grained’ architectures Course-graineddescribes large CLBs which are optimized with particular features such as dedicatedRAM or arithmetic logic, while fine-grained CLBs provide small simple logic functionality.Coarse-grained architectures provide higher processing speeds due to the specific optimizedsilicon circuitry and minimal routing requirements between them Fine-grained architec-tures, although still relatively fast, pay the performance price arising from the extra routingrequired to interconnect them The trade-off for performance is, of course, flexibility Fine-grained architectures are more flexible than coarse-grained due to the greater possibilitiesprovided by a high quantity of simple logic Coarse-grained, however, are limited to thespecific optimized functions To illustrate in more detail the features of the fine- and coarse-grained FPGA architectures, we describe the Xilinx Virtex and Altera APEX devicefamilies

7.3.2.1 The Xilinx Virtex Architecture

The Xilinx Virtex architecture [42] follows the classic FPGA architecture as illustrated inFigure 7.5 but features several coarse-grained enhancements The architecture consists of astandard array of CLBs with a partial border of block RAMS (BRAMs) The periphery of thechip consists of configurable I/O blocks (IOBs), which are capable of interfacing to theoutside world via a multitude of voltages and signalling schemes The delay locked loop(DLL), as supplied by most modern FPGAs, provides correction of clock skew on and offchip, ensuring that all logic is correctly synchronized The most interesting part of the VirtexFPGA is its extremely versatile CLB architecture

The Virtex CLB is split into two halves (slices) Each slice has two distinct data paths, eachcomprising:

† a look up table (LUT), which can perform (at least) three possible functions

– 4 input, 1 output look up table, for definition of logic functions

– 16 deep by 1-bit wide RAM or ROM

– 16-bit shift register

† control, which can be used for

– combining both LUTs to create larger logic functions

– combining both LUTs to provide larger RAMs or a dual port capability

– arithmetic support for high speed multipliers

– carry control for adders/subtractors

– route through for more flexible routing

† Configurable storage element, which can support:

– either flip-flop or latch clocking mode

– rising or falling edge clock

– clock enable

– either polarity asynchronous reset

Although sizable RAM may be simply constructed from the several CLBs, the BRAMsprovide a large resource for storage of application data Each BRAM can store 4 kbits ofdata with dual port access Each port has address and data dimensions which are configurable,allowing almost any combination of data width and address depth for access to the storage.The Virtex can be configured [44] by a stream of binary configuration data A dedicatedport can be used to access configuration hardware either serially or in parallel Both write andread operations can be performed on the configuration data via command-based control Theconfiguration mechanism allows either full or partial reconfiguration of the FPGA resources.The Virtex series of FPGA is now also being offered in different forms with emphasis ondifferent functionality, system voltage, and price range The Virtex-E device, for example,employs a smaller silicon geometry allowing lower system voltages Its architecture differsmostly in the CLB array Instead of having BRAMs on the periphery of the CLB array, moreBRAM resource is offered by interlacing BRAM columns with CLB columns in the body ofthe device This provides extra RAM resource while reducing the access delay The Virtex-

EM has even more BRAM facility, offering a maximum of approximately 1 megabit ofBRAM on-chip storage

7.3.2.2 Altera APEX

The main architecture of the APEX [3] is also based on the standard CLB array architecture

as described above In this case, each CLB consists of three separate blocks:

† a look up table (LUT)

† product term (P-term)

† data storage (memory)

In addition, the APEX also includes coarse-grained embedded system blocks (ESD) uted across the array of CLBs Each ESD can assume three different configurations:

distrib-† product term

† dual port RAM

† content addressable random access memory (CAM)

Clock distribution is achieved by use of phase locked loops which can distribute clocks andtheir multiples with minimal skew The device supports most recognized I/O and interfacingstandards The maximum equivalent gate count of the APEX at this time is 2.5 million with amaximum of 432 kbits of on-chip RAM Configuration is achieved serially and only config-uration of the full device is possible

7.3.3 Recent Digital Developments

The advent of field programmable technology, coupled with the drive to provide solutions forthe third-generation mobile, has recently sparked an interest in providing ASICs with eithermore specific functionality or a greater variation in available resources

Motorola, Analog Devices, Texas Instruments, and various others provide their DSP coreswith other silicon intellectual property (IP) for specific communication solutions At this timethere is a major focus on providing solutions for asynchronous digital subscriber line (ADSL)modems and other remote access (RAS) devices

Some specific solutions provide so-called ‘communications processors’ These devicessplit the ASIC or chipset architecture into the OSI layers and provide a range of service ateach layer This architecture provides the signal chain of processing required for the structure

of baseband processing as described by [27] The following examples illustrate a convergencebetween devices of fine- and coarse-grained FPGA resource, and silicon IP cores

7.3.3.1 Quicklogic

Quicklogic provides a range of devices which allows combinations of different processingresources dependant upon the requirements of the processing application The concept of

‘embedded standard products (ESP)’ describes how different IP processing functionality can

be brought together on a single IC

Four distinct types of resource are provided:

† data I/O – low voltage differential signaling (LVDS), PCI, fiber channel

† array of logic cells (LC) – the Quicklogic version of fine-grained CLB

† dual port RAMs (DPRAM) – providing dedicated coarse-grained memory resource

† embedded computation units (ECU) – dedicated coarse-grained arithmetic processing,including multiply accumulate (MAC)

Ranges of devices provide different quantities of each resource

7.3.3.2 Chameleon RCP

The Chameleon [7] reconfigurable communications processor (RCP) is a device which ishighly targeted towards mobile wireless applications It combines features of both reconfi-gurable logic and the dynamics of a microprocessor

The architecture combines many features:

† dedicated 32 bit PCI interface

† ARC processor

† large reconfigurable processing fabric

† external memory controller

† reconfigurable I/O

The reconfigurable fabric is organized into dynamic coarse-grained processing elementscombining local memory with parameterizable data path units and multipliers Each data pathunit works in a similar manner to the arithmetic logic unit (ALU) of a conventional processor

Configuration instructions are applied to define the operation of the data path elements,thereby allowing rapid configuration of the reconfigurable processing hardware.

7.3.3.3 Xilinx Virtex II

The Virtex II device from Xilinx [43] represents a vast enhancement to their existing VirtexFamily The CLB and BRAM architectures remain relatively unchanged The major enhance-ments included in this architecture not only combine fine- and coarse-grained resource butalso support system maintenance, with inclusion of a security mechanism The key enhance-ments of resources include:

† higher density

† dedicated 18-bit £ 18-bit multipliers

† new routing structure

† new I/O functionality

† triple DES encrypted configuration bitstream

† advanced clock management

The most noticeable addition is the dedicated multiplier resource Multipliers of this size havealways been a challenge to implement using, fine-grained field programmable resource Theaddition of these coarse-grained units will improve the MAC ability but may also increaseredundancy for applications which do not need them

The largest Virtex-II device includes:

† CLB array – 128 £ 120

† 18 £ 18 multipliers – 192

† 18-kbit BRAMS – 192

7.3.4 Reconfigurable Analog Components

Two major problems which drove the evolution from analog to digital processing were therequirements of improved flexibility and stability Analog processing, even when IC-based,relies upon fixed quantities of capacitance, resistance, and inductance, traditionally imple-mented using fixed, soldered discrete components Flexibility is therefore impractical withoutchanging the physical components Recent attempts have been made to provide IC-basedsolutions which house a choice of analog components to facilitate adaptive analog integratedcircuitry These devices are commonly described as field programmable analog arrays(FPAA)

The FPAA, similar to the FPGA, consists of an array of configurable analog blocks (CAB).These provide an analog processing resource surrounded by configurable routing A CAB andits support circuitry may consist of operational amplifiers with connections to componentsrequired for configuring analog filters, summing amplifiers, oscillators, rectifiers, compara-tors, and virtually any other type of analog circuit

The Anadigm AN10E40 [4] is the most interesting device available at present whichillustrates that the traditional problems associated with stability are being brought undercontrol The CABs used in the Anadigm device consists of op-amps and switched capacitorcircuitry which ensures that voltage drift due to temperature variation and aging is almost