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Digital Integrated CircuitsA Design Perspective The Devices Jan M.. Goal of this chapter Present intuitive understanding of device operation  Introduction of basic device equations  I

Digital Integrated Circuits

A Design Perspective

The Devices

Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic

July 30, 2002

Goal of this chapter

 Present intuitive understanding of device operation

 Introduction of basic device equations

 Introduction of models for manual

The Diode

n p

Mostly occurring as parasitic element in Digital ICs

Depletion Region

hole diffusion electron diffusion

hole drift electron drift Charge

Density

Distance

x +

-Electrical

x Field

x Potential V

ξ ρ

W2-W1

Diode Current

diffusionTypically avoided in Digital ICs

diffusion

Models for Manual Analysis

V D

I D = I S(eVD/φT – 1)+

Junction Capacitance

Diffusion Capacitance

Secondary Effects

V D (V) –0.1

SPICE Parameters

The MOS Transistor

MOS Transistors

-Types and Symbols

D

S G

D

S G

G

S

S G

NMOS Enhancement NMOS

Threshold Voltage: Concept

DepletionRegionn-channel

The Threshold Voltage

The Body Effect

-2.5 -2 -1.5 -1 -0.5 0 0.4

0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

V T

Current-Voltage Relations

A good ol’ transistor

QuadraticRelationship

0 1 2 3 4 5

V(x) +

–

V DS

I D

Current-Voltage Relations

Long-Channel Device

A model for manual analysis

Current-Voltage Relations

The Deep-Submicron Era

LinearRelationship

-4

0.5 1 1.5 2 2.5 x 10

VDS = VGS - VT

Simple Model versus SPICE

0.5 1 1.5 2

Saturated

V DSAT =V GT

V DS =V DSAT

V DS =V GT

A PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0 -1

-0.8 -0.6 -0.4 -0.2

Transistor Model

for Manual Analysis

The Transistor as a Switch

The Transistor as a Switch

1 2 3 4 5 6

The Transistor as a Switch

MOS Capacitances

Dynamic Behavior

Dynamic Behavior of MOS Transistor

D S

The Gate Capacitance

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

Gate Capacitance

WLC ox

WLC ox 2

2WLC o x 3

Measuring the Gate Cap

2 1.52 1 2 0.5 03

456789

Junction Capacitance

Linearizing the Junction Capacitance

Replace non-linear capacitance by

large-signal equivalent linear capacitance

which displaces equal charge over voltage swing of interest

Capacitances in 0.25 µ m CMOS

process

The Sub-Micron MOS Transistor

the length (for low V DS)

Drain-induced barrier lowering

(for low L)

V DS

V T

Typical values for S:

The Slope Factor

ox

D nkT

qV D

C

C n

e I I

GS

+

,

~ 0

qV D

DS GS

e e

I

I 0 1

Sub-Threshold I D vs V DS

kT

qV nkT

Summary of MOSFET Operating

Regions

D S

G

V GS,eff

Latch-up

Future Perspectives

25 nm FINFET MOS transistor