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Digital Integrated Circuits A Design Perspective The Wire Jan M.. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002... Interconnect Impact on Chip... Wire ModelsAll-inclusive mo

Digital Integrated Circuits

A Design Perspective

The Wire

Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic

July 30, 2002

The Wire

Interconnect Impact on Chip

Wire Models

All-inclusive model Capacitance-only

INTERCONNECT

Capacitance of Wire Interconnect

V out

V in

C L

Simplified Model

Capacitance: The Parallel Plate Model

Dielectric Substrat e

WL t

c

di

di int

ε

=

L L

Cwire

S S

Permittivity

Fringing Capacitance

W - H/2 H

+

(a)

(b)

Fringing versus Parallel Plate

(from [Bakoglu89])

Interwire Capacitance

Impact of Interwire Capacitance

(from [Bakoglu89])

15

INTERCONNECT

Wire Resistance

W

L H

R = ρ

H W L

Sheet Resistance

Ro

Interconnect Resistance

Dealing with Resistance

 Selective Technology Scaling

 Use Better Interconnect Materials

 reduce average wire-length

 e.g copper, silicides

 More Interconnect Layers

 reduce average wire-length

Polycide Gate MOSFET

n +

n +

SiO 2 PolySilicon Silicide

p

Silicides: WSi 2, TiSi2, PtSi2 and TaSiConductivity: 8-10 times better than Poly

Sheet Resistance

Modern Interconnect

INTERCONNECT

Interconnect Modeling

The Lumped Model

The Lumped RC-Model

The Elmore Delay

The Ellmore Delay

RC Chain

Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

The Distributed RC-line

1 5 2

RC-Models

Design Rules of Thumb

Lcrit >> √ tpgate/0.38rc

rise (fall) time at the line input is smaller than

RC, the rise (fall) time of the line

trise < RC

 when not met, the change in the signal is slower than the propagation delay of the wire