Compal NM b301 DG424 DG524 REV 1 0

THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMA

Trang 1

Security Classification LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER

Trang 2

BGA-1296 31mm*24mm

EC ITE IT8986E/BX-LQFP

Memory BUS (DDR3L) Single Channel 1.35V DDR3L 1600 MT/s (platform support up to 1866MT/s)

Page 39

Page 45

Page 45 Page 44

Page 38 Page 4~16

LPC BUS

USB 2.0 1x

8MB SPI ROM EC

File Name : Cairo 4D&5D

LCFC confidential

Page 38

Page 8 Page 28

USB2.0 Port5

Page 34 Page 34

AMD LV2-R17M-M1-70

GDDR5*4: 4GB/2GB

AMD: Level2 Package: S3

Trang 3

HIGH HIGH HIGH

Thermal Sensor 0x98(reserve)

EC SM Bus1 address Device

Smart Battery 0x16

WLAN

5

3 4 2 1 0

PCIE PORT LIST

BOM Structure Table

+3VALW

X X

O

X

X X

, X > Means OFF )

( O > Means ON

+3VALW_SOC

O O O

X X

V VGA BATT IT8986HE SODIMM WLAN WiMAX Thermal Sensor PCH

+3VS

EC

PCH

X EC_SMB_CK2

TP Module

X

X X

X

X X

+3VS

+3VL V V

Charger

V +3VL

DDI PORT LIST

Device NC eDP

1 2

3 4

USB3.0 (2.0) Touch Screen USB2.0 USB3.0

BIOS Device ID Map

PCIe1(Func0):Root Port#3

PCIe0(Func0):Root Port#1 PCIe0(Func1):Root Port#2

Type C( USB 2.0)

CARD READER

5 6 7

EMC_NS@ For EMC un-stuff part EMC_15@

EMC_14@

EMC 15" part EMC 14" part

8111H@

8111GUL LAN SKU part@

8111H LAN SKU part@

R16M-M1-30 dGPU SKU part EXO@

UMA@ UMA SKU ID part

Micron 2GB(256x16x4) VRAM X76 SKU M2GX4@

Samsung 2GB(256x16x4) VRAM X76 SKU S2GX4@

Hynix 2GB(256x16x4) VRAM X76 SKU H2GX4@

TMSEN@ Thermal Sensor part TMSEN_PX@ dGPU Thermal Sensor part TMSEN_UMA@ UMA Thermal Sensor part

HIGH HIGH HIGH HIGH LOW

ON ON ON ON

ON ON ON

OFF

OFF OFF OFF

OFF ON

HDMI@ HDMI Logo part

Touch Screen part

Trang 4

D D

Double confirm with Intel FAE, follow CRB will have low riskDDRA_CAVREF_R

DDRA_DQ5DDRA_DQ0

DDRA_DQ24

DDRA_DQ27

DDRA_DQ31DDRA_DQ26

DDRA_DQ39DDRA_DQ37DDRA_DQ35DDRA_DQ33

DDRA_DQ36

DDRA_DQ40

DDRA_DQ44DDRA_DQ42

DDRA_DQ47DDRA_DQ45DDRA_DQ41

DDRA_DQ46

DDRA_DQ56

DDRA_DQ60DDRA_DQ58

DDRA_DQ48

DDRA_DQ52

DDRA_DQS0

DDRA_DQS1DDRA_DQS#0

DDRA_DQS#1DDRA_DQS2DDRA_DQS#2DDRA_DQS3DDRA_DQS#3

DDRA_DQS#4DDRA_DQS4

DDRA_DQS#5DDRA_DQS5

DDRA_DQS6DDRA_DQS#6DDRA_DQS7DDRA_DQS#7

DDRA_MA0DDRA_MA2DDRA_MA4DDRA_MA6DDRA_MA8DDRA_MA10DDRA_MA12DDRA_MA14

DDRA_CAVREFDDRA_DQVREF

DDRA_CLK0DDRA_CLK0#

DDRA_ODT0 17DDRA_ODT1 17

DDRA_RAS# 17DDRA_WE# 17DDRA_CAS# 17

DDRA_CS0# 17DDRA_CS1# 17

DDRA_CKE1 17DDRA_CKE0 17

DDRA_CLK1 17DDRA_CLK1# 17DDRA_CLK0 17DDRA_CLK0# 17

+1.35V

@1

2RC93201 @ 20_0402_5%

RC29024.9_0402_1%

UC1A

APOLLOLAKE_FCBGA1296

@

MEM_CH0_DQ54BD39MEM_CH0_DQ43BJ40MEM_CH0_DQ32AR39

MEM_CH0_DQ7

BD62

MEM_CH0_DQ62BG37MEM_CH0_DQ51BD37

MEM_CH0_DQ40BJ44MEM_CH0_DQ8

AV59

MEM_CH0_DQ63BJ34MEM_CH0_DQ52BB37MEM_CH0_DQ41BG39

APL_SOC

2 OF 23REV = 0.7

MEM_CH0_CB5 AV47MEM_CH0_RESET_N AR34

NCTF2 BB41NCTF1 AT43

TP53 @1

RC93211 @ 20_0402_5%

CC1600.022U_0201_6.3V6-K

@1

2

Trang 5

D D

MEM_CH1_CS0_N BD17

MEM_CH1_CB5 AW19MEM_CH1_MA11

BH13

MEM_CH1_CKE1BG17MEM_CH1_ODT1 AV16

MEM_CH1_VREFDQ AT30

MEM_CH1_CAS_NBH4

MEM_CH1_CB6 BA23MEM_CH1_MA12

NCTF8 BB17NCTF7 AV17

UC1C

@

MEM_CH1_DQ55AV7MEM_CH1_DQ44AV10MEM_CH1_DQ33BD10

MEM_CH1_DQ5

BG27

MEM_CH1_DQ62AY3MEM_CH1_DQ51AU1

MEM_CH1_DQ40AV12MEM_CH1_DQ6

BG26

MEM_CH1_DQ63BG2MEM_CH1_DQ52AY5MEM_CH1_DQ41BD6

Trang 6

PCH_LCD_VDDEN_Q VOH min is 1.35V,

SY6288C20 VIH min is 1.35V, do NOT use level shift (Follow BMWC1)

PCH_ENBKL can direct connect to EC for costdown

GPIO Name I/O Voltage Default Term Buffer TypePNL0_VDDEN 1.8V

1.8V20K PD20K PDCMOSCMOSPNL0_BKLTEN

eDP RCOMP is used for DDI0/DDI1 ports of HDMI/DP

as well as the eDP interface DDI0_RCOMP is not used

CPU_EDP_AUXCPU_EDP_AUX#

CPU_EDP_TX1+

CPU_EDP_TX1-CPU_EDP_TX0+

CPU_EDP_TX0-DDI0_RCOMP_PEDP_RCOMP_N

HDMI_CLK+

HDMI_CLK-HDMI_TX1+

HDMI_TX1-HDMI_TX2+

HDMI_TX2-HDMI_TX0+

HDMI_TX0-PCH_BKLT_CTRL_QPCH_LCD_VDDEN_QPCH_ENBKL

PCH_ENBKLPCH_LCD_VDDEN_QPCH_BKLT_CTRL_Q

28

CPU_EDP_TX0+

28CPU_EDP_TX0-28CPU_EDP_TX1+

28CPU_EDP_TX1-28

HDMI_TX1+ 32HDMI_TX1- 32

HDMI_CLK+ 32HDMI_CLK- 32HDMI_TX0- 32HDMI_TX0+ 32

HDMI_TX2+ 32HDMI_TX2- 32

HDMI_HPD#

32

CPU_EDP_HPD 28EDP_HPD# 10

+3VS

+1.8V_PU

SQC1AL2N7002KDW1T1G_SOT363-62

QC2BPJT138K_SOT363-6

SQC1B

L2N7002KDW1T1G_SOT363-65

RPC210K_0404_4P2R_5%

UC1F

@

MDSI_C_DP_3 AK13MDSI_C_DP_2 AM12MDSI_C_DP_1 AM5MDSI_C_DP_0 AK7

MDSI_C_DN_3AM13MDSI_C_DN_2AM10MDSI_C_DN_1AM6MDSI_C_DN_0AK6

MDSI_C_CLKPAM9MDSI_C_CLKN AM7MDSI_A_DP_3

MDSI_C_TE

M43

PNL1_BKLTEN B53PNL0_VDDEN C47

RC93881 @ 2 0_0402_5%

RPC310K_0404_4P2R_5%

UC1E

@

DDI1_TXP_3 AB3DDI1_TXP_2 AC1DDI1_TXP_1 AD3DDI1_TXP_0 AF2

DDI1_TXN_3 AB2DDI1_TXN_2 AC2DDI1_TXN_1 AD2DDI1_TXN_0 AF3

DDI1_AUXP AK16DDI1_AUXN AK15

DDI0_TXP_3 AL2DDI0_TXP_2 AH3DDI0_TXP_1 AM3DDI0_TXP_0 AK3

DDI0_TXN_3 AL1DDI0_TXN_2 AH2DDI0_TXN_1 AM2DDI0_TXN_0 AK2

DDI0_AUXP AM16DDI0_AUXN AM15

Trang 7

D D

GP_CAMERASB11 E30

MCSI_RX_CLK0_P L23MCSI_RX_CLK0_N J23

GP_CAMERASB7 L34GP_CAMERASB8 M34

APL_SOC

8 OF 23REV = 0.7

T52

EMMC_D3 V51SDIO_D1

P57

EMMC_CLK Y58

EMMC_D4 V52SDIO_D2

Trang 8

Intel recommends to add a VSS shield at least 4Mmils

wide to shield between PCIE2_USB3_SATA3_RCOMP_P /

PCIE2_USB3_SATA3_RCOMP_N trace and adjacent I/O

Port

P0 P1 P2 P3 P4 P5

Config

PCIE Configuration

X4 X1 X1

Device

dGPU LAN WLAN

BIOS Device ID Map

PCIe1(Func0):Root Port#3 PCIe0(Func0):Root Port#1 PCIe0(Func1):Root Port#2

CMOS 20K PU 1.8V

Buffer Type Default Term I/O Voltage

Follow CRB: set WP# and HOLD# PU

The I2C signals are open drain, and it has internal pull-up.

A 1 kΩ ± 5% for external pull-up resistor is recommended.

Reserve Touch Pad I2C LS(MOS and IC) Lewis 2016/10/21

PCH_SPI_CS0#

PCH_SPI_D1

PCH_SPI_CLKPCH_SPI_D0PCH_SPI_D2

PCH_SPI_D3+VCC_SPI

PCH_SPI_D1_RPCH_SPI_CS0#_RPCH_SPI_CLK_R

PCIE_PRX_GTX_P2PCIE_PTX_GRX_P2

PCIE_PRX_GTX_N2

PCIE_PRX_GTX_N1PCIE_PTX_GRX_N1

PCH_SPI_CS0#_RPCH_SPI_CLK_R

TP_I2C_SCL4TP_I2C_SDA4

TP_I2C_SCL4_MTP_I2C_SDA4_MTP_I2C_SCL4

TP_I2C_SCL4_RTP_I2C_SDA4_R

PCIE_PRX_GTX_N1 20PCIE_PRX_GTX_P120PCIE_PTX_C_GRX_P1 20PCIE_PTX_C_GRX_N1 20

PCIE_PTX_C_GRX_P0 20PCIE_PTX_C_GRX_N0 20

PCIE_PRX_GTX_N0 20PCIE_PRX_GTX_P0 20

GPIO_12316

GPIO_11816GPIO_12116GPIO_12016SIO_SPI_2_FS016

GPIO_11116GPIO_11716

GPIO_11216GPIO_11316

GPIO_10416GPIO_10516GPIO_10616GPIO_11016

PCIE_WAKE# 36,39,44

PMC_WAKE#

10

EC_SPI_CLK_R44

EC_SPI_CS0#_R44

EC_SPI_D0_R44

EC_SPI_D1_R44

TP_I2C_SDA4_R 45TP_I2C_SCL4_R 45

+VCC_SPI

+VCC_SPI+1.8VALW

+3VALW

+1.8VALW

+1.8VS+1.8VALW

+3VS+3VALW

+3VS

+1.8VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER

RC937010K_0402_5%

RC93151 @ 20_0402_5%

R94240_0402_5%2 1

RC93831 @ 20_0402_5%

RC93821 @ 20_0402_5%

RP162.2K_0404_4P2R_5%

RC93171 23.3K_0402_5%

CC175 0.1U_0201_6.3V6-KPX@

CC174 0.1U_0201_6.3V6-KPX@

TP56@1

R47321K_0402_5%

APL_SOC

9 OF 23REV = 0.7

PCIE_P0_TXP V3PCIE_P1_TXP R1

PCIE_P5_USB3_P2_TXP

L2

PCIE_P2_TXP T2

PCIE_WAKE3_NN62PCIE_P3_USB3_P4_RXN

P10

PCIE_WAKE2_NP61PCIE2_USB3_SATA3_RCOMP_N

Q166APJT138K_SOT363-6

13

RC93161 23.3K_0402_5%

RP172.2K_0404_4P2R_5%

@

RPC27

10K_0804_8P4R_5%18273645

RC93801 @ 20_0402_5%

CC171 1 20.1U_0201_6.3V6-K

R473510K_0402_5%

2

CC176 0.1U_0201_6.3V6-KPX@

Q166BPJT138K_SOT363-6

CC178 0.1U_0201_6.3V6-KPX@

CC180 0.1U_0201_6.3V6-KPX@

TP55@1

R94170_0402_5% 2 @ 1

2

CC169 1 20.1U_0201_6.3V6-K

RC93811 @ 20_0402_5%

CC177 0.1U_0201_6.3V6-KPX@

RC93111 @ 20_0402_5%

APL_SOC

13 OF 23REV = 0.7UC1M

@

LPSS_I2C0_SCL AR63LPSS_I2C1_SCL AM61LPSS_I2C2_SCL AP58LPSS_I2C3_SCL AL62LPSS_I2C4_SCL AP54

LPSS_I2C0_SDA AR62

LPSS_I2C5_SCL AP51

LPSS_I2C1_SDA AN62

LPSS_I2C6_SCL AK61FST_SPI_MOSI_IO0

RC93102 133_0402_5%

CC173 0.1U_0201_6.3V6-KPX@

Trang 9

2 No trace under crystal

3 Place on oppsosit side of MCP for temp influence

4 EDS request X'TAL ESR=50Kohm; +/-20ppm; X1,X2 pin capacitance=15pF

PDG v0.9 request SUSPWRDNACK PU to +1.8VALW(CRB w/o PU) Remove this requirement in PDG v1.0;

SUSPWRDNACK is +3.3V Level set by GPIO_88(PD) PDG&CRB request H_PROCHOT# 1Kohm PU to +1.8VALW

3.3V

Follow CRB use 10V cap, need confirm if can use 6.3V

RCOMP RESISTOR REQUIREMENT

CSI1.1

CSI 1.2 (DPHY/CPHY)

USB2 and 3.3V mode GPIO

MCSI_DPHY1.1_RCOMP MCSI_DPHY1.2_RCOMP

150 +/-1%

EMMC, Legacy and GPIO

signals including 1.8V mode

SD Card, PMU, LPC, SMBUS.

EMMC_RCOMP GPIO_RCOMP PMU_RCOMP

GPIO_88 strap to LOW, SUSPWRDNACK set to 3.3V Mode

Spacing: 10mils; length: 1000mils

Follow Intel schematics check list to add PU for EC_RSMRST#(Reserve)Need change to 0201 size later

Follow CRB v1.5 to change RC50 from 330Kohm to 100K ohm 05/06

use 10ohm pull up to +1.8VALW for LTB BSSB enable lewis 2016/10/21 reserve

XDP_TDOXDP_TCLKXDP_PRDY#

XDP_TMSXDP_TDIXDP_TRST#

SYS_PWROK_R

RTC_INTRUDERBVCCRTC_EXTPAD

RTC_TEST#

RTC_RST#

H_PROCHOT#

SUSPWRDNACKH_PROCHOT#

MCSI_DPHY1.1_RCOMPUSB2_RCOMP

MCSI_DPHY1.2_RCOMPEMMC_RCOMPGPIO_RCOMP

MDSI_RCOMP

M1_RCOMPPDM0_RCOMPPD

H_PROCHOT#

44

SYS_PWROK 44EC_RSMRST# 44

RTC_RST#

44RTC_TEST#

NCTF14 C15

TP54@1

NCTF46 AC13NCTF41 AB49

NCTF45 AB13

NCTF49 A3

NCTF54 R39NCTF55 R37

NCTF42 R25

NCTF53 P39

SOC_PWROK AG49NCTF47 P27

NCTF50 P25

NCTF52 M39NCTF51 C2NCTF48 J29NCTF43 C13

2RC391 260.4_0402_1%

12RC401 2200_0402_1%

Trang 10

follow CRB reserve PU for PMIC_RESET#

PMIC_RESET# is 1P8V voltage, need double check

Connect SUSCLK to NGFF Conn.

Connect SUSCLK to EC in CRB

PMC_SUSCLK is 3.3V level set by GPIO_88(PD)

PBTN_OUT# is 3.3V level set by GPIO_88(PD), and /w internal 20Kohm PU

PMC_BATLOW# is 3.3V level set by GPIO_88(PD)PMC_PLTRST# & PMC_RSTBTN# is 3.3V level set by GPIO_88(PD)

PM_SLP_S3# & PM_SLP_S4# is 3.3V level set by GPIO_88(PD)

3.3V3.3V3.3V3.3V3.3V

3.3V

EMMC_PWR_EN_N

GPIO_224GPIO_223NCTF

PMIC_I2C_SDA

PMIC_STDBYGPIO_213PMIC_PWRGOOD

GPIO_214PM_SLP_S4#_R

PMIC_THERMTRIP#_RPMC_ACIN

SUS_STAT#

EC_SMI#_QPMC_SUSCLK

PMIC_THERMTRIP#_R

SUSCLK39

PM_SLP_S3#44,54PM_SLP_S4#44PBTN_OUT#44

PLT_RST#20,36,38,39,44

ACIN#44

GPIO_39 16GPIO_40 16

+3VALW+1.8VALW

+3VS+3VALW

+1.8VALW

+1.24VALW

+3VALW_SOC+3VALW_SOC

+3VL_EC+1.8VALW

+1.8VALW+1.8VALW

SQC213B

@

RC60100K_0402_5%

@

RC933410K_0402_5%

@

13

QC6APJT138K_SOT363-6

SQC213A

TP36

GD

SQC10

L2N7002KWT1G_SOT323-3

@2

Trang 11

USB2.0 CARD READER BT

GPU do NOT use CLKREQ#, Set level shifter as NC GPU_CLKREQ# control by BOM structure(Follow CG412)

2 No trace under crystal

3 Place on oppsosit side of MCP for temp influence

4 EDS request X'TAL Max ESR=80ohm; +/-30ppm; Typical CL=12pF; Max PD=100uW

CLOCK REQUEST

19.2MHz CRYSTAL TXC SJ10000LN00

3.3V3.3V1.05V1.05V

Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V]

ODD

USB 2.0( for stand USB 3.0 port)

Remove level shift, due to LAN chip page already have level shift

3.3V3.3V3.3V3.3V3.3V

PCH_SMB_ALERT# with 20K PU default term

Follow HW check list to reserve0.1uF for +1.05VS, 01/15

PCH_SMB_DATAPCH_SMB_CLK

CPU_SVID_ALRT#_R

PCH_SMB_ALERT#

USB20_N7

CPU_SVID_DATCPU_SVID_CLK

WLAN_CLKREQ#_Q

GPU_CLKREQ#_QLAN_CLKREQ#_QPCIE_CLKREQ_3#

CPU_SVID_CLK

GPU_CLKREQ#_QGPU_CLKREQ#_Q

USB30_TX_P1

USB30_RX_P1

SATA_PRX_DTX_N1SATA_PTX_DRX_N1SATA_PRX_DTX_P1

SATA_PRX_DTX_N0SATA_PTX_DRX_N0

CLK_PCIE_GPU#

CLK_PCIE_GPU

CLK_PCIE_WLANCLK_PCIE_WLAN#

CLK_PCIE_LAN#

CLK_PCIE_LAN

HDA_RST_AUDIO#_R

SERIRQ_RLPC_FRAME#_R

CLK_PCI_TPM_RCLK_PCI_EC_RLPC_AD3_R

USB20_P2

USB20_N0SATA_PTX_DRX_P1

USB20_N7 39USB20_P7 39

CPU_SVID_ALRT# 56,57CPU_SVID_DAT 56,57CPU_SVID_CLK 56,57

USB30_RX_N131

USB30_TX_P131

USB30_TX_N131

USB30_RX_P131

GPIO_8216

GPIO_9216

GPIO_8816HDA_RST_AUDIO#

34

GPIO_7816

SERIRQ38,44LPC_FRAME# 38,44

CLK_PCI_TPM 38CLK_PCI_EC 44LPC_AD3 38,44

USB20_N5 34USB20_P5 34

USB20_P3 31USB20_N3 31

USB20_P4 45USB20_N4 45

USB20_N2 28USB20_P2 28

USB20_P0 29USB20_N0 29

USB30_RX_N029

USB30_TX_P029

USB30_TX_N029

USB30_RX_P029

USB20_N6 28USB20_P6 28

USB20_P1 31USB20_N1 31

+3VS+3VS

+1.8VALW

+1.05VS

+3VS+3VALW_SOC

+1.8VALW

+3VALW_SOC

+3VALW_SOC+1.8VALW

+3VALW

SQC225A

@2

RPC142.2K_0404_4P2R_5%

@

LPC_CLKOUT1AA62LPC_CLKOUT0AB61LPC_AD3W63LPC_AD2W62LPC_AD1Y62LPC_AD0Y61

OSCOUT P29OSCIN R27

OSC_CLK_OUT_4AF62OSC_CLK_OUT_3AE60OSC_CLK_OUT_2AG63OSC_CLK_OUT_1AF61OSC_CLK_OUT_0AG62

@

RC298169_0402_1%

SQC17B

RC71 1 220_0402_5%

CC1910.1U_0201_6.3V6-K

@1

2

APL_SOC

12 OF 23REV = 0.7UC1L

SMB_ALERT_N

R63

USB2_DN0V10USB2_DP2Y13USB2_OTG_ID

SQC18B

@5

GD

SQC17A

RC299 2 @ 110K_0402_5%

RC79 1 2 200K_0402_5%

RC93691 220_0402_5%

GD

SQC18A

@2

2

QC22AL2N7002KDW1T1G_SOT363-6

UC1J

@

PCIE_CLKOUT3PB7PCIE_CLKOUT3NB5PCIE_CLKOUT2PA7PCIE_CLKOUT2NB8PCIE_CLKOUT1PC10PCIE_CLKOUT1NA10PCIE_CLKOUT0PC11PCIE_CLKOUT0NB11

USB_SSIC_0_TX_PAH13

USB_SSIC_0_RX_PAG16USB_SSIC_0_TX_NAH12

USB_SSIC_0_RX_NAG15SATA_P0_RXP

@

RC7710K_0402_5%

GD

SQC225B

@5

Trang 12

1206618869: HD Audio SDI I/O Pin Issue

Follow Intel request to remove for QS CPU

PXS_RST#_SOC

PXS_PWREN#_SOC GPIO_15

Signal Name Ball Name

CMOS 20K PD

1.8V

Buffer Type Default Term

I/O Voltage

Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V] Change LBSS138DW[Vgs(th)<1.5V] to L2N7002KDW[Vgs(th)<2.0V]

0

GPU SKU 1

UMA SKU

15" Panel 1

14" Panel

BOARD_ID3 BOARD_ID2

0

BOARD_ID1

Reserve Reserve

If EC_SCI#_Q default term is PU, EC is OD for EC_SCI#, can use 0ohm short If KBRST#_Q default term is PU, EC is OD for KBRST#, can use 0ohm short

Maybe can delete this connection, after checking /w BIOS

Follow CRB: EC_WAKE_SCI# connect to ECFollow CRB: SOC GPIO_11 is 1.8V Voltage

Reserve for MS-Windows RS1

TP_INT# IS Output,pull up @ touch pad conn side

CRB direct connect to GPIO_18

Lewis 2016/10/13

BOARD_ID3BOARD_ID1

PXS_RST#_SOC

KBRST#_QEC_SCI#_Q

VR_VGA_PWRGD_QPCH_BT_OFF#

PCH_BT_OFF#

EC_WAKE_SCI#_R

BOARD_ID2BOARD_ID0

EC_SCI#_Q

VR_VGA_PWRGD_Q

HDA_SDOUT_AUDIO_RHDA_SYNC_AUDIO_RHDA_BITCLK_AUDIO_R

GPIO_37 16

PXS_RST# 20

SDATA_IN 34

KBRST# 44EC_SCI# 44

BT_OFF# 39,44

PCH_BEEP34

+1.8VALW

+3VL_EC+1.8VALW

+3VS+1.8VALW+1.8VALW

+1.8VALW+1.8VALW

+3VS

+1.8VALW

+3VALW

+3VS+1.8VALW

RC3321K_0402_1%

@

QC211BPJT138K_SOT363-6PX@

@

GD

SQC226B

APL_SOC

17 OF 23REV = 0.7

UC1Q

@

PWM0 B41PWM1 C41PWM2 F41PWM3 E41GPIO_216 P30GPIO_217 M29GPIO_218 M30GPIO_219 L30

SQC220B

SQC215A

@2

GD

SQC226A

GPIO_6 B31

ISH_GPIO_3

AM54

GPIO_7 H39GPIO_13 C30

GPIO_24 C25

ISH_GPIO_4

AM51

GPIO_8 B29GPIO_14 C38

S LBSS138LT1G_SOT-23-3QC19

SQC217A

RPC1610K_0404_4P2R_5%

SQC215B

@5

GD

SQC220A

SQ164

L2N7002KWT1G_SOT323-3PX@

2

QC211APJT138K_SOT363-6PX@

RC93921 @ 20_0402_5%

CC137.1U_0402_10V6-K

@1

2

GD

SQC217B

@

RPC2010K_0404_4P2R_5%

Trang 13

Note:Place CAPs Back of CPU

Follow CRB(DOC#559031) V1.0 connectUC1.AM28 to +VDD2_1P24_GLML

Follow CRB: P16, T15, T13 are different power trace.

Maybe can merge them to one net

Place near UC1.AK25, AJ25

Place near UC1.AG20

Place near UC1.AM44, AK46, AK41, AK39, AJ42, AJ41, AJ39, AK42, AK44, AJ46, AJ37, AK37

Follow CRB add 0.1uF CAP

Place near UC1.AC41, AA42, Y44, V44, V46

Note:Place CAP Back of CPU

Place near UC1.AJ20, AJ22, AK22

Place near UC1.AE20, AE18, AE22, AG22

Place near UC1.AM20, AK20, AM37

Place near UC1.AA18, AA20Note:Place CAP Back of CPU

Place near UC1.AA22, Y20, V18, Y18, AA23, AC23

Note:Place CAPs Edge of CPU Note:Place CAP Near CPU

Note:Place CAP Edge of CPUNote:Place CAP Near CPU

Note:Place CAP Edge of CPUNote:Place CAP Near CPUNote:Place CAPs Edge of CPU Note:Place CAP Near CPU

Place near UC1.AM28

IccMax=1.5A IccMax=0.9A

For SVID over moat.

Place near over moat area.

+VDD2_1P24_GLML+1.24VALW

+VDD2_1P24_DSI_CSI+1.24VALW

+VCCRAM_1P05_IO_3PHASEIO

VCCRTC

+VCCRAM_1P05_FUSE+VCCRAM_1P05_FHV0+VCCRAM_1P05_FHV1+1.05VS

+1.05VS

+3VALW_SOC

+VDD2_1P24_DSI_CSI

+VDD2_1P24_AUD_ISH_PLL+VCCRAM_1P05_IO_3PHASEIO

+VCCRAM_1P05_FHV0+VCCRAM_1P05_FHV1+VCCRAM_1P05_FUSE

VCCRTC

+VNN+VNN

2

CC1891U_0402_6.3V6KCD@

1

2

CC791U_0402_6.3V6K1

2

CC541U_0402_6.3V6K1

2

CC881U_0402_6.3V6K1

2

RC104 1 @ 20_0603_5%

CC961U_0402_6.3V6K1

2

CC991U_0402_6.3V6K1

2

RC106 1 @ 20_0603_5%

CC971U_0402_6.3V6KCD@

1

2

CC551U_0402_6.3V6K1

2CC52

1U_0402_6.3V6KCD@

1

2

CC531U_0402_6.3V6K1

2

CC1031U_0402_6.3V6K

@1

2

RC105 1 @ 20_0603_5%

CC1900.1U_0201_6.3V6-K

@1

2

CC1011U_0402_6.3V6KCD@

1

2APL_SOC

22 OF 23REV = 0.7UC1V

VCC_VCGI26 V28

VNN15 AM42

VCC_VCGI15 AJ32VCC_VCGI8 AE30

VCC_VCGI25 U32

VNN14 AM41

VCC_VCGI14 AJ30VCC_VCGI7 AE28

VCC_1P24V_A2

AA20

VCC_VCGI24 U30

RSVD15 V49VNN13 AM25

VCC_VCGI13 AJ28VCC_VCGI6 AC32

VCC_1P24V_A1

AA18

VCC_VCGI23 U28

RSVD14 BJ62VNN12 AM23

VCC_VCGI12 AG32VCC_VCGI5 AC30

2

CC811U_0402_6.3V6K1

2

RC103 1 @ 20_0603_5%

RC2931 @ 20_0603_5%

CC571U_0402_6.3V6K1

2

CC601U_0402_6.3V6KCD@

1

2

CC861U_0402_6.3V6K1

2

CC511U_0402_6.3V6K1

2

CC1001U_0402_6.3V6K1

2RC102 1 @ 20_0603_5%

CC13022U_0603_6.3V6-M1

2

CC1071U_0402_6.3V6K1

2

CC981U_0402_6.3V6K1

2

CC921U_0402_6.3V6KCD@

1

2CC931U_0402_6.3V6K1

2

CC591U_0402_6.3V6K1

2

CC13122U_0603_6.3V6-M1

2

CC871U_0402_6.3V6K1

2

CC721U_0402_6.3V6K1

2CC70

1U_0402_6.3V6K1

2

CC1850.1U_0201_6.3V6-K

@1

2

CC581U_0402_6.3V6K1

2

CC891U_0402_6.3V6KCD@

1

2

CC9422U_0603_6.3V6-M1

2

CC501U_0402_6.3V6KCD@

1

2

CC801U_0402_6.3V6K1

2RC101 1 @ 20_0603_5%

RC2941 @ 20_0603_5%

CC911U_0402_6.3V6K1

2

CC1840.1U_0201_6.3V6-K1

2CC71

1U_0402_6.3V6KCD@

1

2

CC561U_0402_6.3V6K1

1

2RC100 1 @ 20_0603_5%

2

CC611U_0402_6.3V6K1

2

CC1051U_0402_6.3V6KCD@

1

2

CC8422U_0603_6.3V6-M1

2

CC1061U_0402_6.3V6K1

2RC107 1 @ 20_0603_5%

CC9022U_0603_6.3V6-M1

2

Trang 14

D D

Place near UC1.AE25, AC25, AA25, U23, V22, V23, V25, Y23, Y25, U25, U20, U22

Note:Place CAPs Back of CPU Note:Place CAPs Edge of CPU

Place near UC1.AN46, AN44, AN42, AN41, AN23, AN22,AN20, AN18, AV14, AT51, AR17, AR47, AT13, AT17, AV50

Place near UC1.AE44, AC46, AC44, AA46, AE42, AG25, AE46, AC42

Note:Place CAP Edge of CPU

2 x 0402_1uF

4 x 0402_1uF; 2 x 0603_22uF

Note:Place CAPs near CPU

Note:Place CAP Near CPU

57CPU_VSS_SENSE56CPU_VCC_SENSE56

+1.05VA_SOC_G3

+VDD1_1P8 +1.8VALW

2

CC1920.1U_0201_6.3V6-KEMC@

1

2

CC1281U_0402_6.3V6KCD@

1

2

CC12922U_0603_6.3V6-M1

2

CC1211U_0402_6.3V6K1

2

CC1271U_0402_6.3V6K1

2

APL_SOC

23 OF 23REV = 0.7

AR47

VCC_VCGI32 F29VCC_1P8V_A6 AE44

VCC_VCGI36 AC37

VCC_VCGI59 Y41

VCC_VCGI48 U44VDDQ8

AN46

RSVD21

BJ3

VCC_VCGI40 E43VCC_1P8V_A3 AC44

VCC_VCGI60 AC36VCC_VCGI58 Y39

VCC_VCGI47 U42VDDQ7

AN44

RSVD19

BG63

VCC_VCGI33 E35VCC_1P8V_A2 AC42

VCC_VCGI62 AA39VCC_VCGI57 Y37

VCC_1P05V16

V23

VCC_VCGI46 U41VDDQ6

2CC1191U_0402_6.3V6KCD@

1

2

RC822 1100_0402_1%

CC1181U_0402_6.3V6K1

2

CC1261U_0402_6.3V6K1

2CC1251U_0402_6.3V6K1

2

RC93621@ 20_0805_5%

CC12322U_0603_6.3V6-MCD@

1

2

CC1871U_0402_6.3V6KCD@

2

RC108 1@ 20_0805_5%

Trang 15

UC1U

@

VSS353 U57VSS337 U10

VSS334 R32VSS265

E19

VSS374 AN56

VSS380 Y5

VSS360 V27VSS349 U51

VSS367 Y34VSS356 U63VSS345 U27

VSS366 Y27VSS355 U62VSS344 U2

VSS365 Y22VSS354 U59

VSS343 U18VSS333 R23

VSS342 U17VSS332 P9

19 OF23REV = 0.7

VSS31

AC18

VSS20 AA41VSS9 A44

VSS6 A32

APL_SOC

20 OF 23REV = 0.7

VSS224 BE47VSS213 BE1

VSS202 BB25VSS135

AR45

VSS261 C16VSS250 BJ28VSS239 BH1

VSS223 BE43VSS212 BD8

VSS134

AR32

VSS260 C12VSS249 BJ18VSS238 BG45

VSS222 BE37VSS150

AT62

VSS133

AR19

VSS259 BJ8VSS248 BJ14VSS237 BG41

VSS221 BE35VSS210 BD56

Trang 16

GPIO_39 Enable CSE ROM Bypass 20K PD 1 = Enable bypass 0 = Disable bypass (default)* This strap tells CSE (TXE3.0) to bypass ROM EDS(v2.1) P47

GPIO_40 RTC Clock Timer Bypass Only be used when an external oscillator is used to supply a 32.768kHz clock to RTC_X1 EDS(v2.1) P47

GPIO_82 RSVD 20K PD Ensure this strap always PD for normal platform operation EDS(v2.1) P47

GPIO_92 SMBus No Re-Boot 20K PD 1 = Enable 0 = Disable(Default)* Should strap this pin LOW Functionality is handled by the PMC EDS(v2.1) P48

GPIO_88 PMU 1.8V/3.3V mode select 1 = Buffers set to 1.8V mode(Default) 0 = Buffers set to 3.3V mode* Follow CRB to strap this pin LOW PMU signals are 3.3V mode EDS(v2.1) P48 GPIO_78 SMBus 1.8V/3.3V mode select 1 = Buffers set to 1.8V mode(Default) 0 = Buffers set to 3.3V mode* Follow CRB to strap this pin LOW SMBus signals are 3.3V mode EDS(v2.1) P47

GPIO_105 Ensure this strap is PD when RSM_RST_N de-asserts for normal platform operation RSVD

GPIO_106 Ensure this strap is PD when RSM_RST_N de-asserts for normal platform operation

GPIO_111 RSVD 1 = Leave these regions unmapped by the System Agent 0 = Map these regions to the boot SPI Pull LOW for designs that boot from SPI and HIGH otherwise EDS(v2.1) P48

GPIO_118 Flash Descriptor Override 20K PD 1 = Override 0 = No Override (Normal Operation)* This strap enables the platform to override security features in the SPI EDS(v2.1) P48 GPIO_117 RSVD 20K PD Ensure this strap is PD when RSM_RST_N de-asserts for normal platform operation

GPIO_123 Ensure this strap is PU when RSM_RST_N de-asserts for normal platform operation

GPIO_112 RSVD 20K PD Ensure this strap is PD when RSM_RST_N de-asserts for normal platform operation GPIO_113 RSVD 20K PD Ensure this strap is PD when RSM_RST_N de-asserts for normal platform operation

GPIO_120 Top swap override 20K PD 1 = Enable 0 = Disable (default)* This strap enables platform to change different SPI ROM location ESD(v2.1) P48 GPIO_121 RSVD 20K PD Ensure this strap is PD when RSM_RST_N de-asserts for normal platform operation

Floating Floating Floating Floating Floating Floating Floating

4.7K PD

Floating Floating

4.7KPD

Floating Floating Floating

Follow CRB(DOC#: 561386); EDS(v1.5) P57

Change to P-MOS Diodes DMG1013UW-7 09/02

EDS(v2.1) P47 EDS(v2.1) P47

1 = Enable bypass

0 = Disable bypass (default)*

Ensure this strap always PD for normal platform operation EDS(v2.1) P47

EDS(v2.1) P48 EDS(v2.1) P48

EC_ME_PROTECT GPIO_118 TXE Flash Descriptor Override

GPIO_92GPIO_82GPIO_48GPIO_35

GPIO_110GPIO_111GPIO_105

GPIO_121GPIO_112GPIO_117

GPIO_113SIO_SPI_2_FS0

GPIO_37

GPIO_33

GPIO_118

GPIO_3412GPIO_3512GPIO_3612GPIO_3910GPIO_4010GPIO_4310

GPIO_4710GPIO_4810GPIO_7811GPIO_8211GPIO_8811GPIO_9211GPIO_4410

GPIO_1048GPIO_1058GPIO_1068GPIO_1118GPIO_1188GPIO_1108

GPIO_1178GPIO_1238GPIO_1128GPIO_1138GPIO_1208GPIO_1218SIO_SPI_2_FS08

PCH_JTAG_TMS12PCH_JTAG_TDO12

PCH_JTAG_TCK 12PCH_JTAG_TDI12

Size Document Number R e vDate: Sheet o f

RC30710K_0402_5%

@

RC25610K_0402_5%

@

GD

RC92921K_0402_5%

RC23410K_0402_5%

@

RC2474.7K_0402_1%

@

RC94032.2K_0402_5%

RC26210K_0402_5%

@

RC32010K_0402_5%

@

RC30410K_0402_5%

@

RC2284.7K_0402_1%

@

RC2454.7K_0402_1%

@

RC30910K_0402_5%

@

RC2264.7K_0402_1%

@

RC31010K_0402_5%

@

RC30310K_0402_5%

@

RC3194.7K_0402_1%

@

RC9324100K_0402_5%

@

RC2504.7K_0402_1%

@

RC2431K_0402_5%

@

RC2494.7K_0402_1%

@

RC24210K_0402_5%

@

RC32310K_0402_5%

@

RC2484.7K_0402_1%

@

RC23610K_0402_5%

@

RC30610K_0402_5%

@

RC92944.7K_0402_1%

@

RC26310K_0402_5%

@

RC2514.7K_0402_1%

@

RC31810K_0402_5%

@

RC9323100K_0402_5%

@

RC2604.7K_0402_1%

@

RC23510K_0402_5%

@

RC2464.7K_0402_1%

@

RC3174.7K_0402_1%

@

RC30510K_0402_5%

@

RC23310K_0402_5%

@

RC30810K_0402_5%

@

RC2614.7K_0402_1%

@

RC3214.7K_0402_1%

@

RC25910K_0402_5%

@

RC25710K_0402_5%

@

RC9404100K_0402_5%

Trang 17

DDRA_MA4

DDRA_ODT1

DDRA_CLK1DDRA_CLK1#

DDRA_MA11

DDRA_MA2

DDRA_CKE1DDRA_DQ30

DDRA_DQ18

DDRA_DQ24

DDRA_DQ44

DDRA_DM2DDRA_DM1DDRA_DQS0

DDRA_DQS3DDRA_DQS#3DDRA_DQS#0

DDRA_DQ52

SA0SA1

DDRA_DQ40

DDRA_CLK0#

DDRA_MA8

DDRA_DM7DDRA_DQS#6

DDRA_BA2#

DDRA_CS1#

DDRA_MA3

DDRA_CLK0DDRA_MA9DDRA_CKE0

DDRA_DQS#4DDRA_DQS4

DDRA_DQ57

DDRA_DQ58DDRA_DQS7DDRA_DQS#7

DDRA_DQ61

DDRA_DQ2DDRA_DQ4

DDRA_DQ6

DDRA_DQ7

DDRA_DQ8

DDRA_DQ9DDRA_DQ10

DDRA_DQ13

DDRA_DQ16DDRA_DQ20

DDRA_DQ21DDRA_DQ22

DDRA_DQ25DDRA_DQ26

DDRA_DQ27DDRA_DQ31

DDRA_DQ32

DDRA_DQ35DDRA_DQ36

DDRA_DQ37

DDRA_DQ39

DDRA_DQ41DDRA_DQ43

DDRA_DQ46

DDRA_DQ48

DDRA_DQ49DDRA_DQ51

DDRA_DQ55

DDRA_DQ56

DDRA_DQ59DDRA_DQ62

DDR_CA4

DDR_DQ 4

DDRA_DRAMRST#_R 4

DDRA_CKE04DDRA_BA2#

4

DDRA_CLK04DDRA_CLK0#

4DDRA_BA0#

4DDRA_WE#

4DDRA_CAS#

4DDRA_CS1#

4

DDRA_CKE1 4

DDRA_BA1# 4DDRA_RAS# 4DDRA_CS0# 4DDRA_ODT0 4

DDRA_CLK1 4DDRA_CLK1# 4

DDRA_ODT1 4

SMB_DATA_S3 11,39SMB_CLK_S3 11,39

+3VS

RD1613.65K_0402_1%

LCN_DAN06-K4406-0102ME@

VREF_DQ

1

VSS1 2VSS2

3

DQ4 4DQ0

5

DQ5 6DQ1

7

VSS3 8VSS4

9

DQS#010DM0

11

DQS0 12VSS5

13

VSS6 14DQ2

15

DQ6 16DQ3

17

DQ7 18VSS7

19

VSS8 20DQ8

21

DQ12 22DQ9

23

DQ13 24VSS9

25

VSS10 26DQS#1

27

DM1 28DQS1

29

RESET# 30VSS11

31

VSS12 32DQ10

33

DQ14 34DQ11

35

DQ15 36VSS13

37

VSS14 38DQ16

39

DQ20 40DQ17

41

DQ21 42VSS15

43

VSS16 44DQS#2

45

DM2 46DQS2

47

VSS17 48VSS18

49

DQ22 50DQ18

51

DQ23 52DQ19

53

VSS19 54VSS20

55

DQ28 56DQ24

57

DQ29 58DQ25

59

VSS21 60VSS22

61

DQS#362DM3

63

DQS3 64VSS23

65

VSS24 66DQ26

67

DQ30 68DQ27

69

DQ31 70VSS25

85

A7 86VDD5

87

VDD6 88A8

75

VDD2 76NC1

77

A15 78BA2

79

A14 80VDD3

93

VDD8 94A3

95

A2 96A1

97

A0 98VDD9

99

VDD10 100CK0

101

CK1 102CK0#

103

CK1# 104VDD11

105

VDD12 106A10/AP

107

BA1 108BA0

109

RAS#110VDD13

111

VDD14 112WE#

113

S0# 114CAS#

115

ODT0 116VDD15

117

VDD16 118A13

119

ODT1 120S1#

121

NC2 122VDD17

123

VDD18 124NCTEST

125

VREF_CA126VSS27

127

VSS28 128DQ32

129

DQ36 130DQ33

131

DQ37 132VSS29

133

VSS30 134DQS#4

135

DM4 136DQS4

137

VSS31 138VSS32

139

DQ38 140DQ34

141

DQ39 142DQ35

143

VSS33 144VSS34

145

DQ44 146DQ40

147

DQ45 148DQ41

149

VSS35 150VSS36

151

DQS#5152DM5

153

DQS5 154VSS37

155

VSS38 156DQ42

157

DQ46 158DQ43

159

DQ47 160VSS39

161

VSS40 162DQ48

163

DQ52 164DQ49

165

DQ53 166VSS41

167

VSS42 168DQS#6

169

DM6 170DQS6

171

VSS43 172VSS44

173

DQ54 174DQ50

175

DQ55 176DQ51

177

VSS45 178VSS46

179

DQ60 180DQ56

181

DQ61 182DQ57

183

VSS47 184VSS48

185

DQS#7186DM7

187

DQS7 188VSS49

189

VSS50 190DQ58

191

DQ62 192DQ59

193

DQ63 194VSS51

195

VSS52 196SA0

197

EVENT# 198VDDSPD

199

SDA 200SA1

201

SCL 202VTT1

203

VTT2204G1

@1

Trang 18

Trang 19

VDDR1(+1.35VGS) PCIE_VDDC(+0.95VGS)

"Topaz" has the following requirements with regards to power-supply sequencing to

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms

of the start of the ramp-up sequence, though a shorter ramp-up duration is

preferred The maximum slew rate on all rails is 50 mV/µ s.

It is recommended that the 3.3-V rail ramp up first.

The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 µ s

before VDDC, VDDCI, and VMEMIO start to ramp up.

The power rails that are shared with other components on the system should be

gated for the dGPU so that when the dGPU is powered down (for example

AMD PowerXpress idle state), all the power rails are removed from the dGPU.

For power down, reversing the ramp-up sequence is recommended.

VDDC/VDDCI(+VGA_CORE)

100us min.

PERSTb(GPU_RST#) REFCLK(CLK_PCIE_VGA)

VRAM ID

256Mx16

VRAM ID config Memory Type

110

4.53K 010

001

10K 3.4K

Hynix

Micron

Trang 20

11/4 change to PC sample SA000074V10

with BOM strcture control, CV1 CV8 change to 0.22uf for CZ

change the GPU PN to AMD(EXO-S3 PRO), symbol check ok

GPU_RST#

CLK_PCIE_GPU CLK_PCIE_GPU#

PCIE_PRX_C_GTX_P3

PCIE_PRX_C_GTX_N1

PCIE_PRX_GTX_P1 PCIE_PRX_GTX_N0

PCIE_PRX_GTX_N1

PCIE_PRX_GTX_P3 PCIE_PRX_C_GTX_P2

PCIE_PTX_C_GRX_P0

PCIE_PTX_C_GRX_N1

PCIE_PTX_C_GRX_N0 PCIE_PTX_C_GRX_P1

PCIE_PTX_C_GRX_P2

PCIE_PTX_C_GRX_P3

CLK_PCIE_GPU 11

PCIE_PRX_GTX_N1 8 PCIE_PRX_GTX_P1 8 PCIE_PRX_GTX_N0 8 PCIE_PRX_GTX_P0 8

PCIE_PRX_GTX_N3 8 PCIE_PRX_GTX_P3 8

PCIE_PTX_C_GRX_P1 8

PCIE_PTX_C_GRX_N1 8

PCIE_PTX_C_GRX_P0 8

PCIE_PTX_C_GRX_N0 8

PCIE_PTX_C_GRX_P2 8

PCIE_PTX_C_GRX_N2 8

PCIE_PTX_C_GRX_N3 8

PCIE_PTX_C_GRX_P3 8

VR_VGA_PWRGD 12,55

+0.95VGS

+3VGS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PCIE_REFCLKN

AK32 PCIE_REFCLKP AK30

PCIE_RX0N

AE31 PCIE_RX0P AF30

NC#R31

R31 NC#T30 T30

NC#P28

P28 NC#R29 R29

NC#N31

N31 NC#P30 P30

NC#M28

M28 NC#N29 N29

NC#L31

L31 NC#M30 M30

NC#K30

K30 NC#L29 L29

PCIE_RX1N

AD28 PCIE_RX1P AE29

PCIE_RX2N

AC31 PCIE_RX2P AD30

PCIE_RX3N

AB28 PCIE_RX3P AC29

PCIE_RX4N

AA31 PCIE_RX4P AB30

PCIE_RX5N

Y28 PCIE_RX5P AA29

PCIE_RX6N

W31 PCIE_RX6P Y30

PCIE_RX7N

V28 PCIE_RX7P W29

NC#U31

U31 NC#V30 V30

NC#U23 U23 NC#U24 U24 NC#T27 T27 NC#T26 T26 NC#T23 T23 NC#T24 T24 NC#P26 P26 NC#P27 P27 NC#P23 P23 NC#P24 P24 NC#N26 N26 NC#M27 M27

PCIE_TX1N AF28 PCIE_TX1P AG29 PCIE_TX2N AF26 PCIE_TX2P AF27 PCIE_TX3N AD26 PCIE_TX3P AD27 PCIE_TX4N AB25 PCIE_TX4P AC25 PCIE_TX5N Y24 PCIE_TX5P Y23 PCIE_TX6N AB26 PCIE_TX6P AB27 PCIE_TX7N Y26 PCIE_TX7P Y27 NC#W23 W23 NC#W24 W24 NC#U26 U26 NC#V27 V27

RV4 1K_0402_1% 1 PX@ 2

Trang 21

CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR

1 = INSTALL 10K RESISTOR

X = DESIGN DEPENDANT

NA = NOT APPLICABLE

0 = VGA controller capacity enabled

1 = The device will not be recognized as the system’ s V GAcontroller

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

Reserved

0 = Disable the external BIOS ROM device

1 = Enable the external BIOS ROM device

Reserved

X1

1

100

PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,

Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0

XPS_0[4] N/A Reserved for internal use only Must be 1 at reset 1PS_0[5] AUD_PORT_CONN_PINSTRAP[0] The LSB (least significant bit) of the strap option that indicates the number of audio-capable display outputs

PS_1[1]

PS_1[2]

STRAP_BIF_GEN3_EN_ASTRAP_BIF_CLK_PM_EN

1 = PCIe GEN3 is supported

0 = PCIe GEN3 is not supported

0 = The CLKREQB power management capability is disabledPS_1[3]

FULL_SWINGSTRAP_TX_DEEMPH_ENN/A

STRAP_BIOS_ROM_ENSTRAP_BIF_VGA_DIS

Reserved for internal use only Must be 0 at reset

0 = The transmitter half-swing is enabled

1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled

1 = Tx deemphasis enabled X

0X

PS_2[5] N/A Reserved 1PS_3[1] BOARD_CONFIG[0]

Board configuration related strapping, such as for memory ID

101 = Two usable endpoints

100 = Three usable endpoints

011 = Four usable endpoints

001 = Six usable endpoints

000 = All endpoints are usable

111= No usable endpoints

0= Disable1= Enable1= GEN3 is supported

000

011001

R_pd (Ω )

45303400

100

111101

4750

49902000

N C100005620

Note: 0402 1% resistors are required.

Connect GPIO_28 to 10K pull

001

X X X

MLPS PS_0[5:1]

PS_2[5:1]

BOM RV71=8.45k RV77=2K CV15=NC RV60=NC RV69=4.75K CV18=NC

R _ p u () R _ p d () C(nF)

Capacitor Value (nF) Bits [5:4]

68082

N C00

1101

Pull down for none OBFF design

For Topaz, RV23/RV24 stuff 100ohmFor EXO, RV23/RV24 stuff 0hm

Reserve for Topaz

with BOM strcture control, RV63,RV70 change to different value to adjust VRAM config

with BOM strcture control, when config PEG3 RV74 change to 8.45K, RV80 change to 2K

no symbol for 8pf cap, PLM has PN,change the PN

2016/09/02: Pull-down GPU_CLKREQ# at GPU side

GPIO_28_FDO

GPU_DPLUSGPU_DMINUS

+TSVDDPX_EN

GPU_GPIO0

GPU_GPIO5GPU_VID5GPU_GPIO9GPU_GPIO10

GPU_VID3

GPIO_19_CTFGPU_GPIO16

GPU_VID4GPU_GPIO22GPU_CLKREQ#_RGPU_VID1

JTAG_TDOJTAG_TDIJTAG_TRSTB

TESTEN

CEC_1

GENLK_VSYNCGENLK_CLK

PS_0

PS_3PS_1

XTALOUT

XTALIN

XTALINXTALOUT

PS_2

PLL_ANALOG_INVGA_VDDCI_SEN

GPU_GPIO17

BP_0

+VGA_CORE

GPU_SVD_RDIECRACKMON

VGA_CORE_SEN_RVGA_VSS_SEN_R

GPU_GPIO11

+VGA_CORE

GPU_GPIO11+VGA_CORE

EC_SMB_CK2 38,44

EC_SMB_DA2 38,44

VGA_AC_DET44

VGA_CORE_SEN 55VGA_VSS_SEN55

+3VGS

+3VGS+3VGS

+1.8VGS +1.8VGS

+1.8VGS+3VGS

+VDDIO_GPU+3VGS

Size Document Number R e v

@

RV131100K_0402_5%

PX@

12

RV98

TV13PAD

PX@

RV12010K_0402_5%

TOPAZ@

1 2

TV12PAD

@ 1

RV694.75K_0402_1%

PX@

61

TV15PAD

RV9416.2K_0402_1%

TV14PAD

@

RV4210K_0402_5%

PX@

34

CV19.01U_0402_16V7-K

@12

TOPAZ@

1 2

TV7PAD

@1

CV16.01U_0402_16V7-K

@12

TV6PAD

@ 1

RV9

RV772K_0402_1%

@12

RV20510K_0402_5%

@

RV20910K_0402_5%

@

RV718.45K_0402_1%

@12

@1 2

TV11PAD

@1

RV461M_0402_5%

DPC

FutureASIC/SEYMOUR/PARK

SEYMOUR/FutureASICUV1B

TS_AAE19

NC_AUX1NAD4

NC_AUX1PAD2

NC_AUX2NAD11NC_AUX2PAD13

NC_AVDDAG24NC_AVSSQAE22NC_BAH24

NC_DDC2CLKAC11NC_DDC2DATAAC13

NC_DDCVGACLKAC1NC_DDCVGADATAAC3NC#AD16AD16NC#AE16AE16

NC_GAL25

NC_SVI2#AL11AL11NC_SVI2#AJ11AJ11

NC_AVSSN#AJ25AJ25NC_RAM26

CEC_1AM12NC_SVI2#AK12AK12

NC#AM5AM5NC#AK6AK6NC#AH6AH6NC#AJ7AJ7NC#AL7AL7NC#AK8AK8

NC#AF4AF4NC#AF2AF2

NC#AM3AM3NC#AK5AK5

NC_GENLK_VSYNCAJ13NC_VDD1DIAE23

@12

RV23100_0402_5%

TOPAZ@

RV21010K_0402_5%

@

LV3BLM15PD121SN1D_2P

TOPAZ@

RV1282.2K_0402_5%

@

1 2

RV13247K_0402_5%

@

1 2

Trang 22

@

NC_DIGON AB12

NC_UPHYAB_TMDPA_TX0P AK14 NC_UPHYAB_TMDPA_TX0N AL15

NC_UPHYAB_TMDPB_TX0P AJ19 NC_UPHYAB_TMDPB_TX0N AH20

NC_UPHYAB_TMDPA_TX1P AJ15 NC_UPHYAB_TMDPA_TX1N AH16

NC_UPHYAB_TMDPA_TX2P AK16 NC_UPHYAB_TMDPA_TX2N AL17

NC_UPHYAB_TMDPA_TX3P AJ17 NC_UPHYAB_TMDPA_TX3N AH18

NC_TXOUT_L3N AK18 NC_TXOUT_L3P AL19

NC_UPHYAB_TMDPB_TX1P AK20 NC_UPHYAB_TMDPB_TX1N AL21

NC_UPHYAB_TMDPB_TX2P AJ21 NC_UPHYAB_TMDPB_TX2N AH22

NC_UPHYAB_TMDPB_TX3P AK22 NC_UPHYAB_TMDPB_TX3N AL23

NC_TXOUT_U3N AJ23 NC_TXOUT_U3P AK24 NC_VARY_BL AB11

Trang 23

GND_65 A3

GND_74 AD8 GND_75 AE7 GND_76 AG12 GND_77 AH10 GND_78 AH28 GND_79 B10 GND_80 B12 GND_81 B14 GND_82 B16 GND_83 B18 GND_66 A30

GND_84 B20 GND_85 B22 GND_86 B24 GND_87 B26 GND_88 B6 GND_89 B8 GND_90 C1 GND_91 C32 GND_92 E28 GND_93 F10 GND_67 AA13

GND_94 F12 GND_95 F14 GND_96 F16 GND_97 F18 GND_98 F2 GND_99 F20 GND_100 F22 GND_101 F24 GND_102 F26 GND_103 F6 GND_68 AA16

GND_104 F8 GND_105 G10 GND_106 G27 GND_107 G31 GND_108 G8 GND_109 H14 GND_110 H17 GND_111 H2 GND_112 H20 GND_113 H6 GND_69 AB10

GND_114 J27 GND_115 J31 GND_116 K11 GND_117 K2 GND_118 K22 GND_119 K6

GND_64

V11

NC/DP POWER

DP POWERUV1G

@

NC#AG8 AG8

NC#AG7 AG7

NC#AF6 AF6 NC#AF7 AF7

NC#AE11 AE11 NC#AF11 AF11

NC#AE1 AE1 NC#AE3 AE3 NC#AG1 AG1 NC#AG6 AG6 NC#AH5 AH5

NC#AE10 AE10

NC#AG10 AG10

NC#AG11 AG11

NC#AF8 AF8 NC#AF9 AF9

NC#AF10 AF10 NC#AG9 AG9 NC#AH8 AH8 NC#AM6 AM6 NC#AM8 AM8

NC#AE13 AE13 NC#AF13 AF13 NC_DP_VDDR#AG18

Trang 24

Reserve for GPU support +0.95VS /2A

Can change to low cost and small size MOS.Rdson<22mohm

change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122)

as DFC suggest, footprint with

V20B+

+1.35V +1.35VGS

SizeDocument Number R e vDate : Sheet o f

GD

SQV20

2N7002KW_SOT323-3

@2

GD

SQV27

RV24515K_0402_5%

SQV28

2N7002KW_SOT323-3

@2

RV1002470_0603_5%

PX@

12

LV6BLM15PD121SN1D_2P

GD

SQV11

RV166470_0603_5%

SQV192N7002KW_SOT323-3

@2

CV2130.1U_0201_25V6-K

PX@

12

GD

SQV21

2N7002KW_SOT323-3

@2

CV50233P_0402_50V8J

RF_PX@

12

CV2210.1U_0201_25V6-K

PX@

12

RV1001470_0603_5%

PX@

13

QV9AON6414AL_DFN8-5

PX@

1 2

CV330.1U_0201_6.3V6-K

@12

CV50433P_0402_50V8J

RF_PX@

12

RV1007470_0603_5%

RF_PX@

12

GD

SQV10

L2N7002KWT1G_SOT323-3

@2

QV2AO3402_SOT-23-3

RV101015K_0402_5%

PX@12

I/O

LEVE L TRANSLAT IO N

ISOLATE D CORE I/OUV1D

PCIE_VDDC_2L24PCIE_VDDC_3L25PCIE_VDDC_4L26PCIE_VDDC_5M22PCIE_VDDC_6N22PCIE_VDDC_7N23PCIE_VDDC_8N24PCIE_VDDC_9R22

NC#AB23AB23NC#AC23AC23NC#AD24AD24NC#AE24AE24NC#AE25AE25NC#AE26AE26NC#AF25AF25NC#AG26AG26

BIF_VDDC_2U21

VDDC_16V15VDDC_17V17VDDC_18V20VDDC_15V21VDDC_2N15

VDDC_19Y13VDDC_20Y16VDDC_21Y18

VDDC_7Y21VDDC_3N17VDDC_4R13VDDC_5R16VDDC_6R18

BIF_VDDC_1R21

VDDC_8T12VDDC_9T15

VDDCI_1M13VDDCI_2M15VDDCI_3M16VDDCI_4M17VDDC_23M11

VDDCI_5M18VDDCI_7M21VDDCI_6M20VDDCI_8N20

VDDC_25U11

NC_VDDR4_3

U12

VDDC_22AA12VDDC_24N12

RV1181M_0402_5%

PX@

CV411U_0402_6.3V6K

PX@

12

CV2370.1U_0201_25V6-K

PX@

12

RV123150K_0402_5%

+CV214

@12

RV91470_0603_5%

@

RV10041M_0402_5%

PX@

CV5200.1U_0201_6.3V6-K

@12

RV1006

CV50333P_0402_50V8J

RF_PX@

12

GD

SQV23

QV3AON6414AL_DFN8-5

Trang 25

DQA0_18 DQA0_16 DQA0_14 DQA0_11

DQA0_15 DQA0_13

DQA0_20 DQA0_12

DQA0_24 DQA0_22

DQA0_26

DQA0_30

DQA0_21

DQA0_25 DQA0_23

DQA0_27 DQA0_29 DQA0_31

DQA1_8

DQA1_14 DQA1_11

DQA1_17 DQA1_12

DQA1_1

DQA1_9 DQA1_4

DQA1_16

DQA1_0

DQA1_6 DQA1_3

DQA1_10 DQA1_7 DQA1_5

DQA1_18

DQA1_27 DQA1_23 DQA1_26 DQA1_21

DQA1_28

DQA1_20

DQA1_24

DQA1_29 DQA1_25 DQA1_22

DQA1_30 DQA1_19

DQA1_31

ADBIA0

RASA#1

CASA#1 CSA0#_0

CSA1#_0

CKEA1

WEA#1

WCKA1#_1 WCKA1_1 WCKA1#_0 WCKA0#_1 WCKA0_1 WCKA1_0 WCKA0#_0 WCKA0_0

DDBIA1_3 DDBIA1_1 DDBIA0_2 DDBIA0_0 EDCA1_3 EDCA1_1 EDCA0_2 EDCA0_0

MAA0_4 MAA0_2 MAA0_0

MAA0_8 MAA0_6

MAA1_4 MAA1_2 MAA1_0

MAA1_8 MAA1_6

CLKA0 CLKA#0 CLKA1 CLKA#1

CSA1#_0 27

CKEA0 26 CKEA1 27 WEA#0 26 WEA#1 27

ADBIA1 27

CLKA1 27 CLKA#1 27

CLKA0 26 CLKA#0 26

DQA1_[31 0] 27

MAA1_[8 0] 27

WCKA0_0 26 WCKA0#_0 26 WCKA0_1 26 WCKA0#_1 26 WCKA1_0 27 WCKA1#_0 27 WCKA1_1 27 WCKA1#_1 27 EDCA0_0 26 EDCA0_1 26 EDCA0_2 26 EDCA0_3 26 EDCA1_0 27 EDCA1_1 27 EDCA1_2 27 EDCA1_3 27 DDBIA0_0 26 DDBIA0_1 26 DDBIA0_2 26 DDBIA0_3 26 DDBIA1_0 27 DDBIA1_1 27 DDBIA1_2 27 DDBIA1_3 27 +1.35VGS

+1.35VGS

PX@

CV157 1U_0402_6.3V6K PX@

1

2

CV154 1U_0402_6.3V6K PX@

1

2

CV147 120P_0402_50V8-J PX@

CKEA0 K20 CKEA1 J17

CLKA0 H26 CLKA0B H25 CLKA1 G9 CLKA1B H9

CSA0B_0 H22 CSA0B_1 J22 CSA1B_0 G13 CSA1B_1 K13

ADBIA0/ODTA0 L18 ADBIA1/ODTA1 K16

RASA0B G22 RASA1B G17

WEA0B G25 WEA1B H10 DRAM_RST

MAA1_0/MAA_8 J14 MAA1_1/MAA_9 K14 MAA1_2/MAA_10 J11 MAA1_3/MAA_11 J13 MAA1_4/MAA_12 H11 MAA1_5/MAA_BA2 G11 MAA1_6/MAA_BA0 J16 MAA1_7/MAA_BA1 L15

WCKA0_0/DQMA0_0 E32 WCKA0B_0/DQMA0_1 E30 WCKA0_1/DQMA0_2 A21 WCKA0B_1/DQMA0_3 C21 WCKA1_0/DQMA1_0 E13 WCKA1B_0/DQMA1_1 D12 WCKA1_1/DQMA1_2 E3 WCKA1B_1/DQMA1_3 F4 EDCA0_0/QSA0_0 H28 EDCA0_1/QSA0_1 C27 EDCA0_2/QSA0_2 A23 EDCA0_3/QSA0_3 E19 EDCA1_0/QSA1_0 E15 EDCA1_1/QSA1_1 D10 EDCA1_2/QSA1_2 D6 EDCA1_3/QSA1_3 G5 DDBIA0_0/QSA0_0B H27 DDBIA0_1/QSA0_1B A27 DDBIA0_2/QSA0_2B C23 DDBIA0_3/QSA0_3B C19 DDBIA1_0/QSA1_0B C15 DDBIA1_1/QSA1_1B E9 DDBIA1_2/QSA1_2B C5 DDBIA1_3/QSA1_3B H4

MAA0_8/MAA_13 G20

MAA1_8/MAA_14 G14 MAA0_9/MAA_15 L17

MAA1_9/RSVD L16

RV58 4.99K_0402_1%

Trang 26

DDBIA0_0DDBIA0_2EDCA0_2

CLKA#0CKEA0

RASA#0CASA#0

CSA0#_0WEA#0CLKA0

DRAM_RSTVREFC_A0VREFD2_A0ADBIA0

MAA0_4MAA0_2

MAA0_8

MAA0_0MAA0_7

DQA0_6

DQA0_1DQA0_7

DQA0_0DQA0_4DQA0_5

DQA0_2

DQA0_18

DQA0_23DQA0_22

WCKA0_0WCKA0#_0

DQA0_31

DQA0_26DQA0_25DQA0_27DQA0_24DQA0_30

MAA0_8MAA0_0MAA0_7

MAA0_2MAA0_4

MAA0_6

DQA0_9DQA0_10DQA0_8

DQA0_12DQA0_13DQA0_14

DQA0_11

WCKA0_1WCKA0#_1

WCKA0_0WCKA0#_0

EDCA0_1EDCA0_3

DDBIA0_1DDBIA0_3

CASA#0RASA#0

CLKA0CKEA0CLKA#0

WEA#0CSA0#_0

DRAM_RST

VREFD1_A0VREFC_A0ADBIA0

VREFD1_A0

VREFD2_A0

VREFC_A0

DDBIA0_025DDBIA0_225

EDCA0_025EDCA0_225

ADBIA025

DRAM_RST25,27

WEA#025CSA0#_025

WCKA0_125

MAA0_[8 0] 25DQA0_[31 0] 25

EDCA0_125

WCKA0#_025WCKA0_025

WCKA0#_125

RASA#025

EDCA0_325

CKEA025CLKA#025CLKA025

CASA#025

+1.35VGS

+1.35VGS+1.35VGS

+1.35VGS

+1.35VGS+1.35VGS

@1

2

CV56233P_0402_50V8JRF_PX@1

2

CV5231U_0402_6.3V6K

@1

VSSQ3 E1VSS12

VSSQ4 N1VSSQ5 R1

VDDQ8 L2VDDQ9 B3

G1

VSS7

B10T5 VSS6VSS5

L5 VSS4G5 VSS3B5 VSS2

VSSQ10 C3VSSQ11 E3VSSQ12 N3VSSQ13 R3VSSQ14 U3VSSQ15 C4VSSQ16 R4VSSQ17 F5VSSQ18 M5VSSQ19 F10VSSQ20 M10VSSQ21 C11VSSQ22 R11VSSQ23 A12VSSQ24 C12VSSQ25 E12VSSQ26 N12VSSQ27 R12VSSQ28 U12VSSQ29 H13VSSQ30 K13VSSQ31 A14VSSQ32 C14VSSQ33 E14VSSQ34 N14VSSQ35 R14VSSQ36 U14

VSSQ3 E1VSS12

VSSQ4 N1VSSQ5 R1

VDDQ8 L2VDDQ9 B3

G1

VSS7

B10T5 VSS6VSS5

@1

Trang 27

MF=0 No Mirror MF=1 Mirror

UV7 SIDE

CLKA1CLKA#1

WCKA1_0WCKA1#_0

WCKA1_1WCKA1#_1

EDCA1_3EDCA1_0

DDBIA1_0DDBIA1_3

CASA#1RASA#1

CLKA#1CKEA1CLKA1

WEA#1CSA1#_0

DQA1_29DQA1_26DQA1_24DQA1_30

DQA1_0

DQA1_7DQA1_6DQA1_3

VREFD2_A1ADBIA1

DRAM_RSTVREFC_A1

MAA1_2MAA1_4

MAA1_7MAA1_0MAA1_8VREFD2_A1

VREFD1_A1

VREFC_A1

VREFD2_A1VREFC_A1ADBIA1

DRAM_RST

DQA1_16DQA1_19

DQA1_21DQA1_20

MAA1_3

MAA1_0MAA1_5

MAA1_7MAA1_8

DQA1_15DQA1_14

DQA1_13DQA1_12DQA1_11

DQA1_9DQA1_8DQA1_10

WCKA1_1WCKA1#_1

WCKA1_0WCKA1#_0

EDCA1_1EDCA1_2

DDBIA1_1DDBIA1_2

CASA#1RASA#1

CKEA1CLKA#1CLKA1

WEA#1CSA1#_0

EDCA1_025

EDCA1_325

WCKA1#_125WCKA1_125

EDCA1_225EDCA1_125

WCKA1#_025WCKA1_025

RASA#125CASA#125

WEA#125

CLKA125CLKA#125CKEA125

DRAM_RST25,26

ADBIA125

CSA1#_025

DQA1_[31 0] 25MAA1_[8 0] 25

+1.35VGS

+1.35VGS+1.35VGS

+1.35VGS

+1.35VGS+1.35VGS

@1

PX@

CV5321U_0402_6.3V6K

@1

2

CV5291U_0402_6.3V6K

@1

2

170-BALLSGRAM GDDR5

VSSQ3 E1VSS12

VSSQ4 N1VSSQ5 R1

VDDQ8 L2VDDQ9 B3

G1

VSS7

B10T5 VSS6VSS5

VSSQ3 E1VSS12

VSSQ4 N1VSSQ5 R1

VDDQ8 L2VDDQ9 B3

G1

VSS7

B10T5 VSS6VSS5

@1

Trang 28

LCD POWER CIRCUIT B+ to +LEDVDD POWER

2A 80 mil 2A 80 mil

C23 0.1u for G HSW panel blink issue

EMC

APL SoC output enable Voh min is 1.8V-0.45V=1.35V

AUX do NOT reserve pull high and pull low for eDP panel

W=60mils

For RF request: keep 0402

For EMI Close to R5

W=40mils W=40 mils

Need Short

For ESD For EMI

Touch Screen

ENBKLDISPOFF#

USB20_P6USB20_N6

EDP_TX0+

CPU_EDP_TX0+

CPU_EDP_TX0-

CPU_EDP_TX1-

INVT_PWMDISPOFF#

USB20_P6

EDP_AUX#

EDP_AUX

USB20_N2_CONNUSB20_P2_CONN

USB20_P611USB20_N611

CPU_EDP_TX0+

6CPU_EDP_TX0-6CPU_EDP_TX1+

6CPU_EDP_TX1-6CPU_EDP_AUX6CPU_EDP_AUX#

6

CPU_EDP_HPD6

USB20_P211USB20_N211

+3VS

+LEDVDD

+LCDVDD_CON+3VS

+3VS

+3VS_CMOS

V20B+

+LEDVDD+LCDVDD_CON

+3VS

+3VS_CMOS+3VS_CMOS_R

+5VS_TS+5VS

+5VS_TS

1

2 2

3 34

5

6

6R28 2TS@ 1 0_0402_5%

R16100K_0402_5%

C90.01U_0201_6.3V7-K

@1

2

C1320.047U_0201_6.3V6KEMC_NS@

2R19 1 @ 20_0402_5%

C16 2 1 0.1U_0201_6.3V6-K

R210_0402_5%

1

2

C21 2 1 0.1U_0201_6.3V6-K

R35100K_0402_5%

4

R104.7K_0402_5%

@

R20100K_0402_5%

@

13

2

Trang 29

For C_VBUS power switch OCP pin

Rp configuration

1 0 1

0 R3144/R3142 mount

Rp:900mA

Rp:1.5A

Rp:3.0A

Note R3139/R3143 mount Rp:1.5A (now)

Power switch enable pin

R3146 mount Low Active

Close Pin19

Close Pin13

Equalizer control and program for channel A 3.3V tolerant Internally pulled down at ~150K[A_EQ1, A_EQ0] ==

LL: program EQ for channel loss up to 9.5dB(default) LH: program EQ for channel loss up to 13dB HL: program EQ for channel loss up to 4.5dB

Programmable output de-emphasis level setting for channel A 3.3V tolerant Internally pulled down at ~150K[A_DE1, A_DE0] ==

LL: 3.5dB de-emphasis (default) LH: No de-emphasis HL: 2.7dB de-emphasis HH: 5dB de-emphasis Equalizer control and program for channel B 3.3V tolerant Internally pulled down at ~150K[B_EQ1, B_EQ0] ==

LL: program EQ for channel loss up to 9.5dB(default) LH: program EQ for channel loss up to 13dB HL: program EQ for channel loss up to 4.5dB

Programmable output de-emphasis level setting for channel B3.3V tolerant Internally pulled down at ~150K[B_DE1, B_DE0] ==

LL: 3.5dB de-emphasis (default) LH: No de-emphasis HL: 2.7dB de-emphasis HH: 5dB de-emphasis LFPS swing adjust

3.3V tolerant Internally pulled down at ~150KΩTEST==

L: Normal LFPS swing(default)H:Turn down LFPS swing

09/02 Update Type-C Conn DC021608291 wei

3A

ILIM (A)=6800/R9426 (Ω )

C_RX2_N_CC_RX2_P_C

USB30_TX_P0_C

USB30_RX_N0_CUSB30_RX_P0_C

VBUS_ENTYPE_C_OCP#

C_RX1_PC_RX1_N

C_RX1_P_CC_RX1_N_C

USB30_TX_N0_U

USB30_RX_N0_UUSB30_RX_P0_U

USB_EQ0_BUSB_EQ1_B

USB_DE0_B

USB_EQ0_AUSB_EQ1_A

C_TX1_P_C

C_RX2_N_CC_TX1_N_C

C_RX2_P_C

C_DMC_DPCC1

C_TX2_P_C

C_RX1_P_CC_RX1_N_C

CC2C_DMC_DP

C_TX2_N_C

C_TX2_P_C C_TX2_P_C

C_RX1_P_CC_RX1_N_C

C_TX1_P_C C_TX1_P_C

C_RX2_P_CC_RX2_N_CC_RX2_N_C

C_RX2_P_C

C_DMC_DP

USB30_TX_P0_RUSB30_TX_N0_RUSB30_RX_P0_RUSB30_RX_N0_R

USB30_TX_P0USB30_TX_N0USB30_RX_P0

USB30_TX_P0_MUSB30_TX_N0_MUSB30_RX_P0_M

CC1CC2

C_DPC_DM

TYPE_C_OCP# 11

USB30_RX_N0 11USB30_RX_P0 11USB30_TX_P0

11

USB30_TX_N0

11

USB20_N011USB20_P011

VBUS_P0+3VS

+3VS+3VS

@1

2C21347U_0805_6.3V6-M @1

2

RW311 @ 20_0402_5%

TP52

@1

CW38 0.1U_0201_6.3V6-K

R467410K_0402_5%

@

EXC24CH900U_4PEMC_NS@

1 234

CC214

C_TX1_1P/2N8C_TX1_1N/2P9

VCON_IN13

C_RX2_1N/2P1C_RX2_1P/2N24

CC112

C_TX2_1P/2N11C_TX2_1N/2P10

@1

R47141@ 20_0201_5%

C20741@ 20.1U_0201_6.3V6-K

D50AZC199-02S.R7G_SOT23-3EMC_NS@

RW304.99K_0402_1%

@

CW33.1U_0402_10V6-K

@1

2

R31506.2K_0402_1%

2

R314210K_0402_5%

1 234

8

7

5

321

9 10D36

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

41

627

3

98

9 10D20

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

41

627

3

98

2

CC1271220P_0201_25V7-K

@12

B_DE0_I2C_ADDR03B_EQ0_NC2

B_INn

8 B_INp

9

B_OUTp22B_OUTn23B_EQ1_I2C_ADDR14

U6

SY6861B1ABC_SOT23-6

@

OUT 1GND 2OCB 3IN

2

RW191 @ 24.7K_0402_5%

L25

12

2

CC1272220P_0201_25V7-K

@12

L24

12

3 4

R314910K_0402_1%

Tiêu đề	Lc Future Center Secret Data
Trường học	LC Future Center
Chuyên ngành	Engineering
Thể loại	engineering drawing
Năm xuất bản	2017
Thành phố	Cairo

Định dạng
Số trang	58
Dung lượng	4,43 MB