Compal D4PB1 D5PB1 LA f241p rev 1 0 схема

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.THIS SHEET OF ENGINEERING DRAWIN

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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WLAN+BT+Wigig (Combo)

USBx8

port 11,12

SATA HDD Conn

page 38

port 6,8

port 0

PCIE/SATA SSD NGFF Card

page 38

TPM NPCT650

page 31

WLAN Module for BT

page 6~17

page 22

DP to VGA RTD2168

SM BUS

HP MIC LINE IN

page 37

DOCK CONN.

page 30

Combo Jack (CTIA)

ALC3225

HDA Codec

LS-B732P TP/B

page 38

Processor

Skylake U/Kabylake U PCH-LP(MCP) SKL-U_2+2, KBL-U2+2, KBL-U4+2

Intel Skylake U/Kabylake U

Dual Core + GT2

15W 1356pin BGA

page 24 page 25

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BOM Structure Table

0x31 - 0x3B 0.691 V 0.702 V 0.713 V

0x3C - 0x46 0.807 V 0.819 V 0.831 V

0x47 - 0x54 0.978 V 0.992 V 1.006 V

0x55 - 0x64 1.169 V 1.185 V 1.200 V

ON +0.6VS_VTT DDR +0.6VS power rail for DDR terminator

+1.8VALW_PRIM +1.8V Always power rail

+1.2V_VDDQ

ON ON +VCC_CORE

Voltage Rails +19V_VIN

+19VB

Adapter power supply

AC or battery power rail for power circuit.

Processor IA Cores Power Rail

Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.

S0

ON ON

N/A

N/A Power Plane Description

+VCC_GT Processor Graphics Power Rails +17.4V_BATT Battery power supply N/A

S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

ON ON ON

ON

OFF OFF OFF

OFF OFF OFF OFF OFF

LOW LOW

HIGH HIGH

Power State

+1.0VALW_PRIM +1.0V Always power rail ON Board ID Table for AD channel

+1.8VS System +1.8V power rail ON

+VCC_SA System Agent power rail

VGA@

dGPU

BOM Option Table

X76OBRAM@

CONN@

Connector

BOM Option Table

43 level BOM table

VRAM BOM Select X76@

I2C Address Table

SR@/DR@

(DR@ is not been used

in this project) Single/Dual Rank

+1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON

+1.0V_VCCSTU Sustain voltage for processor in Standby modes ON

+3VLP +19VB to +3VLP power rail for suspend power ON +3VALW System +3VALW always on power rail ON

+5VS System +5V power rail

+5V Always power rail

ON

ON +1.05VSDGPU +1.05VS power rail for GPU

+3VSDGPU_AON +3VS power rail for GPU(AON rails) ON +3VSDGPU_MAIN +3VS power rail for GPU GC62.0 ON +1.5VSDGPU +1.5VS power rail for GPU ON

+VGA_CORE Core power for descrete GPU ON

SMT MB AD301 B4DBG QJFC 2.3G UMA HDMI SMT MB AD301 B4DBG QJ8M 2.4G UMA HDMI SMT MB AD301 B4DBG QJKP 2.3G DIS HDMI SMT MB AD301 B4DBG QJKK 2.5G DIS HDMI

S3 S4/S5

OFF

N/A N/A

ON ON

OFF

ON

OFF OFF

ON ON

ON

OFF

ON ON*1

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

0.1

Power Map

E

4 54 Friday, June 09, 2017 2017/02/22 2018/02/22 Compal Electronics, Inc.

LA-F241P

Title

Si ze Document Number R e v Date: Sheet o f Security Classification Compal Secret Data

0.1

Power Map

E

LA-F241P

Title

Si ze Document Number R e v Date: Sheet o f Security Classification Compal Secret Data

0.1

Power Map

E

LA-F241P

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SPOK

+3VALW PBTN_OUT#

+VCCPRIM_CORE +1.8VALW_PG +1.8VALW_PRIM

EC_VCCST_PG

+0.6VS_VTT

VR_PWRGD

VR_ON +1.5VS

PCH_PWROK

H_CPUPWRGD

+VCC_CORE PLT_RST#

C4PB1/C5PB1 Power OFF sequence

89.6us26.8us26.8us465.6us

465.6us

5s

29.2us

31.98us23.84us

71.68us

68.48us39.12us

23.84us

6.94us

8.904s4.108ms

78us

4.108ms

4.294ms

000

29us

29us0130us

+VCC_SA +0.6VS_VTT

23.61ms245.3us

35.68us33.04us

68.8us

1.632ms

20.424ms20.424ms245.3us

20.09ms20.09ms2.205ms32.4us

32.4us

32.4us20.8us28.2us

22.04ms30.44ms376.8us

133.6ms

653.6us143.5ms475.2us

0

Resum OFF

Title

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PS8338 HDMI DDC

Rev_0.53

DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):

DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):

(Sampled:Rising edge of PCH_PWROK)

Display Port B/C/D Detected

0 =Port is not detected.

1 =Port is detected

Functional Strap Definitions

PDG0.9 P.771 PROC_POPIRCOMP/PCH_OPIRCOMP

PD 50ohm

#543016 PDG0.9 P.775

#544669 CRB RVP7 1.0 EDRAM_OPIO_RCOMP/EOPIO_RCOMP PD50ohm

AR HDMI DDC

#545659 PCH EDS 0.7 P.108 SCI capability is available on all GPIOs, while NMI and SMI capability is available on selected GPIOs only.

Below are the PCH GPIOs that can be routed to generate SMI# or NMI:

Trace width= 0 mils,Spacing= 5mil,Max length=100mils

COMPENSATION PU FOR eDP

#54 016 PDG0.9 P.75

PH 1K to VCCST

CPU over 1 0 degree will output low force S0->S5

Reserved for ESD 2014/9/17

EC_SCI# SOC internal PU

Place to CPU side

Follow 544924_Skylake_EDS_Vol_1_Rev_0.93

Place to CPU side

PS8338

follow INTEL check list to reserve D63 test point

use for iAMT Test

EDP_COMP

SOC_DP1_AUXNSOC_DP1_AUXP

SOC_DP1_HPDCPU_HDMI_HPD

EC_SCI#

CPU_EDP_HPD

ENBKLSOC_BKL_PWMSOC_ENVDDSOC_DP1_CTRL_DATA

H_PECI

CPU_POPIRCOMPPCH_OPIRCOMPEDRAM_OPIO_RCOMPEOPIO_RCOMP

CPU_XDP_TCK0

SOC_XDP_TMSSOC_XDP_TRST#

SOC_XDP_TDISOC_XDP_TDO

CPU_XDP_TCK0SOC_XDP_TMSSOC_XDP_TRST#

PCH_JTAG_TCK1SOC_XDP_TDISOC_XDP_TDO

H_PROCHOT#_RH_THERMTRIP#

SOC_DP2_AUXNSOC_DP2_AUXP

TBT_DP1_CTRL_CLKTBT_DP1_CTRL_DATA

DDI2_CTRL_DATADDI2_CTRL_CK

RC2450_0402_5%

@

RC31K_0402_5%

1 OF 20UC1A

SKL-U_BGA1356

@

DDI1_AUXN G50DDI1_AUXP F50

EDP_RCOMP

E52

EDP_AUXN E45EDP_AUXP F45EDP_DISP_UTIL B52

EDP_TXN[0] C47EDP_TXN[1] D46EDP_TXN[2] A45EDP_TXN[3] A47

EDP_TXP[0] C46EDP_TXP[1] C45EDP_TXP[2] B45EDP_TXP[3] B47

GPP_E13/DDPB_HPD0 L9GPP_E14/DDPC_HPD1 L7GPP_E15/DDPD_HPD2 L6GPP_E16/DDPE_HPD3 N9GPP_E17/EDP_HPD L10

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#543016 PDG0.9 P.117 W=12-15 Space= 20/25 L=500mil

#543016 PDG0.9 P.163 RC place near SODIMM

DDR_VTT_CNTL to DDRVTT supplied ramped

<35uS(tCPU18)

Reserve for cost test.

DDR_A_D61DDR_A_D55DDR_A_D52

DDR_A_D7

DDR_A_D13DDR_A_D8

DDR_A_D15DDR_A_D11

DDR_A_D18

DDR_A_D22

DDR_A_D29

DDR_A_D20DDR_A_D16

DDR_A_D25

DDR_A_D47DDR_A_D39

DDR_A_D33

DDR_A_D35

DDR_A_D42

DDR_A_D38DDR_A_D40

DDR_A_D34

DDR_A_D36

DDR_A_D43DDR_A_D37

DDR_A_D45DDR_A_D41

DDR_A_D46DDR_A_D44DDR_A_D32

DDR_A_ODT0

DDR_A_MA5

DDR_A_MA6

DDR_A_CLK0DDR_A_CLK#0

DDR_A_BA1DDR_A_MA10DDR_A_MA1

DDR_A_MA3

DDR_A_DQS#0DDR_A_DQS0DDR_A_DQS#1DDR_A_DQS1DDR_A_DQS#2DDR_A_DQS2DDR_A_DQS#3

DDR_A_DQS#4DDR_A_DQS3

DDR_A_DQS4DDR_A_DQS#5DDR_A_DQS5DDR_A_DQS#6DDR_A_DQS6DDR_A_DQS#7DDR_A_DQS7

DDR_B_D3

DDR_B_D8

DDR_B_D13DDR_B_D4

DDR_B_D14

DDR_B_D7

DDR_B_D10

DDR_B_D2DDR_B_D0

DDR_B_D24DDR_B_D16

DDR_B_D56

DDR_B_D60

DDR_B_D54

DDR_B_D57DDR_B_D53

DDR_B_D62DDR_B_D51

DDR_B_D61DDR_B_D58

DDR_B_MA5

DDR_B_MA6

DDR_B_MA7DDR_B_MA12

DDR_B_MA3

DDR_B_DQS#0DDR_B_DQS0DDR_B_DQS#1DDR_B_DQS1DDR_B_DQS#2DDR_B_DQS2DDR_B_DQS#3

DDR_B_DQS#4DDR_B_DQS3DDR_B_DQS4DDR_B_DQS#5DDR_B_DQS5DDR_B_DQS#6DDR_B_DQS6DDR_B_DQS#7DDR_B_DQS7

DDR_B_CLK1DDR_B_CLK#1DDR_B_CLK0

DDR_B_DQS0 <18>DDR_B_DQS#1 <18>DDR_B_DQS1 <18>DDR_B_DQS#2 <18>DDR_B_DQS2 <18>DDR_B_DQS#3 <18>DDR_B_DQS3 <18>DDR_B_DQS#4 <18>DDR_B_DQS4 <18>DDR_B_DQS#5 <18>DDR_B_DQS5 <18>DDR_B_DQS#6 <18>DDR_B_DQS6 <18>DDR_B_DQS#7 <18>DDR_B_DQS7 <18>DDR_B_MA13 <18>

DDR_B_CLK#0 <18>DDR_B_CLK0 <18>

DDR_B_CLK#1 <18>DDR_B_CLK1 <18>

+1.2V_VDDQ

Title

12

SKL-U_BGA1356

@

DDR_RCOMP[0] AR18DDR_RCOMP[1] AT18DDR_RCOMP[2] AU18DDR1_ALERT# AN43

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] BB44DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] BA44

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AP52

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY43

DDR1_CKE[0] AN56DDR1_CKE[1] AP55DDR1_CKE[2] AN55DDR1_CKE[3] AP53

DDR1_CKN[0] AN45DDR1_CKN[1] AN46DDR1_CKP[0] AP45DDR1_CKP[1] AP46

DDR1_CS#[0] BB42DDR1_CS#[1] AY42

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BA46DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AY46DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AW46

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN48DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN50

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] BA43DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AN52DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN53

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AY47

DDR1_MA[3] BB46DDR1_MA[4] BA47

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AY48DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BA48DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP48DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] BB48DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AP50

DDR1_ODT[0] BA42DDR1_ODT[1] AW42

DDR1_PAR AP43

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] AW44DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AY44

DDR1_DQSP[0]/DDR0_DQSP[2] AH65DDR1_DQSP[1]/DDR0_DQSP[3] AG70DDR1_DQSP[2]/DDR0_DQSP[6] AR65DDR1_DQSP[3]/DDR0_DQSP[7] AR60DDR1_DQSP[4]/DDR1_DQSP[2] AR38DDR1_DQSP[5]/DDR1_DQSP[3] AR32DDR1_DQSP[6] AR27DDR1_DQSP[7] AR21DRAM_RESET# AT13

SKL-U

DDR CH - A

2 OF 20UC1B

SKL-U_BGA1356

@

DDR_VREF_CA AY67DDR0_VREF_DQ AY68DDR1_VREF_DQ BA67DDR_VTT_CNTL AW67DDR0_ALERT# AW50

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AU52DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT48

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AY55

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AU48

DDR0_CKE[0] BA56DDR0_CKE[1] BB56DDR0_CKE[2] AW56DDR0_CKE[3] AY56

DDR0_CKN[0] AU53DDR0_CKN[1] AU55DDR0_CKP[0] AT53DDR0_CKP[1] AT55

DDR0_CS#[0] AU45DDR0_CS#[1] AU43

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AY50DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] BB50DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AT50

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA54DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AW54

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU46DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AY54DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# BA55

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AY51

DDR0_MA[3] BA50DDR0_MA[4] BB52

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BA51DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] BA52DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AW52DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AY52DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BB54

DDR0_ODT[0] AT45DDR0_ODT[1] AT43

DDR0_DQSP[0] AM69DDR0_DQSP[1] AT70DDR0_DQSP[2]/DDR0_DQSP[4] AY64DDR0_DQSP[3]/DDR0_DQSP[5] BA60DDR0_DQSP[4]/DDR1_DQSP[0] AY38DDR0_DQSP[5]/DDR1_DQSP[1] BA34DDR0_DQSP[6]/DDR1_DQSP[4] AY30DDR0_DQSP[7]/DDR1_DQSP[5] BA26

@1

3

RC162M_0402_5%

@

Trang 8

SOC_SPI_IO2_0_R SOC_SPI_CLK_0_R

SOC_SPI_SI_0_RSOC_SPI_SO_0_R

SOC_SPI_CS#0

SOC_SPI_SI_0_RSOC_SPI_IO3_0_RSOC_SPI_SO_0_R

SOC_SPI_IO2

SOC_SPI_IO2_0_R

SOC_SPI_CLKSOC_SPI_SISOC_SPI_SO

EC_KBRST#_RTPM_SERIRQ

SOC_SML1ALERT#

SOC_SML0CLKSOC_SML0DATASOC_SML1CLK_1SOC_SML1DATA_1

SOC_SMBCLK_1SOC_SMBDATA_1

SOC_SML0ALERT#

ESPI_CLKCK_LPC_TPM_RPM_CLKRUN#

LPC_FRAME#

LPC_AD2LPC_AD0LPC_AD3LPC_AD1

ESPI_RST#

SOC_SML0CLKSOC_SML0DATAPM_CLKRUN#

SOC_SMBCLK_1SOC_SMBDATA_1

SOC_SPI_IO3SOC_SPI_IO3_0_R

SOC_SPI_SISOC_SPI_SI_0_R

SOC_SPI_CLKSOC_SPI_CLK_0_R

SOC_SPI_SOSOC_SPI_SO_0_R

SOC_SMBDATASOC_SMBCLK

SOC_SML1CLK_1SOC_SML1DATA_1

SOC_SML1DATASOC_SML1CLK

SOC_SML1DATA_1SOC_SML1CLK_1

TBT_CIO_PLUG_EVENT#

TBT_FORCE_PW R

SOC_SML1CLKSOC_SML1DATA

+3VS+3VS+3VALW _PRIM

Title

@EMC@

RC240_0402_5%

1

RC491<BOM Structure>2 499_0402_1%

RC2471 <BOM Structure>2 2.2K_0402_5%

Q2018BME2N7002D1KW -G 2N SOT363-6

GPP_A1/LAD0/ESPI_IO0 AY13GPP_A2/LAD1/ESPI_IO1 BA13GPP_A3/LAD2/ESPI_IO2 BB13GPP_A4/LAD3/ESPI_IO3 AY12GPP_A5/LFRAME#/ESPI_CS# BA12GPP_A14/SUS_STAT#/ESPI_RESET# BA11GPP_A9/CLKOUT_LPC0/ESPI_CLK AW9GPP_A10/CLKOUT_LPC1 AY9GPP_A8/CLKRUN# AW11

3

GND

4

VCC 8HOLD#

RC481 @ 2 1K_0402_1%

RC144 1 @ 2 0_0402_5%

Q2017BME2N7002D1KW -G 2N SOT363-6

SB00000SA00

Trang 9

SPKR / GPP_B14 (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. -> AAX05 Use

1 = Enable TOP Swap Mode.

#54 016 PDG0.9 P 1 Terminat i ng Unus ed S DI O/S DXC Si gnal s SDIO signals are mult i pl exed w i t h GPI Os and default to GPIO funct i onali t y ( as i nput) If SDIO interface is not used, the signals can be used as GPIOs instead If the GPIO funct i onali t y i s al s o not us ed, t he si gnal s can be l e ft as no- c onnect.

DGPU_PRSNT#

UMA

DIS,Optimus

1 0 GPIO67

HDA for AUDIO

HDA_BIT_CLKHDA_SYNC

HDA_RST#

HDA_SDIN0HDA_SDOUT

HDA_SDOUT

HDA_SDIN0

HDA_BIT_CLKHDA_RST#

RF@

12

SKL-UAUDIO

R52530_0402_5%

GPP_F13/EMMC_DATA0 AP2GPP_F14/EMMC_DATA1 AP1GPP_F15/EMMC_DATA2 AP3GPP_F16/EMMC_DATA3 AN3GPP_F17/EMMC_DATA4 AN1GPP_F18/EMMC_DATA5 AN2GPP_F19/EMMC_DATA6 AM4GPP_F20/EMMC_DATA7 AM1GPP_F21/EMMC_RCLK AM2GPP_F22/EMMC_CLK AM3GPP_F12/EMMC_CMD AP4EMMC_RCOMP AT1

RC77 0_0402_5%

@

RC13410K_0402_5%

VGA@

RC13310K_0402_5%

Trang 10

#543016 PDG0.9 P.526 PROCPWRGD is used only for power sequence debug and is not required to be connected to anything on the platform.

WAKE# (DSX wake event)

10 KΩ pull- up t o Vcc DS W The pull-up is required even if PCIe* interface is not used on the plat f or m

LAN WAKE: LAN Wake Indicator from the GbE PHY.

Reserved for ESD 2014/9/17

Follow 2014MOW48 Skylake U PU 2.7k ohm to 1V Cannonlake U PD 60.4 ohm

2014MOW48:

Skylake U use 24M 50 ohm ESR

Cannonlake U use 38.4M 30 ohm ESR

Change PN to SJ10000PW00

AR

CR WIGIG

2017/4/18 for MB Fieldlesson learnt ESD request

Close to UC1

CLKREQ_PCIE#0

SOC_XTAL24_IN_RSOC_XTAL24_OUT_R

EC_RSMRST# PCH_DPW ROKH_CPUPW RGD

EC_VCCST_PG

SYS_PW ROKPCH_PW ROKPCH_DPW ROKSUSPW RDNACKSUSACK#

PM_BATLOW #PM_BATLOW #

PBTN_OUT#_RSOC_VRALERT#

CLKREQ_PCIE#4

CLKREQ_PCIE#1CLK_PCIE_P1CLK_PCIE_N1

CLKREQ_PCIE#2CLK_PCIE_N2CLK_PCIE_P2

CLKREQ_PCIE#5

SOC_XTAL24_INSOC_XTAL24_OUT

SOC_RTCX2SOC_SRTCRST#

SOC_RTCRST#

CLKREQ_PCIE#1CLKREQ_PCIE#2CLKREQ_PCIE#3

EC_RSMRST#

LAN_PME#

CLKREQ_PCIE#4CLKREQ_PCIE#5

PBTN_OUT#_R

PCH_PW ROKSYS_PW ROK

SOC_RTCX1SOC_RTCX2CLKREQ_PCIE#3

CLK_PCIE_N3

CLK_PCIE_CARDCLK_PCIE_CARD#

SUSCLK

LAN_DISABLE_N

CLK_PCIE_N5CLK_PCIE_P5

SOC_XTAL24_OUTSOC_XTAL24_IN

T86

@

RC1131K_0402_5%

CC158.2P_0402_50V8D

1

2

UC3MC74VHC1G08DFT2G_SC70-5

@EMC@

12

RC2510_0201_5%

U22@

CC51.1U_0402_16V7K

@EMC@

12

RC931 2 20K_0402_5%

T95 @

YC124MHZ_12PF_7V24000020

Trang 11

SPKR / GPP_B14 (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. -> AAX05 Use

1 = Enable TOP Swap Mode.

GSPI0_MOSI /GPP_B18 (Internal Pull Down):

(Rising edge of PCH_PWROK)

No Reboot

0 = Disable No Reboot mode > AAX05 Use

1 = Enable No Reboot Mode (PCH will disable the TCO

Timer system reboot feature) This function is useful

when running ITP/XDP.

GSPI1_MOSI / GPP_B22 (Internal Pull Down):

(Rising edge of PCH_PWROK)

Boot BIOS Strap Bit

0 = SPI Mode > AAX05 Use

1 = LPC Mode

SML0ALERT# / GPP_C5 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# )

eSPI or LPC

0 = LPC is selected for EC > For KB9022/9032 Use

1 = eSPI is selected for EC > For KB9032 Only.

SMBALERT# / GPP_C2 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# )

TLS Confidentiality

0 = Disable Intel ME Crypto Transport Layer Security

(TLS) cipher suite (no confidentiality).

1 = Enable Intel ME Crypto (TLS) (with confidentiality)

Must be pulled up to support Intel AMT with TLS and Intel

SBA (Small Business Advantage) with TLS.

HDA_SDO/I2S_TXD0 (Internal Pull Down):

(Sampled: Rising edge of PCH_PWROK ) Flash Descriptor Security Override

0 = Enable security measures defined in the Flash Descriptor

1 = Disable Flash Descriptor Security (override) This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY

DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):

DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):

(Sampled:Rising edge of PCH_PWROK) Display Port B/C/D Detected

0 =Port D is not detected.

*

1 1

B4DBU+VPRO

Project_ID0 Project_ID1

Reserved B4DBU+NVPRO

VGA_ID

1

0 GM GL

RANK_ID SR DR

GPP_D9

0 1 GPP_D10

NFC_DFU follow PDG 1.3

DGPU_AC_DETECT

D4PB1/D5PB1Change to

On Borad Ram ID Page.19

NFC_DFU

EC_LID_OUT#

GSPI1_MOSI

UART_2_CTXD_DRXDUART_2_CRTS_DCTS

I2C_2_SDAI2C_2_SCLI2C_3_SDAI2C_3_SCLI2C_4_SDAI2C_4_SCL

SOC_GPIOD13SOC_GPIOD16

ISH_I2C0_SDAISH_I2C0_SCL

DGPU_HOLD_RST#

DGPU_PWR_EN

UART_2_CTXD_DRXDUART_2_CRXD_DTXD

UART_2_CRTS_DCTSUART_2_CCTS_DRTS

I2C_5_SDAI2C_5_SCL

ISH_I2C1_SCLISH_I2C1_SDA

G_INTRAM_FLAG1ALS_INT#

ISH_I2C1_SCLISH_I2C1_SDA

ISH_I2C0_SDAISH_I2C0_SCL

SOC_GPIOD15

PROJECT_ID1

VGA_IDRANK_ID

PROJECT_ID0

PROJECT_ID1VGA_ID

RANK_ID

I2C_0_SCLI2C_0_SDA

I2C_1_SCLI2C_1_SDA

Title

T3819@

RC1770_0402_5%2ESPI@ 1

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U1GPP_D16/ISH_UART0_CTS#/SML0BALERT# U4GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U2

GPP_D15/ISH_UART0_RTS# U3

GPP_D5/ISH_I2C0_SDA M4GPP_D6/ISH_I2C0_SCL N3GPP_D7/ISH_I2C1_SDA N1GPP_D8/ISH_I2C1_SCL N2GPP_D9 P2

GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD11GPP_F11/I2C5_SCL/ISH_I2C2_SCL AD12

Trang 12

Camera HDD

#543016 P.239 PCIE_RCOMPN/PCIE_RCOMPP

BO=4 W=12 S=12 R=100ohm

DEVSLP[2:0] ImplementationDEVSLP is a host-controlled hardware signal which enables a SATA host and device to enter an ultra-low interface power state, including the possibility to completely power down host and device PHYs

The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U

When high, DEVSLP requests the SATA device to enter into the DEVSLP power state

‧When low, DEVSLP requests the SATA device to exit from the DEVSLP power state

‧and transition to active state

SATA General Purpose (SATAGP[2:0]) SignalsThe processor provides three SATA general purpose input signals,SATAGP[2:0] for SKL U

‧These signals can be configured as interlock switch inputs corresponding to a given SATA port When used as an interlock switch status indication, this signal should be driven to 0

‧

to indicate that the switch is closed and to a 1 to indicate that the switch is open

If mechanical presence switches will not be used on the platform, SATAGP[2:0]

‧signals can be configured as GPP_E[2:0] GPIOs signals

Acer HSIO def i ne

NGFF WLAN+BT(Key E)

GLAN

AG3,AG4 PD1K for DCI (follow PCH EDS1.2) 2015MOW10, USB2_ID connected to GND

FP LTE

SSD

Thunderbolt

Wigig

IO/B DOCKING

DOCKING IO/B

NFC_IRQ,RST# follow PDG 1.3

NFC

TS CR

Close to UC1

2017/4/18 for MB Fieldlesson learnt ESD request

USB20_N2USB20_N3USB20_P3

USB20_N1USB20_P1USB20_P2

USB20_P7USB20_N7

PCIE_RCOMPNXDP_PRDY#

USB2_COMP

USB_OC0#

USB20_N5USB20_P5

USB_OC0#

PIRQA#

PCIE_CTX_DRX_N5PCIE_CRX_DTX_N5PCIE_CTX_DRX_P5PCIE_CRX_DTX_P5

PCIE_CRX_DTX_N6PCIE_CTX_DRX_P6

USB2_IDUSB2_VBUSSENSE

USB20_P8USB20_N8USB20_N9USB20_P9

PCIE_CRX_DTX_N11PCIE_CTX_DRX_N11PCIE_CTX_DRX_P11PCIE_CRX_DTX_P11

PCIE_CTX_DRX_N12PCIE_CRX_DTX_N12PCIE_CTX_DRX_P12PCIE_CRX_DTX_P12

PCIE_CRX_GTX_N8PCIE_CTX_GRX_N8PCIE_CRX_GTX_N9

PCIE_CRX_GTX_N10

USB20_N4USB20_P4

NFC_RST#

DEVSLP2PCH_SATALED#

PCH_SATALED#

NFC_IRQNFC_RST#

DEVSLP2USB20_N10

USB20_N6USB20_P6

PCIE_CTX_GRX_P9

PCIE_CTX_GRX_P10

SATAXPCIE1

PCIE_CRX_DTX_N4PCIE_CTX_DRX_N4

+3VS+3VS

Title

CC435 1U_0402_16V7K

ESD@

12

Trang 13

543016_SKL_PDG_1_0 +1.35V_VDDQ_CPU : 2x 10uF 0402 (Placeholder)

4x 1uF 0201 (Placeholder) 4x 10uF 0402

3x 22uF 0603

For Power consumption Measurement

BSC Side PSC Side

543016_SKL_PDG_1_0 +1.0V_VCCSFR : 1x 1uF 0402

543016_SKL_PDG_1_0 +1.0V_VCCST : 1x 1uF 0402

543016_SKL_PDG_1_0 +1.0VS_VCCSTG : 1x 1uF 0402 (Placeholder)

PSC Side

BSC Side

543016_SKL_PDG_1_0 +1.35V_VDDQC : 1x 1uF 0201 (Placeholder)

1x 10uF 0402

PSC Side

6.35A 2.73A

6A

0.09A 0.04A 0.04A 0.26A 0.12A

VCCSA_SENSE

VCCIO_SENSEVSSIO_SENSEVSSSA_SENSE

EN_1.8VSEN_1.0V_VCCSTU

+1.2V_VDDQ_CPU

+1.2V_VDDQ

+1.0VS_VCCSTG

+1.0V_VCCST+1.0VS_VCCSTG+1.2V_VCCSFR_OC+1.0V_VCCSFR

+1.8VALW _VS

+1.0V_VCCSTU+1.0VALW _PRIM

+1.2V_VDDQC+1.2V_VDDQ_CPU

VCCIO_SENSE AM23

VCCSA AK23VCCSA AK25VCCSA G23VCCSA G25VCCSA G27VCCSA G28VCCSA J22VCCSA J23VCCSA J27VCCSA K23VCCSA K25VCCSA K27VCCSA K28VCCSA K30VSSIO_SENSE AM22VSSSA_SENSE H21VCCSA_SENSE H20

2

JPC2JUMP_43X118

2

T124@

JPC8JUMP_43X39

2

CC941000P_0402_50V7K

2

J16JUMP_43X79

2

CC951000P_0402_50V7K

7

CT1 12VOUT1 14

VOUT2 8

VOUT1 13VIN1

4

GND 5GND 9

VOUT 7VOUT 8VIN

@12

4

VOUT 6VIN2

Trang 14

CC77,CC78 near AK17 (<3 mm)

CC86 near A10 (<3 mm) CC87 near K17 (<3 mm)

+1.0VALW _CLK6_24TBT+RTCVCC

+1.0VALW _APLL+1.0VALW _CLK4_F100OC

+3VALW _PGPPC+3VALW _1.8VALW _PGPPD+3VALW _PGPPE+1.8VALW _PRIM+3VALW _PGPPG

+1.0VALW _SRAM

+3VALW _PRIM

+1.0VALW _PRIM+1.0VALW _APLLEBB

+3VALW _1.8VALW _PGPPA+3VALW _PGPPB

+1.0VALW _CLK6_24TBT+1.0VALW _PRIM

+1.0VALW _PRIM +3VALW _PRIM +1.8VALW _PRIM

+1.0VALW _MPHYPLL+1.0VALW _PRIM

+RTCBATT

+RTCVCC+CHGRTC

+1.0VALW _MPHYGT

+1.0VALW _VCCCLK2

+3VALW _PRIM+1.8VALW _PRIM+3VALW _1.8VALW _PGPPA

+1.8VALW _PRIM

+1.0VALW _CLK5_F24NS +1.0VALW _PRIM

+1.0VALW _MPHYAON+1.0VALW _PRIM

+3VM

Title

RF@

RC1640_0603_5%

2

T136@

RC1520_0603_5%

2

CC12522U_0603_6.3V6M @

12

RC1610_0402_5%

2

CC741U_0402_6.3V6K @

12

RC1620_0402_5%

2

RC1670_0402_5%

2

RC1900_0603_5%

2

CC110.1U_0402_16V7K

RF@

RC1710_0402_5%

2

CC631U_0402_6.3V6K

@

RC1960_0402_5% 2ESPI@ 1

CC861U_0402_6.3V6K @

12

RC1630_0402_5%

2

RC1690_0402_5%

2

CC721U_0402_6.3V6K

12

CC871U_0402_6.3V6K

2

CC12322U_0603_6.3V6M

@

CC911U_0402_6.3V6K

@12

C201247U_0805_6.3V6M

12

RC1870_0402_5%

2

CC731U_0402_6.3V6K @

12

RC192 0_0603_5%

@

CC118.1U_0402_16V7K

2

CC1021U_0402_6.3V6K @

12

CC831U_0402_6.3V6K @

12

CC81 22U_0603_6.3V6M

@

C151.1U_0402_16V7K

1

2

RC2060_0402_5% 1 @ 2

CC761U_0402_6.3V6K

@12

2

JPC9JUMP_43X79

3

CC751U_0402_6.3V6K @

12

SKL-UCPU POWER 4 OF 4

Trang 15

1 1

Trace Length < 25 mils

For CPU2+3e SKU

Trace Length < 25 mils

SVID ALERT

SVID DATA

Place the PU resistors close to CPU

#5449 4 Skylake EDS P.1 1 VCCGT U(15W)-dual core GT 40A(MAX) 0.55-1.15V

+VCC_GTX_VCORE(12PIN) U22 ==> NC

U42 ==> +VCC_CORE

+VCC GT VCORE(10PIN)

U ==>+VCC GT U4 ==>+VCC CORE

56910 U42/U22 common board K52/AK52 NC

VCCGT_SENSEVSSGT_SENSE

VCCOPC_SENSE

VCCEOPIO_SENSEVSSEOPIO_SENSE

SOC_SVID_CLKSOC_SVID_ALERT#

SOC_SVID_ALERT#

VCCGTX_SENSEVSSGTX_SENSE

SOC_SVID_DAT

VCCGTX_AK52VCC_GT_K52

+VCC_GTX_VCORE+VCC_GT_VCORE

+VCC_GT

Title

RSVD_K32

K32

VSS_SENSE E33RSVD_AK32

AK32

Trang 16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SKL-UGND 2 OF 3

BA45

VSS BA49VSS BA53VSS BA57VSS BA6VSS BA62VSS BA66VSS BA71VSS BB18VSS BB26VSS BB30VSS BB34VSS BB38VSS BB43VSS BB55VSS BB6VSS BB60VSS BB64VSS BB67VSS BB70VSS C1VSS C25VSS C5VSS D10VSS D11VSS D14VSS D18VSS D22VSS D25VSS D26VSS D30VSS D34VSS D39VSS D44VSS D45VSS D47VSS D48VSS D53VSS D58VSS D6VSS D62VSS D66VSS D69VSS E11VSS E15VSS E18VSS E21VSS E46VSS E50VSS E53VSS E56VSS E6VSS E65VSS E71VSS F1VSS F13VSS F2VSS F22VSS F23VSS F27VSS F28VSS F32VSS F33VSS F35VSS F37VSS F38VSS F4VSS F40VSS F42VSS

F68

SKL-UGND 3 OF 3

Trang 17

Display Port Presence Strap

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

1 : Disabled; No Physical Display Port

attached to Embedded Display Port

For 2+3e Solution PM_ZVM#

Zero Voltage Mode: Control Signal to OPC

VR, when low OPC VR output is 0V.

PM_MSM#

Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solution for OPC).

CFG16CFG18

CFG0CFG2CFG4CFG6CFG8CFG10CFG12CFG14

SOC_XTAL24_IN_U42_RSOC_XTAL24_OUT_U42_R

SOC_XTAL24_OUT_U42

SOC_XTAL24_IN_U42

+1.0V_VCCST+1.8VALW _PRIM

Title

RSVD_A69 A69RSVD_B69 B69

RSVD_TP_BB68 BB68RSVD_TP_BB69 BB69

RSVD_TP_AK13 AK13RSVD_TP_AK12 AK12

TP4 BB5

TP5 AU5TP6 AT5

RSVD_B3 B3RSVD_A3 A3

@1

Trang 18

Check voltage tolerance of

VREF_DQ at the DIMM socket

4 as near side of the DIMM close to VDD pins

Place these caps on the VTT plane close to DIMM

DDR_B_CLK#0

DDR_B_CS#1DDR_B_CKE1

DDR_B_BA1

DDR_B_CLK#1DDR_B_CLK1

DDR_B_CS#0

SOC_SMBDATASOC_SMBCLK

+3VS_DIMM

DDR_B_D10DDR_B_D15

DDR_B_D9DDR_B_D12

DDR_B_D11DDR_B_D14

DDR_B_D8DDR_B_D13

DDR_B_D0DDR_B_D5

DDR_B_D4DDR_B_D1

DDR_B_D6DDR_B_D3

DDR_B_D16DDR_B_D17

DDR_B_D18DDR_B_D22

DDR_B_D20DDR_B_D21

DDR_B_D19DDR_B_D23

DDR_B_D24DDR_B_D25

DDR_B_D28DDR_B_D29

DDR_B_D32DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36DDR_B_D37

DDR_B_DQS#4DDR_B_DQS4

DDR_B_DQS3DDR_B_DQS#3

DDR_B_DQS1DDR_B_DQS#1

DDR_B_D48DDR_B_D49

DDR_B_D51DDR_B_D50

DDR_B_D54DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D60DDR_B_D61

DDR_B_D63DDR_B_DQS#7DDR_B_DQS7

DDR_B_CLK0DDR_B_CLK#0

DDR_B_CLK1DDR_B_CLK#1

DDR_B_CS#0

DDR_B_CS#1DDR_B_ODT0DDR_B_ODT1

DDR_B_BG0

DDR_B_BA0DDR_B_BA1

DDR_B_MA0DDR_B_MA1

DDR_B_MA2DDR_B_MA3

DDR_B_MA4DDR_B_MA6

DDR_B_MA7DDR_B_MA8

DDR_B_MA10

DDR_B_MA11DDR_B_MA12

+1.2V_VDDQ

Title

12

3

DQ4 4VSS

5

VSS6DQ1

7

DQ0 8VSS

9

VSS10DQS0_C

11

DM0*/DBI0* 12DQS0_T

13

VSS14VSS

15

DQ6 16DQ7

17

VSS18VSS

19

DQ2 20DQ3

21

VSS22VSS

23

DQ12 24DQ13

25

VSS26VSS

27

DQ8 28DQ9

29

VSS30VSS

31

DQS1_C 32DM1*/DBI1*

33

DQS1_T 34VSS

35

VSS36DQ15

37

DQ14 38VSS

39

VSS40DQ10

41

DQ11 42VSS

43

VSS44DQ21

45

DQ20 46VSS

47

VSS48DQ17

49

DQ16 50VSS

51

VSS52DQS2_C

53

DM2*/DBI2* 54DQS2_T

55

VSS56VSS

57

DQ22 58DQ23

59

VSS60VSS

61

DQ18 62DQ19

63

VSS64VSS

65

DQ28 66DQ29

67

VSS68VSS

69

DQ24 70DQ25

85

VSS86CB5_NC

87

CB4_NC 88VSS

75

DQS3_T 76VSS

77

VSS78DQ30

79

DQ31 80VSS

81

VSS82CB1_NC

91

CB0_NC 92VSS

93

VSS94DQS8_C

95

DM8*/DBI8* 96DQS8_T

97

VSS98VSS

99

CB6_NC 100CB2_NC

101

VSS102VSS

103

CB7_NC 104CB3_NC

105

VSS106VSS

107

RESET* 108CKE0

109

CKE1 110VDD1

111

VDD2 112BG1

113

ACT* 114BG0

115

ALERT* 116VDD3

117

VDD4 118A12

119

A11120A9

121

A7 122VDD5

123

VDD6 124A8

125

A5 126A6

127

A4 128VDD7

129

VDD8 130A3

131

A2 132A1

133

EVENT* 134VDD9

135

VDD10 136CK0_T

137

CK1_T 138CK0_C

139

CK1_C 140VDD11

141

VDD12 142PARITY

143

A0 144BA1

145

A10_AP 146VDD13

147

VDD14 148S0*

149

BA0 150A14_WE*

151

A16_RAS* 152VDD15

153

VDD16 154ODT0

155

A15_CAS* 156S1*

157

A13158VDD17

159

VDD18 160ODT1

161

S2*/C0 162VDD19

163

VREFCA 164S3*/C1

165

SA2 166VSS

167

VSS168DQ37

169

DQ36 170VSS

171

VSS172DQ33

173

DQ32 174VSS

175

VSS176DQS4_C

177

DM4*/DBI4* 178DQS4_T

179

VSS180VSS

181

DQ39 182DQ38

183

VSS184VSS

185

DQ35 186DQ34

187

VSS188VSS

189

DQ45 190DQ44

191

VSS192VSS

193

DQ41 194DQ40

195

VSS196VSS

197

DQS5_C 198DM5*/DBI5*

199

DQS5_T 200VSS

201

VSS202DQ46

203

DQ47 204VSS

205

VSS206DQ42

CD28.1U_0402_16V7K

1

2

RD1380_0402_5%

RD10810K_0402_5%

RD1224.9_0402_1%

@1

Trang 19

S IC W83L771AWG-2 TSSOP 8P SENSOR

External DDR Thermal Sensor

DQU2 DQU0

DQU6 DQU7

DQL6

DQU4 DQU3

DQL2 DQL0

D2

DQU2

DQU6 DQU0

DQU7

DQU3 DQU4 DQL7

DQU5 DQL6

DQL0

DQL2 U3

DQL3 DQL4 DQL1

DQL5 DQ

DQU2

DQU6 DQU0

DQU7

DQL6

DQU3 DQU4

DQL0

DQL2

DQL4 DQL1

DQL7 DQL5

DQU5

DQ

DQU2

DQU6 DQU0

DQU7

DQL6

DQU3 DQU4

DQL0

DQL2

DQL4 DQL1

DQL7 DQL5

DQU5

DQ

D0

D5 D7

D6

D8 D10

D11 D9

D12 D15 D14

D19 D17 D18

D23 D21 D22

D26 D24

D25 D30 D29

D28

D35 D33 D34

D39 D37 D38

D42 D40

D41 D46 D45

D44

D51 D49 D50

D55 D53 D54

D58 D56

D57 D62 D61

D60

on board ram flag

1 1 0 0

1

FLAG1

0 FLAG0

1 0

INTEL suggest 50ohm 1%

Micron 4G(SDP) SA00009V220hynix 4G(SDP) SA0000A1H20

X76OBRAM@ Level includes U2~U5, RU169, RU170, RU172, RU173, RC215 and RC216

Co-lay for SDP/DDP

MICRON 8G (DDP) SA0000A3120hynix 8G(DDP) SA0000ARA10

2017/6/8confirm Thermal/EC change to reserve

VGA_ID (D4PB1/D5PB1)

0 0 0 1 1

1 1

0 0

No on baord RAM

MEMRST#

DDR_A_MA8DDR_A_MA5DDR_A_MA3

DDR_A_MA13DDR_A_MA10DDR_A_MA9DDR_A_MA11DDR_A_MA7DDR_A_MA4DDR_A_MA0

DDR_A_CLK#0DDR_A_CLK0DDR_A_CKE0DDR_A_MA14

DDR_A_D8DDR_A_D14

DDR_A_D12

DDR_A_D10DDR_A_D11

DDR_A_D0DDR_A_D1

DDR_A_D9

DDR_A_D3

DDR_A_D5

DDR_A_ODT0DDR_A_CS#0

DDR_A_ALERT#

DDR_A_BG0M_A_ACT#

MEMRST#

DDR_DRAMRST#

DDR_A_ALERT#

DDR_A_D30DDR_A_D24

DDR_A_D31DDR_A_D25

DDR_A_D18DDR_A_D23DDR_A_D20DDR_A_D19

DDR_A_MA10DDR_A_MA12

DDR_A_MA2DDR_A_MA5

DDR_A_MA8

DDR_A_MA0

DDR_A_MA4DDR_A_MA6

DDR_A_MA11DDR_A_MA9

DDR_A_MA14

DDR_A_D46DDR_A_D40

DDR_A_D47DDR_A_D41

DDR_A_D34DDR_A_D39DDR_A_D36DDR_A_D37DDR_A_D35

DDR_A_MA11DDR_A_MA9

DDR_A_MA14

DDR_A_D62DDR_A_D56

DDR_A_D63DDR_A_D57

DDR_A_D50DDR_A_D55DDR_A_D52DDR_A_D53DDR_A_D51

MEMRST#

DDR_A_MA11DDR_A_MA9

DDR_A_CKE0DDR_A_CLK0DDR_A_CLK#0

DDR_A_MA16DDR_A_ODT0DDR_A_CS#0

DDR_A_DQS4DDR_A_DQS#4

DDR_A_DQS#7DDR_A_DQS7DDR_A_DQS6DDR_A_DQS#6

DDR_A_ALERT#

DDR_A_BG0M_A_ACT#

DDR_A_ALERT#

DDR_A_BG0M_A_ACT#

DDR_A_ALERT#

DDR_A_BG0M_A_ACT#

RAM_FLAG1RAM_FLAG0

+DDR_VREF_CA+1.2V_VDDQ

DDP@

RU1740_0402_5%

SDP@

SD028000080

RU1780_0402_5%

RU1750_0402_5%

SDP@

SD028000080

RU160240_0402_1%

RU177240_0402_1%

DDP@

96-BALLSDRAM DDR4

VSSQ C9

VSSB2VSSE9VSSE1

ACT

L3

VDD B3VDD B9

VDDQ A1VDDQ A9VDDQ C1VDDQ D9

DQSU_c

A7

VDDQ G1

VSSQ E8VSSQ F1

VDDQ G9VDDQ J2

VSSK9VSSM9VSSN1VSST1

VDDQ F2VDD T9

SDP@

RU1760_0402_5%

SDP@SD028000080

RU161240_0402_1%

RD1951.8K_0402_1%

RU17010K_0402_5%

X76OBRAM@

RU16910K_0402_5%

X76OBRAM@

RU163240_0402_1%

VSSQC9

VSSB2VSSE9VSSE1

ACT

L3

VDDB3VDDB9

DQSU_c

A7

VDDQ G1

VSSQE8VSSQF1

VDDQ G9VDDQ J2

VDDQ F2VDDT9

X76OBRAM@

CD36.1U_0402_16V7K

@1

4

GND 5D+

2

D-3

SCLK 8SDATA 7

ZZZ

ALT GROUP PARTS HYNIX 4G AE591 C4PB1

X76@OBHYNIX4X76713BOL03

96-BALLSDRAM DDR4

VSSQ C9

VSS B2VSS E9VSS E1

ACT

L3

VDD B3VDD B9

DQSU_c

A7

VDDQ G1

VSSQ E8VSSQ F1

VDDQ G9VDDQ J2

VSS K9VSS M9VSS N1VSS T1

VDDQ F2VDD T9

X76OBRAM@

CD240.022U_0402_16V7K

DDP@

RU162240_0402_1%

RD1324.9_0402_1%

RD2001.8K_0402_1%

CU1810.1U_0402_16V4Z

@

96-BALLSDRAM DDR4

VSSQC9

VSSB2VSSE9VSSE1

ACT

L3

VDDB3VDDB9

DQSU_c

A7

VDDQ G1

VSSQE8VSSQF1

VDDQ G9VDDQ J2

VDDQ F2VDDT9

12

RU174240_0402_1%

Trang 20

D D

2 as near each on board RAM device as possible

4 as near each on board RAM device as possible

SGA00009S00 330U 2V H1.9 9mohm POLY

Follow MA51

DDR_A_MA9DDR_A_MA1

DDR_A_MA6DDR_A_MA11DDR_A_MA7

DDR_A_MA14DDR_A_BA0

DDR_A_ODT0DDR_A_CS#0DDR_A_MA16

DDR_A_BG0

DDR_A_MA13DDR_A_MA8

DDR_A_MA2DDR_A_PARITYDDR_A_MA3

DDR_A_CKE0DDR_A_MA12M_A_ACT#

Trang 21

EDP_AUXN_CEDP_AUXP_C

USB20_P7USB20_N7 USB20_N7_CAMERA

USB20_P7_CAMERA

USB20_N7_CAMERAEDP_AUXP_CEDP_AUXN_C

EDP_TXP0_CEDP_TXP1_C

BKOFF#

SOC_BKL_PW MEDP_HPDEDP_TXN2_CEDP_TXN3_C

USB20_P10+TS_PW R

TS_EN

USB20_P10USB20_N10

+3VS

Title

TS_3VS@

C3871 2.1U_0402_16V7K

R364100K_0402_5%

<BOM Structure>12

@1

2

C3781 2.1U_0402_16V7K

L14HCB2012KF-221T30_0805

R6142 @ 1 100K_0402_5%

C375.1U_0402_16V7K

RF@

1

2

C419.1U_0402_16V7K

@1

RF@

C36568P_0402_50V8J

@EMC@

1

2

R5270100K_0402_5%

RF@

1

2

L4904MCF12102G900-T_4P

1

2

C3741 2.1U_0402_16V7KC3731 2.1U_0402_16V7K

Trang 22

0 0

1

EEPROM EP

*ROM X

ROM: Internal ROM

EP: Programmed external EC

EEPROM: External ROM

POL_SDA

Address:(layout guide P.11) Please reserve slave address of 0x64/0x65 and 0x68/0x69 for RTD2168’ s use

DP_CRT_AUXPSOC_DP1_P0_CSOC_DP1_P1_C

VCCK_12

VCCK_12+3VS_CRT

SOC_SML1DATASOC_SML1CLK

POL2_SCLPOL1_SDA

PCH_CRT_HSYNC_R

PCH_CRT_GPCH_CRT_R

LDO_EN

CRT_CLK_1

CRT_SMB_CLKCRT_SMB_SDA

POL1_SDAPOL2_SCL LDO_EN

LDO_EN 21GREEN_P 12

EPAD_GND

33

R19 1 @ 2 0_0402_5%

C38 1 2 1U_0402_16V7KC5 1 2 1U_0402_16V7K

C17 1U_0402_16V7K

12

R2530100K_0402_5%

1

2

RP2375_0804_8P4R_1%

Trang 23

To CRT CONN.

SEL:High

CRT_CLK_1CRT_DATA_1PCH_CRT_HSYNC_RPCH_CRT_GPCH_CRT_RPCH_CRT_B

CRT_R_2CRT_G

CRT_DATA_2

CRT_R

CRT_G_2

CRT_HSYNC_2CRT_B_2

CRT_VSYNC_2CRT_B

CRT_CLK_1CRT_DATA_1

CRT_DATA_DOCKCRT_CLK_DOCKVSYNC_DOCK

CRT_RCRT_BCRT_GCRT_VSYNCCRT_HSYNCCRT_DATA_2CRT_CLK_2DOCK_CRT_DET#

CRT_B_2

+3VS_CRT_SW+5VS_CRT_SW+5VS_CRT_SW

H2_OUT 19R2 26

R1 27G1 25

G2 24

GND

31

VDD 32SDA_SOURCE

L2503BLM15BA220SN1D_2P

EMC@

C253610P_0402_50V8J

1

2

R252433_0402_5%

GG

JCRT2

SUYIN_070546FR015S251ZR

CONN@

611112213314410516

C253710P_0402_50V8J

1

2

R76210K_0402_5% 1 2

Trang 24

D D

Chip operational mode configuration;

Internal pull down at ~150K?, 3.3V I/O.

L: Control switching mode (default) H: Automatic switching mode

AUX interception disable for Port y (y=1,2)

L: AUX interception enable, driver configuration

is set by link training (default)

H: AUX interception disable, driver output with

fixed 800mv and 0dB

M: AUX interception disable, driver output with

fixed 400mv and 0dB

Output swing adjusment for Port y (y=1,2).

L:default H: +20%

M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

Automatic EQ disable;

Internal pull down at ~150K?, 3.3V IO L: Automatic EQ enable (default) H: Automatic EQ disable

Auto test enable;

L: Auto test disable & input offset cancellation enable (default)

H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable

Port switching control or priority configuration;

L: Port1 is selected or with higher priority

PC20

PC11

PC21

PC11PC21

TBT_DP1_AUXNDP_DOCK_AUXN

TBT_DP1_AUXPDP_DOCK_AUXP

CPU_DP2_P2CPU_DP2_N2CPU_DP2_P1CPU_DP2_N1CPU_DP2_P0

DDI2_AUX_DPDDI2_AUX_DN

DPB_AUXPDPB_AUXNCPU_DP2_P3

DPB_P0DPB_N1

DPB_N2DPB_P1

DPB_P2DPB_N3DPB_P3CPU_DP2_N3

DPB_P2

DPB_N3

DPB_P1DPB_N0

DPB_N1

DPB_N2

DPB_AUXN

DDI2_CTRL_CKDDI2_CTRL_DATA

Trang 25

2017/4/17 add diode for ESD request

ME2N7002D1KW use SB00000DH00 symbol

HDMI_TX2- HDMI_TX2+ HDMI_TX2+

HDMI_TX1-HDMI_R_SDATAHDMI_R_SCLKHDMI_R_HPD

HDMI_R_SDATA

HDMI_R_SCLKHDMI_SCLK

HDMI_SDATA

HDMI_R_HPDHDMI_HPD

HDMI_TX0+

HDMI_TX1-HDMI_TX1+

HDMI_TX0-HDMI_TX2+

HDMI_TX2-HDMI_CLK+

HDMI_CLK-HDMI_TX0+

HDMI_TX0-HDMI_TX2+

OUT 3IN

1

Q2020AME2N7002D1KW-G 2N SOT363-6

SB00000SA0061

R420K_0402_5%

R51721M_0402_5%

4

3

21

9 10

D2021

L05ESDL5V0NA-4 SLP2510P8

ESD@

451

C8020.1U_0402_16V4Z

SB00000SA00

34

4

3

21

9 10

D2022

L05ESDL5V0NA-4 SLP2510P8

ESD@

451

SB00000SA00

61

Q2020BME2N7002D1KW-G 2N SOT363-6

GND 20GND 21GND 22GND 23

Trang 26

0810 add for customer's request

RDSATA_PTX_C_DRX_P0 RDSATA_PTX_C_DRX_N0 RDSATA_PRX_C_DTX_N0 RDSATA_PRX_C_DTX_P0

RDSATA_PRX_DTX_P0 RDSATA_PRX_DTX_N0 RDSATA_PTX_DRX_N0

A_EQ1 B_EQ1 B_DE

A_EQ2 A_DE

B_EQ1

A_EQ2

A_DE B_DE

A_EQ1

SATA_CRX_DTX_P0 SATA_CRX_DTX_N0

SATA_CTX_DRX_P0 SATA_CTX_DRX_N0 SATA_PTX_C_DRX_N0

SATA_PTX_C_DRX_P0

SATA_PRX_C_DTX_P0 SATA_PRX_C_DTX_N0

RDSATA_PTX_DRX_P0 RDSATA_PTX_DRX_N0 RDSATA_PRX_DTX_N0 RDSATA_PRX_DTX_P0

@

R523 0_0402_5% @

C628 1 2 0.1U_0402_16V4Z

Trang 27

PCIE_CTX_DRX_P12PCIE_CTX_DRX_N12

SSD_DET#

PCIE_CTX_C_DRX_P11PCIE_CRX_DTX_N11

PCIE_CRX_DTX_P11

PCIE_CTX_DRX_P11PCIE_CTX_DRX_N11

CLK_PCIE_P0

CLKREQ_PCIE#0

CLKREQ_PCIE#0 <10>

+3VS_SSD_NGFF+3VS

+3VS_SSD_NGFF+3VS_SSD_NGFF

@

R6410_0402_5%

3

N/C 8PERn3

5

DAS/DSS# 10PETp3

11

3.3VAUX 12PETn3

13

3.3VAUX 14GND

15

3.3VAUX 163.3VAUX 18N/C 20N/C 22N/C 24N/C 26N/C 28N/C 30N/C 32N/C 34N/C 36DEVSLP 38N/C 40N/C 42N/C 44N/C 46N/C 48PERST# 50CLKREQ# 52PEWake# 54GND

MTG76 68MTG77

C8361 20.22U_0402_16V7K

R6370_0603_5%

SGA00009M001

R6400_0603_5% 1 2

1

2

R527510K_0402_5%

@

SB00000SA00

R52760_0402_5%

@

C8391 20.22U_0402_16V7K

R414100K_0402_5%

1

2

GD

S

Q20232N7002E_SOT23-3

@2

R6600_0402_5%

@

R6620_0603_5% 1 2

R664 0_0402_5%

@

Định dạng
Số trang	54
Dung lượng	3,72 MB