COMPAL LA 6121p NCL50 UMA REV 1 0

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Montevina UMA LA6121P 0.2 Cover

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Montevina UMA LA6121P 0.2

Cover SheetCustom

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Cover SheetCustom

2010-04-08 NCL50 REV:1.0

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Block DiagramCustom

Fan conn

Mobile Penryn/Merom uFCPGA-478 CPU

FSB 667/800/1066 MHz 1.05V H_A#(3 35)

Codec_AL272 Audio CKT AMP & Audio Jack

SPI

Clock Generator SLG8SP553V

P17

CRT

LVDS Panel Interface

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1 1

Title

Notes ListCustom

Wednesday, April 14, 2010

O MEANS ON X MEANS OFF Voltage Rails

power plane

S5 S4/AC & Battery

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

SERIAL EEPROM

SMB_EC_CK2

SOURCE

KB926

SMBUS Control Table

I2C / SMBUS ADDRESSING

1 0 1 0 0 0 0 0

D2 A0

CLOCK GENERATOR (EXT.)

O O O O

O O O

O O

X X X

V

X X X

X X

X X X

X

X X

X

X X

X

X X

X

X X X

KB926

DEBUG@ : means just reserve for debug.

CONN@ : means ME part BATT @ : means need be mounted when 45 level assy or rework stage.

45@ : means need be mounted when 45 level assy or rework stage USB-8 X

USB-6 Bluetooth USB-5 WLAN USB-4 Camera USB-2 Left side

USB-10 X USB-9 X

USB-3 X

USB-7 Cardreader USB assignment:

USB-11 X USB-0 Right side daughter board

PCIe-2 X

PCIe assignment:

PCIe-1 X

PCIe-3 WLAN PCIe-4 GLAN (Realtek) PCIe-5 X

+1.5V

+0.75VS

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Security Classification Compal Secret Data

Power delevry

C

Title

Power delevry

C

Title

+5VAMP ODD 1.8A

SATA 700mA

MCH 3.7A

+VCCP

ICH9 MCH 1.26A

CPU 2.3A

1.17A

LVDS CON

3.35A 5.89A

3.7 X 3=11.1V

1.7A 2A

1.3A 0.58A

12.11A 1.9A

4.7A

7A

+1.5VS

ICH_VCC1_5 ICH9 657mA

ICH9 1.56A

2.2A 0.3A

2A

CPU 34A/1.025V

Mini card (WLAN) 1A

+3VAUX_BT

SPI ROM

+3VALW_EC 20mA

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1 1

Title

Notes ListCustom

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H_THERMDCH_THERMTRIP#

H_THERMDAH_THERMDA_R

H_ADSTB#0

H_A#7H_A#9

H_A#16

H_A#6H_A#8

H_A#12H_A#15H_A#5

H_A#14H_A#4

H_REQ#2H_REQ#4H_REQ#1H_REQ#3

H_A#32H_A#34

H_A#18

H_A#30H_A#27H_A#21H_A#17

H_A#20

H_A#25H_REQ#0

H_ADSTB#1H_A#28

H_RESET# 9H_RS#0 9H_RS#1 9H_RS#2 9

H_DEFER# 9

H_INIT# 21H_BPRI# 9

H_DRDY# 9H_DBSY# 9H_BR0# 9

EN_DFAN131

Montevina UMA LA6121P 0.2Penryn(1/3)-AGTL+/ITP-XDPCustom

Thursday, April 15, 2010

Address:100_1100 H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil

For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm.

PWM Fan Control circuit

This shall place near CPU

Change value in 5/02

Place TP with a GND 0.1" away

PV：：：Checklist Ver 1.5 change to 56 ohm

PV：：： follow check list ver:1.5 change to 51 ohm ITP-XDP Connector

03/18 PV：：：Delete XDP connector

04/29 MV1 reserve 10K for 2nd source

04/29 MV1 R2~R8 change to 54.9 Ohm, follow checklist 2.0

04/29 MV1 change R14、、、R15 to 0 ohm

1A

10mil Modify as KSWAA, need double check the CONN pin define 10/24 Prince

2R18

56_0402_5%

R1856_0402_5%

C32200P_0402_50V7KC3

2200P_0402_50V7K

C6210U_0805_10V4ZC6210U_0805_10V4Z

1

2R17

56_0402_5%

@R1756_0402_5%

THERM#

SMDATA 7

D341SS355_SOD323-2

@

D341SS355_SOD323-2

R1610K_0402_5%

R14 1 2 0_0402_5%

C6310U_0805_10V4ZC6310U_0805_10V4Z1

2

R11K_0402_5%

@R11K_0402_5%

BNR# E2

BPM[0]# AD4BPM[1]# AD3BPM[2]# AD1BPM[3]# AC4

BPRI# G5

BR0# F1

DBR# C20

DBSY# E1DEFER# H5DRDY# F21

FERR#

A5

HIT# G6HITM# E4IERR# D20

THERMTRIP# C7

THERMDA A24THERMDC B25TMS AB5TRDY# G2

@C1681000P_0402_25V8J

@12

R8 1 2 54.9_0402_1%

R5010K_0402_5%

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H_D#6H_D#2

H_D#8

H_D#12

H_D#1

H_D#5H_D#7

H_D#11H_D#0

H_D#15

H_D#27H_D#25

H_D#31H_D#24H_D#20

H_D#30H_D#23H_D#19

H_D#29

H_D#16H_D#18

H_D#22

H_D#26H_D#28

H_D#17

H_D#21H_DINV#0

H_DINV#1H_DSTBP#1

H_DSTBP#0

+VCCPA

VSSSENSEVCCSENSE

+V_CPU_GTLREFTEST1

H_D#35

H_D#46

H_D#37H_D#34

H_D#41

H_D#45H_D#43

H_DINV#2H_DSTBN#2

H_DINV#3H_DSTBN#3

H_D#48

H_D#56H_D#52

H_D#59

H_D#63

H_D#55H_D#51

H_D#62H_D#58H_D#54H_D#50

H_D#57

H_D#61

H_D#53H_D#49

H_D#60

COMP0COMP2

H_PWRGOODH_CPUSLP#

CPU_BSEL1TEST5

CPU_BSEL2TEST2

H_DSTBN#3 9H_DSTBP#3 9H_DINV#3 9

H_DPSLP# 21

H_CPUSLP# 9H_DPWR# 9H_PWRGOOD 21CPU_BSEL2

H_PSI# 41H_DPRSTP# 9,21,41

Close to CPU pin AD26 within 500mils.

166

200

CPU_BSEL0

Resistor placed within 0.5"

of CPU pin.Trace should be

at least 25 mils away from any other toggling signal.

COMP[0,2] trace width is 18 mils COMP[1,3] trace width

is 4 mils.

Length match within 25 mils.

The trace width/space/other is 20/7/25.

Close to CPU pin within 500mils.

Near pin B26

* Route the TEST3 and TEST5 signals through

a ground referenced Zo = 55-ohm trace that

ends in a via that is near a GND via and is

accessible through an oscilloscope

connection.

266

1

1 0

VCCA[01] B26

VCCP[03] J6VCCP[04] K6VCCP[05] M6VCCP[06] J21VCCP[07] K21VCCP[08] M21VCCP[09] N21VCCP[10] N6VCCP[11] R21VCCP[12] R6VCCP[13] T21VCCP[14] T6VCCP[15] V21VCCP[16] W21

VCCSENSE AF7

VID[0] AD6VID[1] AF5VID[2] AE5VID[3] AF4VID[4] AE3VID[5] AF3VID[6] AE2

VSSSENSE AE7VCCA[02] C26

VCCP[01] G21VCCP[02] V6

Penryn

COMP[0] R26COMP[1] U26COMP[2] AA1COMP[3] Y1

F23

D[40]# Y25D[41]# W22D[42]# Y23D[43]# W24D[44]# W25D[45]# AA23D[46]# AA24D[47]# AB25

D[48]# AE24D[49]# AD24

D[5]#

G25

D[50]# AA21D[51]# AB22D[52]# AB21D[53]# AC26D[54]# AD20D[55]# AE22D[56]# AF23D[57]# AC25D[58]# AE21D[59]# AD21

D[6]#

E25

D[60]# AC22D[61]# AD23D[62]# AF22D[63]# AC23

R200_0402_5%

R292K_0402_1%

R271K_0402_1%

330U_D2E_2.5VM_R71

2

T3

R190_0402_5%

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Inside CPU center cavity in 2 rows Mid Frequence Decoupling

Place these capacitors on L8 (North side,Secondary Layer)

ESR <= 1.5m ohm Capacitor > 1980uF

Near CPU CORE regulator

Place these capacitors on L8 (North side,Secondary Layer)

11/21 Change ESR=7m ohm

C2910U_0805_6.3V6MC2910U_0805_6.3V6M1

2

C45

0.1U_0402_10V6KC45

0.1U_0402_10V6K1

2

C3910U_0805_6.3V6MC3910U_0805_6.3V6M1

2

C47

0.1U_0402_10V6KC47

0.1U_0402_10V6K1

2

C2810U_0805_6.3V6MC2810U_0805_6.3V6M1

2

C19

10U_0805_6.3V6MC19

10U_0805_6.3V6M1

2

C46

0.1U_0402_10V6KC46

0.1U_0402_10V6K1

2

C17

10U_0805_6.3V6MC17

10U_0805_6.3V6M1

2

C24

10U_0805_6.3V6MC24

10U_0805_6.3V6M1

2

C3310U_0805_6.3V6MC3310U_0805_6.3V6M1

2

C20

10U_0805_6.3V6MC20

10U_0805_6.3V6M1

2

C22

10U_0805_6.3V6MC22

10U_0805_6.3V6M1

2

C10

10U_0805_6.3V6MC10

10U_0805_6.3V6M1

2

+C42

0.1U_0402_10V6K1

2

+C43

2

C23

10U_0805_6.3V6MC23

10U_0805_6.3V6M1

2

C4010U_0805_6.3V6MC4010U_0805_6.3V6M1

2

C2710U_0805_6.3V6MC2710U_0805_6.3V6M1

2

C16

10U_0805_6.3V6MC16

10U_0805_6.3V6M1

2

C3610U_0805_6.3V6MC3610U_0805_6.3V6M1

2JCPU1D

Penryn

.JCPU1D

VSS[083] P21VSS[084] P24VSS[085] R2VSS[086] R5VSS[087] R22VSS[088] R25VSS[089] T1VSS[090] T4VSS[091] T23VSS[092] T26VSS[093] U3VSS[094] U6VSS[095] U21VSS[096] U24VSS[097] V2VSS[098] V5VSS[099] V22VSS[100] V25VSS[101] W1VSS[102] W4VSS[103] W23VSS[104] W26VSS[105] Y3VSS[107] Y21VSS[108] Y24VSS[109] AA2VSS[110] AA5VSS[111] AA8VSS[112] AA11VSS[113] AA14VSS[114] AA16VSS[115] AA19VSS[116] AA22VSS[117] AA25VSS[118] AB1VSS[119] AB4VSS[120] AB8VSS[121] AB11VSS[122] AB13VSS[123] AB16VSS[124] AB19VSS[125] AB23VSS[126] AB26VSS[127] AC3VSS[128] AC6VSS[129] AC8VSS[130] AC11VSS[131] AC14VSS[132] AC16VSS[133] AC19VSS[134] AC21VSS[135] AC24VSS[136] AD2VSS[137] AD5VSS[138] AD8VSS[139] AD11VSS[140] AD13VSS[141] AD16VSS[142] AD19VSS[143] AD22VSS[144] AD25VSS[145] AE1VSS[146] AE4

VSS[106] Y6

VSS[001]

A4

VSS[149] AE14VSS[150] AE16VSS[147] AE8

VSS[163] AF25

C14

10U_0805_6.3V6MC14

10U_0805_6.3V6M1

2

C21

10U_0805_6.3V6MC21

10U_0805_6.3V6M1

2

C11

10U_0805_6.3V6MC11

10U_0805_6.3V6M1

2

C15

10U_0805_6.3V6MC15

10U_0805_6.3V6M1

2

C3210U_0805_6.3V6MC3210U_0805_6.3V6M1

2C26

10U_0805_6.3V6MC2610U_0805_6.3V6M1

2

C3510U_0805_6.3V6MC3510U_0805_6.3V6M1

2

C9

10U_0805_6.3V6MC9

10U_0805_6.3V6M1

2

C18

10U_0805_6.3V6MC18

10U_0805_6.3V6M1

2

C13

10U_0805_6.3V6MC13

10U_0805_6.3V6M1

2

C3810U_0805_6.3V6MC3810U_0805_6.3V6M1

2C34

10U_0805_6.3V6MC3410U_0805_6.3V6M1

2

C48

0.1U_0402_10V6KC48

0.1U_0402_10V6K1

2

+C41

2

C12

10U_0805_6.3V6MC12

10U_0805_6.3V6M1

2

C3110U_0805_6.3V6MC3110U_0805_6.3V6M1

2

C50

0.1U_0402_10V6KC50

0.1U_0402_10V6K1

2

C2510U_0805_6.3V6MC2510U_0805_6.3V6M1

2

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+H_SWNG

H_D#32

H_D#24H_D#19

H_D#59

H_D#42H_D#36H_D#3

H_D#40

H_RCOMP

H_D#55H_D#4

H_D#60

H_D#30

H_D#34H_D#27

H_D#1

H_D#23

H_D#51H_D#48H_D#46H_D#44H_D#39

H_D#22H_D#15H_D#9

H_D#56H_D#54H_D#8

H_RESET#

H_D#37H_D#35

H_D#28H_D#25H_D#12

H_D#38H_D#26

H_D#11H_D#7

H_D#53H_D#41

H_D#18H_D#10

+H_VREF

H_D#57

H_D#33H_D#29

+H_SWNG

H_D#6

H_D#45H_D#43H_D#20

H_D#61H_D#17

H_D#63H_D#58

H_D#21H_D#16

H_A#3

H_A#18

H_A#21

H_A#16H_A#19

H_A#31H_A#27H_A#5

H_A#30

H_A#9

H_A#26

H_A#14H_A#11

H_A#22

H_A#34H_A#20

H_A#8

H_A#15H_A#6

H_A#25H_A#17

H_A#4

H_A#13

H_A#33H_A#29H_A#10

H_DSTBN#1H_DSTBN#3H_DSTBN#0H_DSTBN#2

H_DSTBP#2H_DSTBP#0H_DSTBP#3H_DSTBP#1

H_REQ#0H_REQ#3H_REQ#1

H_REQ#4H_REQ#2

H_RS#1

MCH_CLKSEL0SMRCOMP_VOL

+CL_VREF

MCH_ICH_SYNC#

CLKREQ#_7M_PWROK

DMI_TXN0DMI_TXN2

DMI_TXP0DMI_TXP2

DMI_RXN0DMI_RXN2DMI_RXP0DMI_RXP2

MCH_SSCDREFCLKMCH_SSCDREFCLK#

SM_REXTV_DDR_MCH_REF

M_CLK_DDR3M_CLK_DDR#0M_CLK_DDR#2M_CLK_DDR2M_CLK_DDR0

SMRCOMP_VOHSMRCOMP_VOL

M_ODT1

SMRCOMP#

M_ODT3M_ODT0M_ODT2SMRCOMP

DDR_CKE0_DIMMADDR_CKE3_DIMMB

DDR_CS1_DIMMA#

DDR_CKE2_DIMMBDDR_CS0_DIMMA#

DDR_CS3_DIMMB#

MCH_CLKSEL1

CFG11CFG9CFG7

CFG10CFG6

CFG14CFG16

CFG8CFG5

CFG13

CFG18CFG12

CFG20

H_DPRSTP#

THERMTRIP#

PM_PWROKPM_EXTTS#1PM_BMBUSY#

H_BPRI# 6H_BNR# 6

H_DEFER# 6H_BR0# 6

H_DBSY# 6CLK_MCH_BCLK 17CLK_MCH_BCLK# 17H_DPWR# 7H_DRDY# 6H_HIT# 6H_HITM# 6H_LOCK# 6H_TRDY# 6

H_DINV#0 7H_DINV#1 7H_DINV#2 7H_DINV#3 7H_DSTBN#0 7H_DSTBN#1 7H_DSTBN#2 7H_DSTBN#3 7H_DSTBP#0 7H_DSTBP#1 7H_DSTBP#2 7H_DSTBP#3 7

H_REQ#3 6H_REQ#2 6H_REQ#1 6

H_REQ#4 6H_REQ#0 6

H_RS#2 6H_RS#1 6H_RS#0 6

MCH_CLKSEL017

MCH_CLKSEL117

MCH_CLKSEL217

TSATN# 31MCH_ICH_SYNC# 22M_PWROK 22,31

DMI_TXP0 22

DMI_RXN0 22

DMI_RXP0 22

DMI_TXN0 22DMI_TXN1 22DMI_TXN2 22DMI_TXN3 22

DMI_TXP1 22DMI_TXP2 22DMI_TXP3 22

DMI_RXN1 22DMI_RXN2 22DMI_RXN3 22

DMI_RXP1 22DMI_RXP2 22DMI_RXP3 22

CLK_MCH_3GPLL 17CLK_MCH_3GPLL# 17

MCH_SSCDREFCLK 17MCH_SSCDREFCLK# 17

CLK_MCH_DREFCLK 17CLK_MCH_DREFCLK# 17

DDR_CKE0_DIMMA 15DDR_CKE1_DIMMA 15DDR_CKE2_DIMMB 16DDR_CKE3_DIMMB 16

DDR_CS0_DIMMA# 15DDR_CS1_DIMMA# 15DDR_CS2_DIMMB# 16DDR_CS3_DIMMB# 16

M_CLK_DDR0 15M_CLK_DDR1 15M_CLK_DDR2 16M_CLK_DDR3 16

M_CLK_DDR#0 15M_CLK_DDR#1 15M_CLK_DDR#2 16M_CLK_DDR#3 16

M_ODT0 15M_ODT1 15M_ODT2 16M_ODT3 16

CLKREQ#_7 17

CFG511

CFG911CFG11

11 CFG1011

CFG611CFG711

CFG1311CFG1211

CFG1611CFG1811

CFG2011CFG1911

CFG811

CFG1411CFG1511CFG1711

PM_BMBUSY#

22

PM_EXTTS#015PM_EXTTS#116PM_PWROK22,31H_THERMTRIP#

6,21

SM_DRAMRST# 15,16

DDR3_SM_PWROK 39SYSON 31,33,39

PLT_RST#

20,25,26

CL_CLK0 22CL_DATA0 22

CL_RST# 22

+VCCP+VCCP

+3VS

+1.5V

+VCCP+1.5V

Title

Montevina UMA LA6121P 0.2Cantiga(1/6)-AGTL/DMI/DDRCustom

trace width and spacing is 10/20

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

Near B3 pin within 100 mils from NB

Layout note:

Route H_SCOMP and H_SCOMP# with trace

width, spacing and impedance (55 ohm) same

as FSB data traces

0621 add CLK and DAT for DVI

0830 Add pull-up and pull-down resistor.

*R44*Follow Intel feedback

Follow Design Guide For Cantiga: 80.6ohm

80% of 1.5V VCC_SM

20% of 1.5V VCC_SM

+V_DDR_MCH_REF generated by DC-DC

PV：：： follow check list ver:1.5 change to 10K ohm

delete test point for Placement.11/17

Delete them for placement 11/23

R311K_0402_1%

T28T17

R431K_0402_1%

2T23

R44499_0402_1%

R4510K_0402_1%

H_A#_30 B18H_A#_31 K17

H_A#_4 C15H_A#_5 F16H_A#_6 H13H_A#_7 C18H_A#_8 M16H_A#_9 J13

H_ADS# H12H_ADSTB#_0 B16H_ADSTB#_1 G17H_BNR# A9H_BPRI# F11H_BREQ# G12

H_DPWR# J11H_DRDY# F9

H_DSTBN#_0 L10H_DSTBN#_1 M7H_DSTBN#_2 AA5H_DSTBN#_3 AE6

H_DSTBP#_0 L9H_DSTBP#_1 M8H_DSTBP#_2 AA6H_DSTBP#_3 AE5

H_REQ#_0 B15H_REQ#_1 K13

H_REQ#_4 B14

H_A#_32 B20H_A#_33 F21H_A#_34 K21H_A#_35 L20

R4810K_0402_1%

R331K_0402_1%

R323.01K_0402_1%

SA_CK#_0 AR24SA_CK#_1 AR21SB_CK#_0 AU24

SA_CKE_0 BC28SA_CKE_1 AY28SB_CKE_0 AY36SB_CKE_1 BB36SA_CS#_0 BA17SA_CS#_1 AY16SB_CS#_0 AV16SB_CS#_1 AR13

SM_DRAMRST# BC36

SA_ODT_0 BD17SA_ODT_1 AY17SB_ODT_0 BF15SB_ODT_1 AY13SM_RCOMP BG22SM_RCOMP# BH21

DMI_RXN_0 AE41DMI_RXN_1 AE37DMI_RXN_2 AE47DMI_RXN_3 AH39DMI_RXP_0 AE40DMI_RXP_1 AE38DMI_RXP_2 AE48DMI_RXP_3 AH40DMI_TXN_0 AE35DMI_TXN_1 AE43DMI_TXN_2 AE46DMI_TXN_3 AH42DMI_TXP_0 AD35DMI_TXP_1 AE44DMI_TXP_2 AF46DMI_TXP_3 AH43

RESERVED

AL34

RESERVED

AN35 RESERVEDAK34

GFX_VR_EN C34

SM_RCOMP_VOH BF28SM_RCOMP_VOL BH28

RESERVED

M1

HDA_BCLK B28HDA_RST# B30HDA_SDI B29HDA_SDO C29HDA_SYNC A28DDPC_CTRLDATA M28

Trang 10

DDR_A_MA4DDR_A_MA2

DDR_A_MA5DDR_A_MA7DDR_A_MA9DDR_A_MA12DDR_A_MA10

DDR_A_DQS#0

DDR_A_DQS#3DDR_A_DQS#5DDR_A_DQS#7

DDR_A_DQS0DDR_A_DQS2DDR_A_DQS4DDR_A_DQS6

DDR_A_DM7DDR_A_DM5DDR_A_DM2

DDR_A_DM6DDR_A_DM4DDR_A_DM0DDR_A_DM3

DDR_A_CAS#

DDR_A_WE#

DDR_A_D63DDR_A_D61DDR_A_D59DDR_A_D57DDR_A_D55DDR_A_D51DDR_A_D49

DDR_A_D53DDR_A_D47DDR_A_D43DDR_A_D41

DDR_A_D15DDR_A_D11DDR_A_D9

DDR_A_D13

DDR_A_D21

DDR_A_MA14

DDR_B_RAS#

DDR_B_MA14DDR_B_MA10

DDR_B_DQS#7DDR_B_DQS#2DDR_B_DQS7DDR_B_DQS2DDR_B_DM3

DDR_B_D51DDR_B_D39DDR_B_D18

DDR_B_MA7

DDR_B_DQS0DDR_B_D7

DDR_B_D54

DDR_B_D4

DDR_B_D36DDR_B_D21

DDR_B_MA4DDR_B_DM0

DDR_B_D62

DDR_B_D34

DDR_B_D19DDR_B_D13

DDR_B_MA3DDR_B_DQS#6DDR_B_DM7

DDR_B_D50

DDR_B_MA6DDR_B_D6

DDR_B_D53DDR_B_D33

DDR_B_D3

DDR_B_D20

DDR_B_DQS#5DDR_B_BS1

DDR_B_D12

DDR_B_DQS3

DDR_B_MA0DDR_B_DQS#0

DDR_B_DM6DDR_B_DM4

DDR_B_D55DDR_B_D44

DDR_B_MA13DDR_B_MA1

DDR_B_D57DDR_B_D52

DDR_B_D2

DDR_B_D17

DDR_B_DQS#1DDR_B_DQS1DDR_B_D9

DDR_B_DQS4

DDR_B_MA9DDR_B_DQS#4

DDR_B_DM5DDR_B_DM2

DDR_B_D11

DDR_B_WE#

DDR_B_MA12

DDR_B_D56DDR_B_D48

DDR_B_D16DDR_B_D1

DDR_B_MA2DDR_B_DQS5DDR_B_D8

DDR_B_D63DDR_B_D37

DDR_B_D5

DDR_B_MA8

DDR_B_DQS#3DDR_B_DQS6

DDR_B_DM1DDR_B_CAS#

DDR_B_BS0 16DDR_B_BS1 16DDR_B_BS2 16

DDR_B_RAS# 16

DDR_B_WE# 16DDR_B_CAS# 16

Title

Montevina UMA LA6121P 0.2Cantiga(2/6)-DDR3 A/B CH

SA_CAS# BD20

SA_DM_0 AM37SA_DM_1 AT41SA_DM_2 AY41SA_DM_3 AU39SA_DM_4 BB12SA_DM_5 AY6SA_DM_6 AT7

SA_DQS_0 AJ44SA_DQS_1 AT44SA_DQS_2 BA43SA_DQS_3 BC37SA_DQS_4 AW12SA_DQS_5 BC8SA_DQS_6 AU8SA_DQS_7 AM7SA_DM_7 AJ5

SA_DQS#_0 AJ43SA_DQS#_1 AT43SA_DQS#_2 BA44SA_DQS#_3 BD37SA_DQS#_4 AY12SA_DQS#_5 BD8SA_DQS#_6 AU9SA_DQS#_7 AM8

SA_MA_0 BA21SA_MA_1 BC24

SA_MA_10 BC21SA_MA_11 BG26SA_MA_12 BH26SA_MA_13 BH17

SA_MA_2 BG24SA_MA_3 BH24SA_MA_4 BG25SA_MA_5 BA24SA_MA_6 BD24SA_MA_7 BG27SA_MA_8 BF25SA_MA_9 AW24

SA_RAS# BB20SA_WE# AY20

SB_CAS# BG16

SB_DM_0 AM47SB_DM_1 AY47SB_DM_2 BD40SB_DM_3 BF35SB_DM_4 BG11SB_DM_5 BA3SB_DM_6 AP1SB_DM_7 AK2SB_DQS_0 AL47SB_DQS_1 AV48SB_DQS_2 BG41SB_DQS_3 BG37SB_DQS_4 BH9SB_DQS_5 BB2SB_DQS_6 AU1SB_DQS_7 AN6SB_DQS#_0 AL46SB_DQS#_1 AV47SB_DQS#_2 BH41SB_DQS#_3 BH37SB_DQS#_4 BG9SB_DQS#_5 BC2SB_DQS#_6 AT2SB_DQS#_7 AN5

SB_MA_0 AV17SB_MA_1 BA25

SB_MA_10 BB16SB_MA_11 AW33SB_MA_12 AY33SB_MA_13 BH15

SB_MA_2 BC25SB_MA_3 AU25SB_MA_4 AW25SB_MA_5 BB28SB_MA_6 AU28SB_MA_7 AW28SB_MA_8 AT33SB_MA_9 BD33

SB_MA_14 AU33SB_RAS# AU17

SB_WE# BF14

Trang 11

TV_COMPSTV_LUMATV_CRMA

M_BLUE

LVDS_A1+

LVDS_A2-

LVDS_A0-LVDS_ACLK+

ENAVDD

LVDS_ACLK-DDC2_CLKDDC2_DATAENBKLENBKL

CRT_HSYNCCRT_VSYNC

CFG59

3VDDCDA183VDDCCL18

DDC2_DATA19

CFG69

CFG79

CFG89

CFG99

CFG109

CFG119

CFG129

CFG139

CFG149

CFG159

CFG179

CFG189

CFG169

CFG199

CFG209

ENBKL31

DDC2_CLK19

ENAVDD19

CRT_VSYNC18

M_BLUE18M_GREEN18M_RED18

CRT_HSYNC18

19LVDS_ACLK+

LVDS_ACLK-19

19LVDS_A1-19LVDS_A2-19

LVDS_A0-LVDS_A0+

19LVDS_A1+

19LVDS_A2+

19

INV_PWM_GL4019

+VCC_PEG

+3VS

+3VS+3VS

+3VS

Title

Montevina UMA LA6121P 0.2Cantiga(3/6)-VGA/LVDS/TV

Custom

PEGCOMP trace width and spacing is 20/25 mils.

000 = FSB 1066MHz

1 = The iTPM Host Interface is disable *

CFG[2:0] FSB Freq select

Reserved

Reserved CFG[15:14]

Strap Pin Table

Reserved CFG[18:17]

(Lane number in Order)

1 = PCIE/SDVO are operating simu.

0 = Only PCIE or SDVO is operational *

1 = Normal Operation,Lane Number in order

1 = DMI x 4

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality CFG5 (DMI select)

CFG19 (DMI Lane Reversal) CFG16 (FSB Dynamic ODT) CFG7

CFG20

CFG11 CFG[13:12] (XOR/ALLZ) CFG8

Follow Intel DG &

Checklist

(Intel Management Engine Crypto strap)

(PCIE Lookback enable)

(PCIE/SDVO concurrent)

Follow Intel DG &

@R734.02K_0402_1%

@R832.21K_0402_1%

R406 1 2 0_0402_5%

R724.02K_0402_1%

@R724.02K_0402_1%

@R812.21K_0402_1%

R6830.1_0402_1%

R6830.1_0402_1%1 2

R872.21K_0402_1%

@R872.21K_0402_1%

R822.21K_0402_1%

@R822.21K_0402_1%

@R714.02K_0402_1%

R782.21K_0402_1%

@R782.21K_0402_1%

@R852.21K_0402_1%

R6930.1_0402_1%1 2

R60 2.4K_0402_1%

R60 1 22.4K_0402_1%

R762.21K_0402_1%

@R762.21K_0402_1%

R862.21K_0402_1%

@R862.21K_0402_1%

PEG_RX#_0 H44PEG_RX#_1 J46PEG_RX#_2 L44PEG_RX#_3 L40PEG_RX#_4 N41PEG_RX#_5 P48PEG_RX#_6 N44PEG_RX#_7 T43PEG_RX#_8 U43PEG_RX#_9 Y43PEG_RX#_10 Y48PEG_RX#_11 Y36PEG_RX#_12 AA43PEG_RX#_13 AD37PEG_RX#_14 AC47PEG_RX#_15 AD39

PEG_RX_0 H43PEG_RX_1 J44PEG_RX_2 L43PEG_RX_3 L41PEG_RX_4 N40PEG_RX_5 P47PEG_RX_6 N43PEG_RX_7 T42PEG_RX_8 U42PEG_RX_9 Y42PEG_RX_10 W47PEG_RX_11 Y37PEG_RX_12 AA42PEG_RX_13 AD36PEG_RX_14 AC48PEG_RX_15 AD40PEG_TX#_0 J41

PEG_TX#_10 Y40

PEG_TX#_3 M40PEG_TX#_4 M42PEG_TX#_5 R48PEG_TX#_6 N38PEG_TX#_7 T40PEG_TX#_8 U37PEG_TX#_9 U40PEG_TX#_1 M46

PEG_TX#_11 AA46PEG_TX#_12 AA37PEG_TX#_13 AA40PEG_TX#_14 AD43PEG_TX#_15 AC46PEG_TX#_2 M47

PEG_TX_0 J42PEG_TX_1 L46PEG_TX_2 M48PEG_TX_3 M39PEG_TX_4 M43PEG_TX_5 R47PEG_TX_6 N37PEG_TX_7 T39PEG_TX_8 U36PEG_TX_9 U39PEG_TX_10 Y39PEG_TX_11 Y46PEG_TX_12 AA36PEG_TX_13 AA39PEG_TX_14 AD42PEG_TX_15 AD46

@R792.21K_0402_1%

R742.21K_0402_1%

@R742.21K_0402_1%

@R772.21K_0402_1%

R802.21K_0402_1%

@R802.21K_0402_1%

R754.02K_0402_1%

@R754.02K_0402_1%

R701.02K_0402_1%

R842.21K_0402_1%

@R842.21K_0402_1%

Trang 12

+3VS+3VS_TVDAC

+VCCP+1.05VS_DMI

+1.5V+1.5V_SM_CK

+1.05VS_DPLLA

+VCCP

+1.5VS+1.5VS_TVDAC

+VCC_PEG+VCCP

+1.8V+1.8V_LVDS

+1.5VS_PEG_BG

+1.5VS

+1.05VS_PEGPLL

+VCCP+1.05VS_DPLLB

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_MPLL

+1.05VS_DPLLB+1.05VS_HPLL+1.05VS_DPLLA

+3VS_TVDAC

+1.5VS_TVDAC+1.5VS_QDAC

+1.05VS_PEGPLL+1.05VS_HPLL

+1.8V_LVDS

+1.05VS_DMI+VCC_PEG

+3VS_HV+1.8V_TXLVDS+1.5V_SM_CK+V1.05VS_AXF

Title

Montevina UMA LA6121P 0.2Cantiga(4/6)-PWR

50mA414uA13.2mA64.8mA

26mA

321.35mA

118.8mA124mA

105.3mA

1732mA

456mA

TVA 24.15mATVX 24.15mA26mA

50mA

58.67mA48.363mA157.2mA50mA

60.31mA

**RED Mark: Means UMA & dis@ Power select**

~It check by INTEL Graphics Disable Guidelines~

pull low when no HDMI on 09/22

Change the size H to L.10/29

R112100_0603_1%

R930_0603_5%R930_0603_5%

D3

CH751H-40PT_SOD323-2D3

R1240_0402_5%

C10010U_0805_10V4ZC10010U_0805_10V4Z

R9410U_FLC-453232-100K_0.25A_10%

C1021U_0603_10V4Z

1

2

R91BLM18PG181SN1D_0603R91

C881000P_0402_50V7KC881000P_0402_50V7K

1

2

L1BLM18PG121SN1D_0603L1

BLM18PG121SN1D_0603

R950_0805_5%R950_0805_5%

R9010U_FLC-453232-100K_0.25A_10%

R10510_0402_5%

R1000_0805_5%

1

2

R970_0603_5%

R1020_0805_5%R1020_0805_5%

R1070_0603_5%

1

2

C964.7U_0805_10V4ZC964.7U_0805_10V4Z

R1040_0603_5%

@ R960_0603_5%

R1060_0402_5%

Trang 13

+VCCP

+VCCP+1.5V

Title

Montevina UMA LA6121P 0.2Cantiga(5/6)-PWR/GND

2

C1270.1U_0402_16V4Z

C1294.7U_0603_6.3V6M

VCC_NCTF AG30VCC_NCTF AF30VCC_NCTF AE30VCC_NCTF AL32

VCC_NCTF W30VCC_NCTF V30VCC_NCTF AK32

VCC_NCTF AH29VCC_NCTF AG29VCC_NCTF AE29

VCC_NCTF AL28VCC_NCTF AK28VCC_NCTF AL26VCC_NCTF AK26VCC_NCTF AJ32

VCC_NCTF AK24

VCC_NCTF AH32VCC_NCTF AG32VCC_NCTF AE32VCC_NCTF AC32

VCC_NCTF AC29VCC_NCTF AA29VCC_NCTF Y29VCC_NCTF W29VCC_NCTF V29

VCC_NCTF U30VCC_NCTF AL29VCC_NCTF AK29

VCC_NCTF AH30

VCC_NCTF AB30VCC_NCTF AA30VCC_NCTF Y30

0.22U_0402_10V4Z

1

2

T43PAD T43PAD

C1380.1U_0402_16V4Z

VCC_AXG_NCTF U20VCC_AXG_NCTF AM19VCC_AXG_NCTF AL19VCC_AXG_NCTF AK19VCC_AXG_NCTF AJ19VCC_AXG_NCTF AH19VCC_AXG_NCTF AG19VCC_AXG_NCTF AF19VCC_AXG_NCTF AE19VCC_AXG_NCTF AB19VCC_AXG_NCTF W26

VCC_AXG_NCTF AA19VCC_AXG_NCTF Y19VCC_AXG_NCTF W19VCC_AXG_NCTF V19VCC_AXG_NCTF U19VCC_AXG_NCTF AM17VCC_AXG_NCTF AK17VCC_AXG_NCTF AH17VCC_AXG_NCTF AG17VCC_AXG_NCTF AF17VCC_AXG_NCTF V26

VCC_AXG_NCTF AE17VCC_AXG_NCTF AC17VCC_AXG_NCTF AB17VCC_AXG_NCTF Y17VCC_AXG_NCTF W17VCC_AXG_NCTF V17VCC_AXG_NCTF AM16VCC_AXG_NCTF AL16VCC_AXG_NCTF AK16VCC_AXG_NCTF AJ16VCC_AXG_NCTF W25

VCC_AXG_NCTF AH16VCC_AXG_NCTF AG16VCC_AXG_NCTF AF16VCC_AXG_NCTF AE16VCC_AXG_NCTF AC16VCC_AXG_NCTF AB16VCC_AXG_NCTF AA16

VCC_AXG_NCTF V25VCC_AXG_NCTF W24VCC_AXG_NCTF V24VCC_AXG_NCTF W23

C13610U_0805_10V4Z

PAD T42PAD

Trang 14

VSS

AC15

VSS AM6VSS M6VSS C6VSS BA5VSS AH5VSS AD5VSS Y5VSS L5VSS J5VSS H5VSS F5VSS BE4

VSS BC3VSS AV3VSS AL3

VSS_NCTF AF32VSS_NCTF AB32VSS_NCTF V32VSS_NCTF AJ30VSS_NCTF AM29VSS_NCTF AF29VSS_NCTF AB29VSS_NCTF U26VSS_NCTF U23VSS_NCTF AL20VSS_NCTF V20VSS_NCTF AC19VSS_NCTF AL17VSS_NCTF AJ17VSS_NCTF AA17VSS_NCTF U17

VSS_SCB BH48VSS_SCB BH1VSS_SCB A48VSS_SCB C1VSS_SCB A3

VSS BA2

VSS AR2VSS AU2

VSS AP2

VSS F3

VSS AW2

VSS AE2VSS AF2VSS AH2VSS AJ2

VSS AD2VSS AC2VSS Y2VSS M2VSS K2VSS AM1VSS AA1VSS P1VSS H1

VSS

L12

VSSU2I

CANTIGA ES_FCBGA1329

VSSU2I

VSS

AY46

VSS G24VSS E24

VSS AG23

VSS B23

VSS AY24VSS AJ24

VSS AF24VSS R24

VSS K24VSS J24VSS F24

VSS BH23

VSS Y23VSS

AK15

VSS AD12

VSS AJ6

Trang 15

DDR_A_DQS#0DDR_A_DQS0DDR_A_D2

DDR_A_D0

DDR_A_D3

DDR_A_D39

DDR_A_D36DDR_A_DM4DDR_A_D38

PM_EXTTS#0

DDR_A_D53DDR_A_DM6DDR_A_D54DDR_A_D50

DDR_A_D49

DDR_A_D41

DDR_A_D44

DDR_A_DQS5DDR_A_DQS#5

DDR_A_MA13

DDR_A_D14DDR_A_D12

DDR_A_D15DDR_A_DQS1

DDR_A_DQS#1

DDR_A_D10DDR_A_D8

M_ODT1

DDR_A_D29

DDR_A_D31DDR_A_DQS3DDR_A_DQS#3

DDR_A_MA14

DDR_A_D28DDR_A_D25

DDR_A_MA2DDR_A_MA4

DDR_A_BS1DDR_A_RAS#

M_ODT0

DDR_A_D34DDR_A_DQS4DDR_A_DQS#4DDR_A_D32

DDR_A_DQS#2

DDR_A_D20

DDR_A_D18DDR_A_DQS2

DDR_A_D19DDR_A_D16

+V_DDR3_DIMM_REF

DDR_CKE0_DIMMA9

DDR_A_BS210

DDR_A_BS010

DDR_A_WE#

10DDR_A_CAS#

10

M_ODT1 9DDR_CS1_DIMMA#

9

DDR_CKE1_DIMMA 9

M_CLK_DDR1 9M_CLK_DDR#1 9

PM_EXTTS#0 9

DDR_A_BS1 10DDR_A_RAS# 10

M_CLK_DDR09

M_CLK_DDR#09

DDR_CS0_DIMMA# 9M_ODT0 9

Montevina UMA LA6121P 0.2DDRIII-SODIMM SLOT1Custom

R11081K_0402_1%

R11091K_0402_1%

Trang 16

DDR_B_D26DDR_B_D25

DDR_B_D27DDR_B_DM3DDR_B_D24

M_CLK_DDR2M_CLK_DDR#2

DDR_B_DQS7DDR_B_DQS#7

DDR_B_D49

DDR_B_DM6M_ODT3DDR_B_D21

DDR_B_DM7

DDR_B_D63

DDR_B_D60DDR_B_D54

DDR_B_D31DDR_B_D28

DDR_B_D30DDR_B_D29

DDR_B_DM1

DDR_B_D10DDR_B_D9

DDR_B_D11DDR_B_D8

DDR_B_D52DDR_B_DM5

DDR_B_MA1

DDR_B_BS0DDR_B_CAS#

DDR_B_D38

PM_EXTTS#1

DDR_B_D0

DDR_B_D2DDR_B_D1

DDR_B_D15DDR_B_D12

DDR_B_D14

DDR_CS2_DIMMB#

DDR_B_D5

DDR_B_D6DDR_B_D4

DDR_B_D7DDR_B_DM0

DDR_B_D22DDR_B_DM2DDR_B_D20

DDR_B_D23DDR_B_D19

DDR_B_D16

DDR_B_D44

DDR_B_D46

DDR_CKE2_DIMMB

DDR_B_D62

M_ODT2

DDR_B_DQS6DDR_B_DQS#6DDR_CS3_DIMMB#

DDR_B_D59DDR_B_D57

DDR_B_BS010

DDR_B_CAS#

10

PM_EXTTS#1 9

DDR_CS2_DIMMB# 9M_ODT2 9M_ODT3 9

DDR_B_MA[0 14]

10

DDR_B_D[0 63]

10DDR_B_DQS#[0 7]

10

DDR_B_DM[0 7]

10DDR_B_DQS[0 7]

Montevina UMA LA6121P 0.2DDRIII-SODIMM SLOT2

JDIMM2

TYCO_C-2013310CONN@

Trang 17

CLK_SMBCLKCLK_SMBDATA

ITP_ENREF1

FSA

R_CKPWRGDFSBCLK_XTAL_OUTCLK_XTAL_INFSC

CLK_SMBCLK

27_SELPCI_CLK3

R_MCH_DREFCLK

SSCDREFCLKR_PCIE_ICHR_PCIE_ICH#

R_PCIE_SATAR_PCIE_SATA#

R_MCH_3GPLL

R_CPU_BCLKR_CPU_BCLK#

R_MCH_BCLKR_MCH_BCLK#

ICH_SMBCLK22,26

ICH_SMBDATA22,26

CLK_PCI_ICH20

CLK_48M_ICH22

CK_PWRGD22

CLK_14M_ICH22

CLK_PCI_EC31

MCH_SSCDREFCLK 9MCH_SSCDREFCLK# 9CLK_PCIE_ICH 22CLK_PCIE_ICH# 22

CLK_PCIE_SATA# 21CLK_PCIE_SATA 21

CLKREQ#_C 22

CLK_PCIE_MCARD2# 26CLK_PCIE_MCARD2 26CLKREQ#_6 26CLK_MCH_3GPLL 9CLK_MCH_3GPLL# 9CLK_MCH_BCLK#

9CLK_MCH_BCLK9

CLK_CPU_BCLK#

6CLK_CPU_BCLK6

H_STP_PCI# 22

CLK_MCH_DREFCLK#

9CLK_MCH_DREFCLK9

CLK_DEBUG_PORT_126

CLK_SD_48M27

CLK_SMBCLK 15,16CLK_SMBDATA 15,16

+VCCP+VCCP

VGATE22,41

Title

Montevina UMA LA6121P 0.2Clock Generator CK505

Place close to U51

CPU NB

XDP/ITP

100

PCI MHz 266

SRC MHz CLKSEL2

33.3 0

MHz DOT_96 MHz USB MHz

133 1 200 166 333

1 = Enable SRC0 & 27MHz(DIS)

0 = Enable DOT96 & SRC1(UMA)

ITP_EN

Vendor suggests 22pF

NB (UMA)

NB_SSC (UMA) ICH

SATA

LAN

3G_PLL MiniCard_2(WLAN)

No Debug port anymore

CPU MHz CLKSEL1

FSB

CLKSEL0

FSA

48.0 48.0 48.0 48.0 48.0 48.0

96.0 96.0 96.0 96.0 96.0 96.0

14.318 14.318 14.318 14.318 14.318 14.318

33.3 33.3 33.3 33.3 33.3 33.3

100 100 100 100 100 100 100 400

Change 33M and 48M damping to 39M by EMI request

02/13 Add 12P on CLK_14M_ICH for WWAN noise

delete TV on 09/17 need check clkreq#

delete New card on 09/17 need check clkreq# delete clock for cardreader on 09/18

add 48MHZ for cardreader 09/22

R1710_0402_5%

SLG8SP553VTR_QFN72_10x10U3

2

T44R150

1K_0402_5%

R1501K_0402_5%

Y114.318MHZ_16PF_7A14300083Y1

@R1570_0402_5%

0.1U_0402_16V4Z

1

2

R18210K_0402_5%

@R18210K_0402_5%

@

C21418P_0402_50V8JC21418P_0402_50V8J1

2

C2155P_0402_50V8C

@C2155P_0402_50V8C

C206

10U_0805_10V4ZC206

R1792.2K_0402_5%

R1651K_0402_5%

C2110.1U_0402_16V4ZC2110.1U_0402_16V4Z1

2

R191 10K_0402_5%

@R191 10K_0402_5%

@

R1391K_0402_5%

@R1391K_0402_5%

2

R1282.2K_0402_5%

C2174.7P_0402_50V8C

@C2174.7P_0402_50V8C

2

R1291K_0402_5%

C2000.1U_0402_16V4ZC2000.1U_0402_16V4Z1

2

R136 0_0402_5%

R136 1 2 0_0402_5%

R1740_0402_5%

@R1740_0402_5%

@

C21612P_0402_50V8JC21612P_0402_50V8J2 1

R130 0_0402_5%

R130 1 2 0_0402_5%

C2030.1U_0402_16V4ZC2030.1U_0402_16V4Z1

2

C2184.7P_0402_50V8C

@C2184.7P_0402_50V8C

@R1431K_0402_5%

@

R18110K_0402_5%

@R18110K_0402_5%

R18310K_0402_5%

R18010K_0402_5%

Q3B

2N7002DW-7-F_SOT363-6Q3B

2N7002DW-7-F_SOT363-63

R1782.2K_0402_5%

C208

0.1U_0402_16V4ZC208

0.1U_0402_16V4Z

1

2

C21318P_0402_50V8JC21318P_0402_50V8J

12

R1631K_0402_5%

@R1631K_0402_5%

Trang 18

3VDDCCLD_DDCDATA

D_DDCCLK

BLUEM_BLUE

M_RED

GREENREDM_GREEN

REDBLUE

RED

GREENBLUE

CRT_HSYNC11

CRT_VSYNC11

3VDDCDA 11

3VDDCCL 11

M_RED11

M_GREEN11

M_BLUE11

+CRTVDD+RCRT_VCC

+5VS

+CRTVDD

+3VS+CRTVDD +CRTVDD

Montevina UMA LA6121P 0.2CRT Connector

W=40mils CRT Connector

Place close to JCRT1

C2220.1U_0402_16V4ZC2220.1U_0402_16V4Z

D4

RB491D_SC59-3D4

R1882.2K_0402_5%

L3NBQ100505T-800Y-N_2PL3NBQ100505T-800Y-N_2P1 2

U4SN74AHCT1G125GW_SOT353-5U4

SN74AHCT1G125GW_SOT353-5A

1.1A_6VDC_FUSE

21

R1872.2K_0402_5%

R1840_0603_5%

C224

5P_0402_50V8CC224

5P_0402_50V8C1

1

2

L2

NBQ100505T-800Y-N_2PL2

NBQ100505T-800Y-N_2P1 2

C223

5P_0402_50V8CC223

5P_0402_50V8C1

R1890_0603_5%

L4

NBQ100505T-800Y-N_2PL4

NBQ100505T-800Y-N_2P1 2

U5SN74AHCT1G125GW_SOT353-5U5

SN74AHCT1G125GW_SOT353-5A

SUYIN_070546FR015S265ZRCONN@

GNDJCRT1

SUYIN_070546FR015S265ZRCONN@

6111

122133

144105

16

Trang 19

USB20_N4USB20_P4

DMIC_DATDMIC_CLK

BKOFF#

DMIC_DATINV_PWM_R

INV_PWM_R

BKOFF#

DDC2_DATADDC2_CLK

LVDS_A2+

LVDS_A2-LVDS_A1+

LVDS_A1-LVDS_A0+

LVDS_ACLK-LVDS_ACLK+

LVDS_A0-USB20_P422

USB20_N422

ENAVDD11

INV_PWM 31INV_PWM_GL40 11

LVDS_A1+ 11LVDS_A1- 11

LVDS_A0+ 11LVDS_A0- 11

LVDS_ACLK+ 11LVDS_ACLK- 11

INVPWR_B+

+LCDVDD+3VS

+3VS

+LCDVDD+5VALW

+LCDVDD+LCDVDD

Montevina UMA LA6121P 0.2LCD CONN.

LVDS CONN & USB Camera + Dig Mic

0308_Install all cap for EMI request.

0831 EMI request

Avoid Panel display garbage after power on.

0308_Reserve L10 and install L11.

delete +5VS transfer to +USB_CAM.10/26

delete Pin28 LOG PWR.10/26

R2032.2K_0402_5%

Q8B2N7002DW-7-F_SOT363-6Q8B

R2022.2K_0402_5%

R198470_0805_5%

L6FBMA-L11-201209-221LMA30T_0805L6

1

2

C434680P_0402_50V7KC434680P_0402_50V7K1

C302

220P_0402_25V8JC302

0.1U_0402_16V4Z

1

2

R1991M_0402_5%

C303

220P_0402_25V8JC303

220P_0402_25V8J1

2

C2380.047U_0402_16V7KC2380.047U_0402_16V7K

R201100K_0402_5%

JLVDS1

ACES_87142-4041-BSJLVDS1

Q7AO3413_SOT23-3

0.1U_0402_16V4Z

@1

2

R5940_0402_5% R5940_0402_5%

@R5960_0402_5%

Trang 20

PCI_PME# 31CLK_PCI_ICH 17PLT_RST# 9,25,26

Montevina UMA LA6121P 0.2ICH9(1/4)-PCI/INT

PCI PCI_GNT0# SPI_CS#1

1

Boot BIOS Strap

*

LPC SPI

A16 swap override Strap

@

R2961K_0402_5%

C/BE0# D8C/BE1# B4C/BE2# D6C/BE3# A5

IRDY# D3PAR E3PCIRST# R1DEVSEL# C6PERR# E4PLOCK# C2SERR# J4STOP# A4TRDY# F5FRAME# D7PLTRST# C14PCICLK D4PME# R2

PIRQE#/GPIO2 H4PIRQF#/GPIO3 K6PIRQG#/GPIO4 F2PIRQH#/GPIO5 G2

@R28010_0402_5%

@C4258.2P_0402_50V

@1

Trang 21

SATA_TXP0_CSATA_TXN0_CSATA_TXP0

HDA_SDOUT_CODEC

ICH_RTCX2

HDA_SDIN0HDA_SYNC

GATEA20H_A20M#

LPC_AD1

ICH_RTCX1ICH_RTCX2

SATA_ITX_DRX_N4

SATA_RXN0_C24

SATA_RXP0_C24

SATA_TXN024SATA_TXP024

HDA_SDIN028

SATA_LED#

32

H_DPSLP# 7

H_FERR# 6H_PWRGOOD 7

H_IGNNE# 6

H_INIT# 6

H_NMI 6H_SMI# 6H_STPCLK# 6

H_THERMTRIP# 6,9

LPC_AD[0 3] 26,31

LPC_FRAME# 26,31

H_A20M# 6GATEA20 31

H_INTR 6KB_RST# 31

ICH_RSVD 22

HDA_SDOUT_CODEC28

CLK_PCIE_SATA# 17CLK_PCIE_SATA 17

HDA_RST#_CODEC28

HDA_SYNC_CODEC28

+3VS

+RTCVCC+CHGRTC

+RTC_BATT

H_DPRSTP# 7,9,41

SATA_ITX_RPI_DRX_N4 24SATA_ITX_RPI_DRX_P4 24SATA_DTX_C_IRX_P4 24SATA_DTX_C_IRX_N4 24

Title

Montevina UMA LA6121P 0.2ICH9(2/4)_LAN,HD,IDE,LPCCustom

XOR CHAIN ENTRANCE STRAP:RSVD

placed within 2"

from ICH9M within 2" from R379

ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_LAN100_SLP Low = Internal VR Disabled

High = Internal VR Enabled(Default)

ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)

1

Add 12p on HDA_SDOUT and HDA_SDOUT

02/13 Reserve cap on HDA_BITCLK for WWAN noise issue

PV：：： follow check list ver:1.5 change to 8.2K ohm

delete MDC and HDMI on 09/17

add pull high to +3VS 09/22

R31124.9_0402_1%

15P_0402_50V8J1

2

C33112P_0402_50V8JC33112P_0402_50V8J

C436

15P_0402_50V8JC436

R312 33_0402_5%

R312 33_0402_5% 1 2

R30110K_0402_5%

R31556_0402_5%

R30656_0402_5%

@R30656_0402_5%

@

T55PADT55PAD

BAS40-04_SOT2312

ML1220T13RE

@

12

R30856_0402_5%

R32224.9_0402_1%

C427

1U_0603_10V4ZC427

1U_0603_10V4Z

1

2

C1930.1U_0402_16V4ZC1930.1U_0402_16V4Z

R250560_0603_5%

Y2

32.768KHZ_12.5P_MC-146Y2

R249560_0603_5%

R31310K_0402_5%

T56PADT56PAD

LDRQ0# J3LDRQ1#/GPIO23 J1A20GATE N7A20M# AJ27

DPRSTP# AJ25DPSLP# AE23FERR# AJ26

CPUPWRGD AD22IGNNE# AF25

INIT# AE22INTR AG25RCIN# L3NMI AF23SMI# AF24

STPCLK# AH27THRMTRIP# AG26

SATA4RXN AH11SATA4RXP AJ11SATA4TXN AG12SATA4TXP AF12

SATA5RXN AH9SATA5RXP AJ9SATA5TXN AE10SATA5TXP AF10

SATA_CLKN AH18SATA_CLKP AJ18SATARBIAS# AJ7SATARBIAS AH7

Trang 22

GPIO10EC_LID_OUT#

CLKREQ#_CPM_BMBUSY#

GPIO49

SIRQ

CLK_48M_ICH

GPIO57GPIO39

OCP#

GPIO6

GPIO18GPIO19GPIO20

EC_SCI#_SB

R_EC_RSMRST#

GPIO37ICH_SMBCLK

USB_OC#0EC_LID_OUT#

USB_OC#7

PCIE_RXN3

USB20_P5

DMI_TXN3DMI_RXN1

CK_PWRGDICH_LOW_BAT#

ICH_RSVD

USB20_P6DMI_RXP2

H_STP_PCI#

GPIO18

CLK_PCIE_ICH#

DMI_RXP0CL_VREF0_ICHICH_PCIE_WAKE#

GLAN_TXP_C

DMI_TXN0

DIS/UMA

CL_VREF1_ICHGPIO20

USB_OC#4

USB20_N5

DMI_TXN1LAN_WOL_EN

USBRBIAS

PCIE_C_TXN3PCIE_RXP3

DMI_IRCOMP

17/14OCP#

SLP_S3#

ICH_SUSCLK

GPIO57VGATELINKALERT#

R_STP_CPU#

GPIO21

GPIO49ICH_RI#

CLK_14M_ICH

THERM_SCI#

USB_OC#9

DMI_TXP3DMI_RXP1

GPIO36

MCH_ICH_SYNC#

GPIO38GPIO22ME_EC_CLK1

USB_OC#2

USB20_N1

DMI_RXP3DMI_TXP2DMI_TXP0CLKREQ#_C

USB_OC#11USB_OC#6

USB20_N6USB20_N4

DMI_TXP1

USB20_N2

USB20_N7USB20_P7

USB20_N4 19USB20_P4 19USB20_N5 26USB20_P5 26

DMI_RXP0 9DMI_RXN0 9

DMI_TXP0 9DMI_TXN0 9

CLK_PCIE_ICH# 17CLK_PCIE_ICH 17

USB20_N1 29USB20_P1 29

USB20_N0 29USB20_P0 29

ICH_SMBCLK17,26ICH_SMBDATA17,26

CLK_48M_ICH 17CLK_14M_ICH 17

SLP_S3# 31SLP_S5# 31

PM_PWROK 9,31

PWRBTN_OUT# 31

M_PWROK 9,31CK_PWRGD 17

17

ICH_PCIE_WAKE#

25,26SIRQ31THERM_SCI#

ICH_RSVD21

EC_SMI#

31

CLKREQ#_C17

OCP#

6

SPI_CS1#_R20

PCIE_TXN3

26 PCIE_RXP326PCIE_TXP326

PM_BMBUSY#

9

PCIE_RXN326

USB20_P2 29USB20_N2 29

SLP_S4# 31,33

R_EC_RSMRST# 37

USB20_N7 27USB20_P7 27

CL_CLK0 9

CL_DATA0 9

CL_RST# 9

USB_OC#229USB_OC#029

+3VALW

+3VS

GLAN_RXN25GLAN_RXP25GLAN_TXN25GLAN_TXP25

DPRSLPVR 9,41

VGATE17,41

Title

Montevina UMA LA6121P 0.2ICH9(3/4)_DMI,USB,GPIO,PCIECustom

Place closely pin H1 Place closely

pin AF3

Low >default High >No boot

USB-4 Camera USB-5 WLAN USB-6 Bluetooth USB-1 Daughter board

NA lead free

Within 500 mils R366

USB-0 Daughter board

Within 500 mils WLAN

Modify back to GPIO19 on 09/22

Board ID

LAN

11/17 Swap PCIE LAN and New card

11/17 Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue

Delete HDCP ROM.11/09

#PV PWROK sequence issue

04/29 MV-1 add R337 clock REQ pull high

05/08 MV-1 Delete R739

USB-2 On Mather board

delete TV on 09/17

delete New Card on 09/17

delete New card function for GPIO48 on 09/17

USB-6 Cardreader modify cardreader from PCIE to USB on 0918

Delete GPIO6 function for cardreader on 09/18

Delete WXMIT_OFF# for WWAN 1104

Change XMIT_OFF to EC contral.01/11

R34010K_0402_5%

@R34010K_0402_5%

DMI1RXN Y27DMI1RXP Y26DMI1TXN W29DMI1TXP W28

DMI2RXN AB27DMI2RXP AB26DMI2TXN AA29DMI2TXP AA28

DMI3RXN AD27DMI3RXP AD26DMI3TXN AC29DMI3TXP AC28

DMI_CLKN T26DMI_CLKP T25DMI_ZCOMP AF29DMI_IRCOMP AF28

USBP0N AC5USBP0P AC4USBP1N AD3USBP1P AD2USBP2N AC1USBP2P AC2USBP3N AA5USBP3P AA4USBP4N AB2USBP4P AB3USBP5N AA1USBP5P AA2USBP6N W5USBP6P W4USBP7N Y3USBP7P Y2USBP8N W1USBP8P W2USBP9N V2USBP9P V3USBP10N U5USBP10P U4USBP11N U1USBP11P U2

T72PAD T72PAD

R368453_0402_1%

R74810K_0402_5%

T62PAD T62PAD

@R33910K_0402_5%

R38422.6_0402_1%

R363453_0402_1%

R34710K_0402_5%R34710K_0402_5%

@R74710K_0402_5%

T74PAD T74PAD

CLK14 H1CLK48 AF3SUSCLK P1

SLP_S3# C16SLP_S4# E16SLP_S5# G17S4_STATE#/GPIO26 C10

PWROK G20

DPRSLPVR/GPIO16 M2BATLOW# B13

PWRBTN# R3LAN_RST# D20

RSMRST# D22

CK_PWRGD R5CLPWROK R6

SLP_M# B16CL_CLK0 F24CL_CLK1 B19

CL_DATA0 F22CL_DATA1 C19CL_VREF0 C25CL_VREF1 A19

CL_RST0# F21CL_RST1# D18

TP11

A20

C448 0.1U_0402_16V4ZC4481 2 0.1U_0402_16V4Z

R353100K_0402_5%1 2

Trang 23

Montevina UMA LA6121P 0.2ICH9(4/4)_POWER&GNDCustom

G3: 6uA 646mA 2mA

212mA

11mA 11mA

308mA

23mA 48mA 2mA

(DMI)

20 mils

C456

2.2U_0603_6.3V4ZC456

2.2U_0603_6.3V4Z

1

2

C4570.1U_0402_16V4Z

C4570.1U_0402_16V4Z1

2

T71

C4750.1U_0402_16V4Z

0.1U_0402_10V6K1

2

R2120_0402_5%

@R2120_0402_5%

@

C4781U_0603_10V4ZC4781U_0603_10V4Z

2

R741150_0402_1%

@R741150_0402_1%

0.1U_0402_16V4Z

1

2

R390 CHB1608U301_0603R390 CHB1608U301_0603

C46010U_0805_10V4Z

10U_0805_10V4Z1

C4550.1U_0402_16V4Z1

2

C4610.01U_0402_16V7K

1

2

C4861U_0603_10V4Z

@C4861U_0603_10V4Z

@1

VCCDMIPLL R29VCC_DMI[1] W23VCC_DMI[2] Y23

V_CPU_IO[1] AB23V_CPU_IO[2] AC23VCC3_3[01] AG29VCC3_3[02] AJ6VCC3_3[07] AC10VCC3_3[03] AD19VCC3_3[04] AF20VCC3_3[05] AG24VCC3_3[06] AC20

VCC3_3[08] B9VCC3_3[09] F9VCC3_3[10] G3VCC3_3[11] G6VCC3_3[12] J2VCC3_3[13] J7VCC3_3[14] K7

VCCHDA AJ4

VCCSUSHDA AJ3

VCCSUS1_05[1] AC8VCCSUS1_05[2] F17

VCCSUS1_5[1] AD8VCCSUS1_5[2] F18

VCCSUS3_3[01] A18VCCSUS3_3[02] D16VCCSUS3_3[03] D17VCCSUS3_3[04] E22

VCCSUS3_3[05] AF1

VCCSUS3_3[06] T1VCCSUS3_3[07] T2VCCSUS3_3[08] T3VCCSUS3_3[09] T4VCCSUS3_3[10] T5VCCSUS3_3[11] T6VCCSUS3_3[12] U6VCCSUS3_3[13] U7VCCSUS3_3[14] V6VCCSUS3_3[15] V7VCCSUS3_3[16] W6VCCSUS3_3[17] W7VCCSUS3_3[18] Y6VCCSUS3_3[19] Y7VCCSUS3_3[20] T7

VCCCL1_05 G22VCCCL1_5 G23

VCCCL3_3[1] A24VCCCL3_3[2] B24

U12E

ICH9-M ES_FCBGA676U12E

ICH9-M ES_FCBGA676

VSS[107] H5VSS[108] J23VSS[109] J26VSS[110] J27VSS[111] AC22VSS[112] K28VSS[113] K29VSS[114] L13VSS[115] L15VSS[116] L2VSS[117] L26VSS[118] L27VSS[119] L5VSS[120] L7VSS[121] M12VSS[122] M13VSS[123] M14VSS[124] M15VSS[125] M16VSS[126] M17VSS[127] M23VSS[128] M28VSS[129] M29VSS[130] N11VSS[131] N12VSS[132] N13VSS[133] N14VSS[134] N15VSS[135] N16VSS[136] N17VSS[137] N18VSS[138] N26VSS[139] N27VSS[140] P12VSS[141] P13VSS[142] P14VSS[143] P15VSS[144] P16VSS[145] P17VSS[146] P2VSS[147] P23VSS[148] P28VSS[149] P29VSS[150] P4VSS[151] P7VSS[152] R11VSS[153] R12VSS[154] R13VSS[155] R14VSS[156] R15VSS[157] R16VSS[158] R17VSS[159] R18VSS[160] R28VSS[161] T12VSS[162] T13VSS[163] T14VSS[164] T15VSS[165] T16VSS[166] T17VSS[167] T23VSS[168] B26VSS[169] U12VSS[170] U13VSS[171] U14VSS[172] U15VSS[173] U16VSS[174] U17VSS[175] AD23VSS[176] U26VSS[177] U27VSS[178] U3VSS[179] V1VSS[180] V13VSS[181] V15VSS[182] V23VSS[183] V28VSS[184] V29VSS[185] V4VSS[186] V5VSS[187] W26VSS[188] W27VSS[189] W3VSS[190] Y1VSS[191] Y28VSS[192] Y29VSS[193] Y4VSS[194] Y5VSS[195] AG28VSS[196] AH6VSS[197] AF2VSS[198] B25

VSS_NCTF[01] A1VSS_NCTF[02] A2VSS_NCTF[03] A28VSS_NCTF[04] A29VSS_NCTF[05] AH1VSS_NCTF[06] AH29VSS_NCTF[07] AJ1VSS_NCTF[08] AJ2VSS_NCTF[09] AJ28VSS_NCTF[10] AJ29VSS_NCTF[11] B1VSS_NCTF[12] B29

D9CH751H-40_SC76D9CH751H-40_SC76

C472

0.1U_0402_10V6KC472

0.1U_0402_10V6K1

CHB1608U301_0603

C4730.1U_0402_16V4Z

Tiêu đề	Compal Confidential Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M Core Logic
Trường học	Compal Electronics, Inc.
Chuyên ngành	Engineering
Thể loại	Engineering Drawing
Năm xuất bản	2010
Thành phố	Taipei

Định dạng
Số trang	46
Dung lượng	1,28 MB