Acer aspire 3 a315 56 compal FH5LI LA j801p rev 1 0 схема

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS usto FH5LI M/B LA-H801P 1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC...

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Compal Confidential FHSLI MB Schematic Document

Security Classification Compal Secret Data Compal Electronics, Inc

Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title ,

Cover Sheet

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Fg; 5 7 Numb Fy AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ze | Yocument Number ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS usto FH5LI M/B LA-H801P 1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Date: Wednesday, October 30, 2019 [Sheet 1 of 102

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HDMI Conn eDP Interleaved Memory

Dual Channel

HDM x 4 lanes

JSB3 port 1 USB2 port3 (MB) Camera

USB2 port1 USB2port4(SUB) USB2 port7

USB2 port 101 page 52 ¬ , 50x25 mm | Touch

Realtek 8111H| Conn - = Conn : : _ 1526p; pin BGA HDA Codec USB2 port 6

page 56 page 38 page 56

page Int.KBD PS2 og Yrom Fs (from EC) /12C (from SOC (FP) I 6

LID /B Security Classification Compal Secret Data Compal Electronics, Inc

Power Circuit DC/DC page 63 Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title Block Diagrams

page 81~100 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ae 1 Document Number lở 0

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC | FH5LI M/B LA-H801P _

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Board ID Table for AD channel

Finger print power FP3V@/FP5V@

SATA/ODD select RD@/NRD@/ODD@

NOX76@/X76DSAM

MD BOM Select XZ©DMICG /X7eDHYNĐ/

SIGNAL STATE ISLP_S3#|SLP_S4# |SLP_S5#| +VALW +VY +VS Clock

SO (Full ON) HIGH | HIGH HIGH ON ON ON ON S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF

Voltage Rails

Power Plane Description so S4 | S4/S5 +19V_VIN Adapter power supply N/A | N/A | N/A +12.6V_BATT Battery power supply N/A | N/A | N/A +19VB AC or battery power rail for power circuit N/A | N/A | N/A +VCCIN Core voltage for CPU ON | OFF| OFF +VCCIN_AUX CPU and PCH merged auxiliary power rail ON | OFF| OFF +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON | OFF | OFF +1.05VO_OUT_FETI FIVR output of PCH to platform 1.05V Power Gates ON | ON | OFF +1.05V_VCCST Sustain voltage for CPU standby modes ON | ON | OFF +1.05VS_VCCSTG| Gated sustain voltage for CPU standby modes ON OFF/ON OFF +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF +1.2V_VCCPLL_O@ 1.2V power rail for CPU digital PLL ON | ON | OFF +1.8VALW_PRIM | +1.8V Always power rail ON | ON | ON*1 +1.8VS System +1.8V power rail ON | OFF| OFF +3VLP +19VB to +3VLP power rail for suspend power ON | ON | ON +3VALW System +3VALW always on power rail ON ON ON"1 +3VALW_PRIM +3VALW power for PCH suspend rails ON ON ON*1 +3VS System +3V power rail ON | OFF] OFF +5VALW +5V Always power rail ON | ON | ON +5VS System +5V power rail ON | OFF] OFF +RTCVCC RTC Battery Power ON | ON | ON

431ALBBOL01 SMT MB AJ8O1 FHSLI I31005D1 HDMI 255@/3S@/MEM@/15@/VOL@/CNVI@/CMC@/SDP@/MP@/FP@/FP3V@/i3@/NRD@/PCB@

431ALBBOL02 SMT MB AJ8O1 FHSLIT 151035D1 HDMI 255@/3S@/MEM@/15@/VOL@/CNVI@/CMC@/SDP@/MP@/FP@/FP3V@/i5 @/NRD@/PCB@

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C7 SYSON G9661MF11U PUM2 LAN_PWR_EN \] SY6288C20AAC UL1 TP_PWR_EN \] SY6288C20AAC UK1 WLAN_ON \] SY6288C20AAC UM1

FP_PWR_EN SY6288C20AAC UK6)FP@

+FP_VCC

+3VALW_TPM

[R-Short ]

smear (PUM) +0.6VSP JUMP pina SY8288CRAC 1UMP AOZ1331DI JUMP (pUs0) +5VALWPIÄ rnIison +5VALWH 3 +5VS_OUT Nae

hye CÁC +USB3_VCCB 11D1

LID/B 1IO1 IO/B

SY8286BRAC (PU301) +3VALWPED brag +3VALW R-Short +3VALW_DSW

R-Short F1

R-Short

+TS_PWR AP2330W

+HDMI_5V_OUT

+5VS_HDD +5VS_ODD

+VDDA +VCC_FAN1

CAMERA

JMIC1

+1.8VALWP

hi (UGIả) 1V I" SÄ+.sv_PRiM_soc_P I" 3 UPCS) I" 3 +1.8V_PRIM_SOC |

+1.05V_VCCST_DUAL it San I" 3 +1.05VS_VCCSTG |

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FH5LI_EVT Power Sequence BIOS ver: V0.01T015 EC: ver: VO.O1T08B

Plug in

+19VB +3VLP

+5VALW ON/OEFFBTN#

3V_EN +3VALW SPOK_3V

+1.05V_VCCST EC_RSMRST#

(DSW_PWROK) AC_PRESENT

PBTN_OUT#

SLP_S4#

SLP_S3#

SYSON +1 2V_VDDQ +2.5V_VPP SusP#

+5V8 +3V8

+1.8V8

SM_PG_CTRL +0.6VS_VTT

EC_VCCST_PG_R VR_ON +VCCIN PCH_PWROK SYSPWROK PLT_RST#

EC_ON

+5VALW

ON/OEFFBTN#

3V_EN +3VALW SPOK_3V

1 8VALW_PRIM

1 8VALW_PG

+VCCIN_AUX

VCCST_OVERRIDE_LS EC_VCCST_EN

+1.05V VCCST

EC_RSMRST#

(DSW_PWROK)

3.463us SYSON

515.9u5

+1.2V_VDDQ +2.5V_VPP

+5V8

1.170ms +3V8

4.5994

“ SM_PG_CTRL

693.9us

— \1476us

348.8us

PLT RST#

Security Classification | Compal Secret Data

Issued Date | 2019/07/12 | Deciphered Date 2019/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONF IDEN’

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Ri DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, ING NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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<38> EDP_TXP1 ya] DDIA_TXP_1 TCPO_TX_P1 pHa

— <38> EDP_AUXP SS BAN TCPO_AUX_P -#——<

— <40> SOG DP2 N0 RES DDIB_TXN 0 pl ARS

<40> SOC_DP2_N2 AG3 DDIB_TXN_2 TCP1_TX_P1 FEBE

<^““ | ppIs AUxP — TCP1_AUX_N TW Ice Lake-U CPU SKU

4SOC GPP E21 mm GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1 -}——<

<40> SOO DP2 HPD TSOC_GPP_ATS CVA6 | GPP_A18/DDSP_HPDB/DISP_MISCB TCP3 TXRX N0 | ERZ*

ry

Ts†aIP@ #4 1SO0-GPT—A20 OVá2 | GPP A19/DDSP HPD1/DISP MISC1 TCP3_TXRX_PO [-BT2><

1303 IP@ ®-€ SE-Ocr7 CRải | GPP A20/DDSP_HPD2/DISP_MISG2 TCP3 TXRX N1 [ET{T

UEB OC27 CT4i | GPP_A14/USB OG1 N/DDSP_HPD3/DISP_MISC3 — TCP4 TXRX P1 ——<

EDP_VDDEN: <38> SOC ENVDD DN21 EDP VDDEN TCP3_AUX_P ->——*«

190K PD on load swith side 1 with si 258s ENBKL — ENBKL BL EDP BKLTEN — 1G HGOMP_N AVI TC_RCOMP_N C_RCOMP RC351_1 2 150 0402 1% 6

GPP_A17/DISP_MISCC Leva

ậ RC164 1 2_10K 0402 5% USB OC1# 10f19

RC165 1 “YY 2 10K 0402 5% USB OC2f RC350 ICL-U_BGA1526

150_0402_ 1% @

Table 5-11 USB3/USB2 Port Pairing for USB Type-C Connectors

Reserve Test Point

TBI LSX #0 PINS VCCIO CONFIGURATION $ RSVD_1: $ PCH USB2 port# 2 3 4 6

HIGH: 3.3V $ 4 ẩ %

RED FROM THE Eco IORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Deciphered Date 2020/04/12 Tile

ICL-U(1/14) DDL EDP

CUSTODY OF THE COMPETENT DIVISION OF R&D ‘| Sze | Document Number Rev

IT CONTAINS FH5LI M/B LA-H801P &

Date: Tuesday, October 15, 2019 [Sheet 6 of 102

E

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w eeu pec CATERR# cử CATERRY PROC TCK Pa $00_KDP Tot _XDP RC13 1 OMG@ 2 51 0402 5%

H_PROCHOT# 1 2 er _ T—- Ca | PEC! PROC_TDI [Kg SOC_XDP_TDO SOG_XDP_TDI RO14 1 OMOQ@ 2 51 0402 5%

499_0402_1%| CC1 EMC@ PROC POPIRCOMP_ CJ41 THRMTRIP# PROC TRST# PROO TMS [N1 SOC_XDP_THSTH SOC_XDP_TDO RGiS 1 OMO@ 2 51 0402 5%

+8VALW_PRIM 2 Aid | PCH OPIRCOMP „„¿ | PCH_TRST# Re PƠI JTAG TCKT

*b14-| RSVD 25 PCH TOK [Ki SOC XDP TDI

>——| RSVD 26 Bói Tdọ | KP SOC_XDP_TDO CMG@

7 XDP_ITP_PMODE DLI | SOC_XDP_TMS SOC_XDP_TCKO 1 %

100K_0402_5% <58» EO SLP S0DŒ EC_SLP_SOIx# 0 0402 5% 2 TRC3901 EC_SCH_ADTI Pvt | GPP_ESICPU_GPO a 2 _ P6 XDP_PRDY#

DC10 <58>_ EC_SCl# 00402 5% 2 TRC3963 # cRag_| GPP_E7/CPU_GP1 PROC PRDY# Mỹ —xDF rmemw—>®@''G I49;

<17> VOGIN AUX GORE ALERT# R[_— > 4 SOG GPP E6 pri | om es

- - 7 D a PCH_JTAG_TCK1 1 2 % SOSo0000200 = T3] GPP H2/CNV BT l2S SDO =——== HG22_ Í VỆ, S1 0402 5%

»PL3$ Í Gpp H19/TIME SYNOO yo 19 +8VALW_PRIM ICL-U_BGA1526

Issued Date 201 9/04/1 2 Deciphered Date 2020/04/1 2 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Tg; a TNumb AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ze ocument Number DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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DDR_A DO G DU OANH ANH PDRA|

— nae Q0_0/DDR0_DQ0_0 DDRA_GLK_N/D! CLK_N_o n- DDR_A_CLK#0 <23> <24> DDR_B_DO.15] <> pA BDO AK48 LPA(NIL) / DDRA(NIL) LPaqnit) /DDRAINIL) Y48

CA D0RA-DG0 1/0DE0-DG0- 1 DDRA_GLK _ >/ODS- GLK_P_0 FBF4Z DDR_ACLKO <23> DDR_E_DT AK45 _DQ0_0/DDR1_DQ0_0 DDRG_CLK_N/DDR1_GLK_N_9 [-ya7 DDR_B_CLK#O <24>

W: DDRB_GLK_N/DDRO_CLK_N_1 grag DDR A CLK#I <23> DU EU K48 | DDRC_DQ0_1/DDR1_DG0_1 DDRG_GLK_P/DDR1_GLK_P_0 [28 rE DDR_B_CLKO <24>

A DDRB_GLK_P/DDRO_GLK_P_1 DDR_A GLKI <23> DDHE AG47 | DDRG_DQ0_2/DDR1_DQ0_2 DDRD_GLK_N/DDR1_GLK_N_1 [M22 P@ T3

W: BG49 DƯH_E-D7 AKá7 | DDRG_DGQ0_3/DDR1_DQ0_3 DDRD_GLK_P/DDR1_GLK P_ 1 ——————— _-^-ẻ "+2

DDRA ‹ CKEOIODRO GKE0 FB7 II _—_mđhnA&Eo <23> ————— | DDRG_DG0_4/DDR1_DQ0_4 U45

Vy !A_GKE1/NG [BES DDH”E DE AGa8_] DDRG_DG0_5/DDR1_DG0_5 DORG_SKEO/DDRT_OKEO [vas 1 > DDR_B_CKEO <24>

G RB_GCKE0/NC | EES CORBA Gag] DDRC_DQ0_6/DDR1_DQ0_6 BG _CKEW/NG Fagg [wares

DDRB_OKEI/DDRO OKEi F————L >D0RA(ŒKEI <23> "FT AIã8-| DDRG_DG0_7/DDR1_DG0_7 D_CKEOING |-pqgX DDR B CKE1

BM38 "—DDHE DỨ TT ——AL38 | DDRG_DG1_0/DDR1_DG1_0 DDED ( GKEL/0DR1 _@KE1F——————————— #8 15+

DDRA ( os Ong GS#0 DDH A GS#0 <23> "—rrmrn TT Ais DDRG_DG1_1/DDR1_DG1_1 V42

lA_GS_1/NG [Bpa: FET A43 | DDRC_DQ1_2/DDR1_DQ1_2 DDRG ( os 021 _0S#0 [vss > DDR_B_CS#0 <24»

B_C©S_0/NG B62 TH BE DT ALS8 | DDRG_DG1_3/DDR1_DG1_3 BG _CS_1/NC FyggX [=

DDRB ( os T/DDRo- _GS#tF TL >DRA(C8#L <23> DDn ETT Aja] DDRC_DQ1_4/DDR1_DQ1_4 D_GS_0/NG | ag< DDR B CS#1

BM43 DOR-B-DT4 AL DDRG_DQ1_5/DDR1_DQ1_5 DDRD ‹ cá choos _cs¢4.,_-—— re +1498 DDRB_CA4/DDRO_BAO Pses¢—— DDR_ABAO <23> Trn T5 N27 DDRG_DG1.8/0DR1_DG1.8 T38

G/DDR0_BA1 DDR_A BÀI <23> <@4> DDR_B_D[16 31] < —>——— DUH HE DTE AB DDRG_DQ1_7/DDR1_DQ1_7 DDRD_GA4/DDR1_BAO az FS DDR_B_BAO <24>

BB49 DƯ TT AE: DDRG_DGQ2_0/DDR1_DG2_0 iC/ODR1_BA1 DDR_B_BA1 <24>

DDRA_GA5/DDR0_BG0 [80——————TD 3 DDH A BG0 <23> DDH-E UTE E28 | DDRG_DG2_1/DDR1_DG2_1 R45 (G/DDR0_BG1 DDRABGI <23> DURE DTS AE: DDRG_DGQ2_2/DDR1_DG2_2 DDRG_GA5/DDR1_BG0 [Mð——T[T> DDR_B_BGO <24>

BB48 DORE T770 XE DDRG_DGQ2_3/DDR1_DG2_3 NC/DDR1_BG1 [ez FS BeBe <24>

NG/DDRO_MAO grag DDR A MA0 <23> DDH_PD2T AB: DDRG_DGQ2_4/DDR1_DG2_4 P42 NG/DDR0_MA1 FB88&8 sss DDH_A MAI <23> DORE RE: DDRG_DQ2_5/DDR1_DQ2_5 NG/DDR1_MA0 [V28 DDRB ( CAB/ODRO | MA? FBE4SE SSS DDH_A MA2 <23> DDHE D7: AE: DDRG_DQ2_6/DDR1_DQ2_6 NG/DDR1_MA1 gag NG/DDR0_MA3 [BJa8 DDR_A MA3 <23> `" TDDHE.DZT———— AD38 | DDRG_DG2_7/DDR1_DQ2_7 DDRD ‹ Gas/DDR _MA2 vag _DQ3_—- | DQ3_ NG/DDRO_MA4 FBG: DDR A MA4 <23> "rrrrr T75 A038- DDRG_DG3_0/0DR1_DG3_0 DDR1_MA3

`"—DDH.A-D27DWä8 | DDRA_DG@3_2/DDR0_DG3_2 DDRA_GA0/DDR0_MA5 [BEäE DDR_ A MAB <23> ` TDR_E.D2E———AE39 | DDRG_DG3_1/DDR1_DG3_ 1 NGIDDAT-MAt R49

"—rrr^-nđy3á- DDRA_DG3_3/0DR0_DG3_3 DDRA_GA2/DDR0_MA8 FBEG2E DDR A MA6 <23> "rrrtrT77ra=4x- DDRG_DG3_2/0DR1_DGQ3_2 DDRG_GA0/DDR1_MA5 [H28 DOR

-ALD23 BWä39 | DDRA_DQ3_4/DDRO_DQ3_4 DDRA_GA4/DDR0_MA7 [FBG47 DDR A MA? <23> "—DDH HE DZB————AE38 | DDRG_DG3_3/DDR1_DG3_3 DDRG_GA2/DDR1_MA8 7

DDRA_GA3/DDR0_MA8 [FBEäZ DDR A MA8 <23> `"TmF_E.D28———ADá4ä3 | DDRG_DQ3_4/DDR1_DQ3_4 DDRG_GA4/DDR1_MA7 [ME DDRA_GA1/DDR0_MA9 FBHRBR DDH_A MA9 <23> DOE se D DDRG_DG3_5/DDR1_DG3_5 DDRG_GA3/DDR1_MA3 [E2 NG/DDR0_MA10 FBB4Z OT DDH_A MAI0 <23> DDH-B-U5T AE DDRG_DG3_8/DDR1_DG3_8 DDRG_GA1/DDR1_MA9 [Ƒpạ;

NG/DDR0_MA11 -BEq DDR_A MAIT <23> <24- DDRB_DI32.47] < —>——— DURE DDRG_DQ3_7/DDR1_DQ3_7 NG/DDR1_MA10 [Ni

NG/DDR0_MA12 ƑBM238 DDH_A MAI2 <23> DDE DDRD_DG0_0/DDR1_DG4_0 NG/DDR1_MA11 a

B_GA0/DDR0_MA13 [ƑBG4ã DDR_A MAIS <23> DDHE D22 DDRD_DQ0_1/DDR1_DG4_1 NG/DDR1_MA12 Fyq DORR TGAB/0DR0 ` MA14WE# DDR_AMAI4 = <23> DORE DSS DDRD_DQ0_2/DDR1_DG4_2 DDRD_GA0/DDR1_MA13 [V DDRB_GA1/DDR0_MA150AS# [BMáT DDR_A MAIS <23> DDHE D2E | DDRD_DQ0_3/DDR1_DG4_3 DDRD_GA2/DDR1_MA14WE# [vz DDRB_GA3/DDR0_MA16RAS# DDH_A MAI6 <23> TH EU 5] DDRD_DQO_4/DDR1_DQ4_4 DDRD_GA1/DDR1_MA15GAS# [V2

BJ39 DORE DS Z| DDRD_DQO_S/DDR1_DQ4_5 DDRD_CA3/DDR1_MA16RAS#

NG/DDR0_ODT_0 [88£—————D—T > DDH_A ODT0 <23» DUH-E U79 E48 | DDRD_DGQ0_8/DDR1_DG4_6 V43 NC/DDRO_ODT_1 DDR_ALODTI <23> "—rmrn nrư sir] DDRD_DGO_7/DDR1_DQ4_7 NG/DDR1_QDT_0 [Wgỹ—mowmdmm— Le: 2 Tế ey ODTO <24>

BY47 \—DORDB-D4T 39] DDRD_DQ1_0/DDR1_DQs_0 NG/DDR1_ODT_1 [wð——mrrvm—E = 6e DDRA_DGSN_0/DDR0_DGSN_0 FBý26 DDH_A DQS#0 <23> "rrrr Tag DDRD_DG1_1/DDR1_DG5_1 AH46

DDRA_DGSP_0/DDR0_DGSP_0 [FGGậT DDR A DQS0 <23> `"—DDH HE D43 42 | DDRD_DG1_2/DDR1_DG8_2 DDRG_DGSN_0/2DR1_DGSN_0 [H47 DDR_B_DQS#0

DDRA_DGSN_1/DDR0_DGSN_1 ƑEEaT DDR_A_DOS#1 <23> "TRE D1 dä9 | DDRD_DG1_3/DDR1_DGQ5_3 DDRG_DQSP_0/DDR1_DQSP_0 [ajay DDR

DDRA_DQSP_1/DDRO_DQSP_1 Ad DDR_A_DQS1 <23> —SOR EDs] DDRD_DQ1_4/DDR1_DQ5_4 DDRG_DQSN_1/DDR1_DQSN_1 Lat DDR

DDRA_DQSN_2/DDRO_DQSN_2 FBB26 DDH_A DQS#2 <23> "TRE -TDTE—— Gáä | DDRD_DG1_5/DDR1_DGQ5_5 DDRG_DQSP_1/DDR1_DGSP_1 [A27 DDR

DDRA_DQSP_2/DDRO_DQSP_2 FByaq7 DDR_A_DQS2 <23> "rrrr TTT-jTx- 0D0đD_DG1_6/0DR1_DG5_8 DDRG_DGSN_2/DDR1_DGSN_2 [ƑAG26 DDR:

DDRA_DQSN_3/DDRO_DQSN_8 [-gyyat DR_A_DQS#3 <23> <24> DDR_B_D/48 63] <= yas Bag] DDRD_DQ1_7/DDR1_DQ5_7 DDRG_DGSP_2/DDR1_DQSP_2 [E2] DDR DDRA_DQSP_3/DDRO_DQSP_3 Faya6 DDR_A_DQS3 <23> "TRE D18 543] DDRD_D@2_0/DDR1_DQ6_0 DDRG_DQSN_3/DDR1_DQSN_3 [-apaq DDR

DDRB_DQSN_0/DDRO_DQSN_4 4 DDH_A DQS#4 <23> "n0 AS] DDRD_DG2_1/DDR1_DQ6_1 DDRG_DQ@SP_3/DDR1_DQSP_3 FAT DDR

DDRB_DQSP_0/DDRO_DQSP_4 Fayaq DDR_A_DOQS4 <23> \—DDR-B-D5T G49] DDRD_D@2_2/DDR1_DQ6_2 DDRD_DQSN_0/DDR1_DQSN_4 [pag DDR

DDRB_DQSN_1/DDR0_DGSN_5 [BBTT DDH_A DQS#B <23> "rrrr T57 -ta2# DDRD_DG2_3/0DR1_DQ6_3 DDRD_DGSP_0/DDR1_DGSP_4 [gã] DDR_B.í

DDRB_DGSP_1/DDR0_DQSP_5 | N46 DDR A DQS5_ <23> "—DDH HE DBS pag] DDRD_DG2_4/DDR1_DG6_4 DDRD_DGSN_1/2DR1_DGSN 5 [đất DDR

DDRB_DQSN_2/DDRO_DQSN_6 N47 DR_A DQS#6 <23> "TRE D51 Báo | DDRD_DG2_5/DDR1_DQ6_5 DDRD_DGSP_1/DDR1_DGSP_5 [2ø DDR

DDRB_DQSP_2/DDRO_DQSP_6 FARaT DDR_A_DQS6 <23> "TH T95 Ad) DDRD_DG2_6/DDR1_DaQ6_6 DDRD_DQSN_2/DDR1_DQSN_6 [pq DDR

DDRB_DQSN_3/DDR0_DGSN_7 [ATa1 DDR A DQS#7 <23> "—DDH.E-DBSB———— B38 | DDRD_DG@2_7/DDR1_DQ8_7 DDRD_DGSP_2/DDR1_DGSP_8[ƑB8ạ—— TT DDR DDRB_DQSP_3/DDRO_DQSP_7 DDR_A_DQS7 <23> —SURSB-057 36] DDRD_DQ3_0/DDR1_DQ7_0 DDRD_DGSN_3/DDR1_DGSN_7 FE§g—————— DDR

BF39 "—DDHLE-DBB———ASB-| DDRD_DQ3_1/DDR1_DG7_1 DDRD_DQSP_3/DDR1_DQSP_7 [TT TT DDR B.(

NG/DDE0_PAR [BEag DDR_A PAN <28> ` TDDHE.DĐ———— 038 | DDRD_DG3_2/DDR1_DG7 2 P38 _DQ3 ‹ _DQ7 ‹ NG/DDR0_AGT# DDR_A AGI# <23> "—rmrrn TEƯ CC tan DDRD_DG3 3/DDR1_DG7 3 er DDR_B_PAR <24~

A AR42_| DDRB_DQ3_5/DDRO_DQ7_5 NC/DDRO_ALERT# DDR_A_ALERT# <23> "TRE TT 63g] DDRD_DQ3_4/DDR1_DQ7_4 NG/DDR1_AGT# = DDR_B_ACT# <24>

DORA" AT43 | DDRB_DG3_8/DDR0_DG@7_8 M38 1 "E157 b3g | DDRD_DG3_5/DDR1_DQ7 5 NC/DDR1_ALERT# DDR_B_ALERT# <24-

DDRB_DG3_7/DDR0_DG7_7 SVD_73 LGaa 2A _VAEFGA "—TDH-E-TDE TT A38 | DDRD_DGQ3_8/DDR1_DQ7 8 SM_RCOMPO 047 | oe RCome 0 pp Rovner CA B45 Ox0.6V-B_VREFCA GJrsace width/spacing >= 20mils ees 3019

AA VVV

25 +1-5%

DDRPGCTRL 2

RC28 100K_0402_5%

ccs

—100P_0402_50V8J EMC@

THs SHEET OF ENGINEERING DRAWING IS THÊ, PROPRIETARY PROPERTY OF COMPAL

Y NOT BE TỈ RED FROM MPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAIN!

Trang 9

e IGH: TL NFIDENTIALITY ENABLE se :

LOW: TLS CONFIDENTIALITY DISABLE ; LOW: ESPT ENABLE (Default i ;

UC1E SOGC SPI 0 CLK DB4z

S8 SOU SPL0 SO SOC SPL0 SỐ DF43 | SPI0_MOSI GPP_CO/SMBCLK |“ppaq SOC_SMBDATA

SPI ROM SOC SPIO 103 DD4rT | SPI0 IO2 SPI0 GPP_C2/SMBALERT#

SOC SPLO CSHO — DB4 Spin oan 4

uz 1 — DK24 SOC_SMLOCLK

SOC SPI 0 CS#2 A1 | SPIO_CS1# GPP_C3/SMLOCLK SOC SMLODATA

TPM<— <66> SOC SPIL0 CS#2 < | ——” B SPIO_CS2# SMLO GPP_C4/SMLODATA Bess SOG SMLOALERT#

GPP_C5/SMLOALERT# —— = GPP E11/SPI1_ CLK/BK1/SBK1 EC SMB CK2

GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_ C6/SML1CLK/SUSWARN_N/SUSPWRDNACK D22 EC SMETDAZ << EC SMB CK2 <58> SMLT GPP_E12/SPI1_MISO/BK2/SBK2 SPI 1 GPP_C7/SML1 DATA/SUSACK# ->—— =—— EC_SMB_DA2 <58> (Link to EC)

GPP_E1/SPI1_102

ESPI CLK 00 40

GPP_E8/SATALED#/SPI1_CS1# GPP_ A0/ESPI_IO0 FCON48 E SPT = Rca 2 SOM — ay, 02 19 ESPIIO0RR <58>

GPP_A1/ESPI_101 SPAR” xv⁄^ —_——- = ESPIIO1+R <58>

V19 eSPI — — CN47 ——— RC36 1 10 0402 1% 103,

Wi9 | CL_CLK MLINK GPP_A3/ESPI_IO3 [FETzs ESPLOSH OO Y® ESPIIO3SR <58>

Trg | CL_DATA GPP_A4/ESPI_CS# LẽR4o—ESPLHSTT—Ế = sẻ ESPLCS# <58>

g5VAT1 W *PđIM ° 99999 90909090606096000000000000000 00006666666 9e CL_RST# GPP_, AG6/ESPL_ RESET# — ESPI_RST# <58> ESPI

› SPIO_MOSI Reserved een Ti strap should sample HIGH There should NOT be

› 100K 0402 5% SOC_SPI_0_102 ° any on-board device driving it to opposite direction

° O ERNAL PU/PD ° External pull-up is required Recommend 100K if pulled "2a ^^ n2 mo

° e — RC38 2 1K 0402 5%

° ° Elsig edgx:6t up to 3.3V or 75K if pulled up to 1.8V 0 RG316 1 2 499 0402 1%

° aa NAB e SPIO_102 Reserved This st hould le HIGH Th hould NOT b BOC SM ˆ

ÊoÔĐÔÔĐĐ20Ô000000600600000600600000600600000000000o00o06eo6eoeeooooeees Ree shiv Ga Board device driving I 66 epposite direction” — LODATA i RG315 2 499 0402 1%

during strap sampling

s®@eeeeeeeeeoeeẨeẨeeoeeeẨeoeeeeeoeeeeeoeeeeoeoeoeedeoeeoeedeoeoeeeeoeoeeeoeeeeedee External pull-up is required Recommend 100K if pulled EC_SMB_CK2 RC381 2 1K 0402 5%

° ° Rising edae of | UP to 3.3V or 75K if pulled up to 1.8V RC382 1 AVAVA_-2_—1K 0402 52 |

„3VALW_ PRIM Ọ SPIO_1O3 Reserved EMRE This strap should sample HIGH, There should NOT be |

e any on-board device driving it to opposite direction

° RG39 1 „A2 100K 0402 5% „_ SOC SPL0 O3 ° Sone Sr ee ĐẾI

SOC_SPLO SO RC¿z 1 49.9 0402 1%SOC_SPIO0 SO_R

SOC SPIO CLK RE3 NOY 4990402 1% 500 SPIO CLK A

SOT_SPI_0_ol RC 1 IN 499 0402 1%SOC SPIO SIA

SOC SPI0 O2 —SPT_O_ RCE ; 1 V2 499 9402 0402 1%SOC SDI 0 I2 A

QC4A 2N7002KDW_SOT363-6

<— >SOC_SMBGLK_1 <23,66>

SOC_SMBDATA 6 = col SOC_SMBDATA_1 << >SOC_SMBDATA_1 <23,66>

E - Master MAF - Master Attached Flash

Attached Flash Sharing Single SPI Flash attached to SPI Bus

— EC FW access through eSPI Bus

oe GED Cee

+

8T

Issued Date 2019/04/12 Deciphered Date 2020/04/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE: PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Sĩ D = Numb R AND TRADE SECRET INFORMATION THIS SHEET MAY NOT RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Ize ocument Number ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS FH5LI M/B LA-H801P 1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

1

Trang 10

UC1G

HDA_BIT_CLK CY46 1

HDA SYNC Cvao | GPP R0/HDA_BGLIK/I260 SGLK GPP G1/SD DATAO

— A45 GPP_ R5/HDA_ SDI1/12S1_ SFRM GPP H1/SD PWR_ EN N/CNV BT Il2S SDO

mô | GPP_ R@6/12S1 TXD SD3 RCOMPE lo

Tae] GPP_R7/I281_RXD spa ROOMP 243 - B038E 1 2 200040211 — — ! 2 200 0402 1% »

NV RE RESET# Ta] GPP_A7/l2S2_SCLK

<52> CNV_RF_RESET# << chy er fies Tas-| GPP_Ag/I2S2_SFRMICNV_RF_RESET# DQ3

a GPP_A10/l2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLKO Lae

<52> CLKREQ_CNV# < GPP_A9/l2S2_TXD/MODEM_CLKREQ GPP_S7/SNDW4_DATA/DMIC_DATA0 F——<

< HD AUDIO > : RC449 1 XXX 2 33K 0402 5% HDA ASTA :

<56> HDA SYNC R a) RO48 1 A A, 2 33 0402 5% HDA_SYNG : Follow :

+ 572907 ICL_UY_ PDG for Glitch

<ð8> HDA_SDOUT_R <<} ROA7 1 AA, 2 33 0402 5% 4 HDA _SDOUT : — :

<58> ME_EN [> ROS1 1 AAA 2 0.0402 5% HDA_SDOUT

Issued Date 2019/04/12 Deciphered Date 2020/04/12 Title ICL U 4 12 HDA sD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Tg; a = N (4 ⁄ ) 2 E AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ze ocument Number ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS FHSLI M/B LA-H801P 1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Trang 11

1 2 % _CLKREQ_PCIE#4 L <68> CLK POIE F0 _] DK33 | CLKOUT_PCIE_P0 Tole ee OLKOUP POLE SPS 4 eeccccers 573123 RVP both side, o INDUTBVSEL 2 1

Ì FC E——v.Èx 10K 0402 5% <68> CLKREG_PCIE#O GPP_DS/SRCCLKREQo# PP HY /SRCETRREGe? Poe : but ORB snip sceeaveon ates) 2 a¥ SELECT STRAP INPUTSVSEL » —_RCA56 2 AR At AM 0402 :

VW GLAN <51> CLK_PCIE NI CLT] CLKOUT_PCIE_N1 DL48 SỌCG BTCX1 : RC457 100K_0402 :

reserve L <51> GLK PGIE S51> CLKREO, Pelee — 32 | cpp D6iSBCGLKREGi# GLKOUT_PGIE P1 arc | RTCX1 nroxe a9 = — BGðIL 1 2 0 0402 5% 3 \C_RTCX2 th RW eSeseecvases S11

WLAN L <52> CLIC PCIE Pep DE3z | CLKOUT PCIE P2 SRTCRST#

_ <52> = GPP_D7/SRCCLKREQ2#

573129_ICL_U_DDR4_SODIMM_HW_SCH_RN : ERE] CLKOUT_PCIE_N3 9573129 ICL_U DDR4 SODIMM HW SCH RN

+3VALW_PRIM : GPP_D8/SRCCLKREQ3# xa [— „„XTAL IN FDUR = = 438

: Si] CLKOUT_PCIE_N4

1 2 % PM_SLP_SO# CLKREGEPGIE®3 ° " " ENZO] CLHOUPPCIE® Pace ses DUG XCLK_BIASREF 1 2 60 % CPU_C10_GATE# 2 1 %

: RC3959 100K 0402 5% PM SLP_- : : GPP_H10/SRCELKREGiT XCLK_BIASREF - RC59 60.4 0402 1% _C10- RC3972 2 PREM@ 1 100K 0402 5%

j Ros99 TT VY 2 100K 0402 5% PM_SLP_LAN# : SOC_RTCX1

TW M3 100K 0402 5% PM_SLP_WLAN# + SLP_SUS# Duag GY42 PBTN_OUT#_R 1 2 % "1

1 RC400 1 AÝA A2 100K 0402 5% : TH eo sip susz GPD3/PWRBTNZ | peso nh tế PBTN_OUT# <58> 1 2

: PM_-SLP S47 TrC28-| GPD10/SLP_S5# GPD1/ACPRESENT 28 - = AC_PRESENT <58> Rose MN 040259

VW : : <15,78> PM_SLP_S3# <78> PM SLP_§4# < ————— == 27] GPDS/SLP S47 GPD4/SLP_S3# GPD0/BATLOW# TT

: PM_SLP_AF DH47 — CL39 PMGALERT#

+8VALW_PRIM <15,58,66> PM_SLP_SO# GPP_B12/SLP_So# P_H18/CPU_C10_GATE# Baqi CPU_C10_GATE# <15> : vc2 ;

- PM_SLP_WLAN# DE4! GPP_H3/SX_EXIT | HOLDOEE NCNV BT I2S SDO | 22% : toe :

EC_RSMRST# DG49 DE47 LAN_WAKE#

+RTCVCG <58> EC RSMRST# >SV5 HEBETE——— DBKi9 | RSMRST#Z GPD2/LAN_WAKE# [Ba : co oF 00GRWOO co :

ọ ¬ ag-| SYS_RESET# GPD11/LANPHYPC/DSWLDO_ MON FEE : oo cee Fase SOC ASEP oo ees : tk 1 :

<66> PLT_NST# [———— —] GPP_B13/PLTRST# CE4 VCOST OVERRIDE RG3Ê81 2 0 0402 5% VCCST OVERBRIDER + : — =- 9 : RC56 1 2 _20K 0402 5% SOC_SRTCRST# VCCST_OVERRIDE [EẸa——EC VCEST PG : ° : 89 82 ;

PCH_DPWROK DBái DSW_PWROK V€GSTPWEGOOD ) TCSS VCCST PWRGD | CE5 T TEULPWEGU RG4831 2 0.0402 5% : : : soncopodde 21 Ÿ _ 24 :

GG13 1 1U 0201 6.3V6M <58,78> PCH_PWROK — DN47 7 PCH PWROK ROCPWRGD [CFI CFi F_PROCPWRGD | gregh arabia ccccesaesscvcccccccccccsscscccccsece® Ss Ss

<58,78> SYS_PWROK = SYS_PWROK DC47 GPD7 Only For Power Sequence Debug œ œ

INPUT3VSEL DNA! GPD7 >®@1r@ T50: PWT modify

: RG377 1 ABA 2 1M_0402 5% SM_INTRUDER# SM_INTRUDER# 48VALW_PRIM

: @_ CC319 1 || 2 0.1U 0201 10V6K itis SốT-XoLZ3CE tCPU22/ t?CH28b 100K 0402 5%

| nnnnnnnnnnnnnnninninnnnnninninnminn- EC_VCCST_PG R RCT? 4 2 60.4 0402 1% EC_VCCST_PG bene

| EMC@ cc20 2 || 1 100P_0402 50va) _SYS_RESET# ! <5#,78> EC_vocsT_pG_R [>

Vv l=Ẩ==c==c=eee==k=al SOC XIAL384 OUI § RCð5 1 RMQG@ 2 0 0402 59 SOC_XTAL38.4_OUT_R

ESD tee ew (nụ cnn cm" an cnn mm nụ cnn mm nu

— R345 1 20 0402 5% EMI want to change 33 ohm, but ORB &CRB is 0ohm

<58> EC_VCCST_EN 2° 0" 6468 Bie From EC to VCCST

ˆ ˆ PM_SLP_S3#"*** — ‡83Š° 1° ^@* ° * 9 %ý 9283 kÀ0 tân = 623 l3 SINR Power SW Enable 3 5 VCCST_OVERRIDE_LS — — D H D L PCH PLTRST Buffer

PM_SLP_S4# R343 1 @ 2 0 0402 5% g RC63 1 2 —_— 0 0402 5%

i PM SLP_93# (SUSP#) D D H L

+3VS EC_VCCST_EN Output H H H L cc19 @

1 2 +8VALW

Issued Date | 2019/04/12 Deciphered Date | 2020/04/12 Title 5

THIS SHEET OF ENGINEERING DRAWING IS THE TY NÓT BE PROPERTY or ara EU rO0y Q đi ANC AND CONTAINS CONFIDENTIAL SI Do 1CL-U/ /12)CLK, GPIO Re

AND TRADE SECRET INFORMATION THIS SHEET M E TRANSFERED E COMPETENT DIVISION OF R&D 2 cum um v

DEPARTMENT EXCEPT AS AUTHORIZED BY GOMPAL E ELEGTHONIOS: ING NEITHER This SHEET NOR THE INFORMATION IT CONTAINS FHSLI M/B LA-H801P MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Date: Wednesday, October 30, 2019 [Sheet 11 of 102

1

Trang 12

PC TECL

GPP_B20/GSPI1_CLK GPP_B22/GSPI1_MOSI GPP_B21/GSPI1_MISO

<63> I2C 1 SDA B28 | GPP_C18/I2C1_SDA

Touch Pad E <63> I2G 1 SGL —— GPP_C19/I2C1_SŒL UART_2 CRXD_DTXD

bur] GPP_H4/I2C2_SDA '

GPP_H5/I2CZ_SCL wat

ora] GPP_H6/l2C3_SDA GPP_H7/I2C3_SCL

ower GPP_H8/I2C4_SDA/CNV_MFUART2_RXD GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

GSPI

6 of 19

«| NODX76@ „| NODX76@ „| NODX76@ „Ì NODX76@

RAM_ID0 | FAM.TDZ

FAM TDZ

RG155 RG225 RC226 10K_0402_5% 10K_0402_5% 10K_0402_5%

@ @ @

RG227 10K_0402_5%

@

RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_IDO PartNumber - Description Hynix 4GB 0 0 0 0 SA0000BMIN30 (S IC D4 512M16 H5SAN8G6NCJR-VKC FBGA ABOI) Micron 4GB 0 0 0 1 SA0000ARD60 (S IC D4 8G/2666 MT40A512M16LY-075:E ABO!) Samsung 4GB 0 0 1 0 SA0000B6F30 (S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P)

DV33 PROJECT_IDO GPP_D13/ISH_UART0_RXD | Dwyag

GPP_Di8I8SH UART0 CT8 NCNV WCENE “———————

PCH_SPKR | SOC_GPP_D16_ INTERNAL PD 20K

eboot Enable {Default

rT] 5 3 wp “| 5 3 wz rÌ 5 3 mm rTÌ sy 8 QGPP_D16 Strap refer RVP see

ee sẽ sẽ os TOP SWAP OVERRIDE

al #8 a| #9 al © al 'y

bà

GPP_D16 MFR_MODE_DET_STRAP

Issued Date | 2019/04/12 Deciphered Date 2020/04/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE TY NÓT BE PROPERTY or ara EU rO0y Q đi ANC AND CONTAINS CONFIDENTIAL Siz ICL-U(6/12)GPIO Rev AND TRADE SEGRET INFORMATION THIS SHEET M: E TRANSFERED IE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY GOMPAL E ELEGTHONIOS: ING NEITHER This SHEET NOR THE INFORMATION IT CONTAINS FHSLI M/B LA-H801P MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Date: Tuesday, October 15,2019 [Sheet 12 of 102

I 2 I

Trang 13

Rev 1.0

of 102

PP | PCIE7_RXP PCIE1_RXP/USB31_1_RXP 5 USB3 CRX DIX P1 <72>

*BBš | PCIE7 TXN PCIEi TXN/USB31 1 TXN [BỊï U§B3 GTX DRX N1 <72> USB3 MB (Front&Charging)

—— PCIE7_TXP PCIE1_TXP/USB31_1_TXP USB3 CTX DhX P1 <72>

<a PCIES_RXN PCIE2_RXN/USB31_2 RXN pes

BAS | PCIE8_RXP PCIE2_RXP/USB31_2 RXP F3 BAS | PCIE8_TXN PCIE2 TXN/USB31_2 TXN 5<

>———] PCIE8 TXP PCIE2_TXP/USB31_2_TXP ->——<

<51> PCIE_CRX_DTX_N9 oe See] PCIES_RXN mẹ PCIE3 RXN/USB31 3 RXN LDEg USBS ORX DTX M3 c71>

<51> POIE CRX DIX P9 = T TT POIE9 RXP POIE3 RXP/USB31 3 RXP E — — — <fl>

<51> PCIE_CTX_C_DRX_P9 5 — — — PCIE9_TXP PCIE3 TXP/USB31_ 3 TXP USB3 CTX DRX P3 <71>

PCIE_CRX_DTX_N10

<52> PCIE_CRX_DTX_N10 FCTE-CRX-DTX PT0—-GMệ | PGIE10_ BxN Pele FSB PCIE4 RXN/USB31 4 RXN [BC

<52> POIE CRX DTX P10 1U 0402 16V7K PCIE CTX DRX N10 CY3 PCIE10 RXP PCIE4_RXP/USB31_4 RXP [IPEE

WLAN <52> PCIE CTX © DRX N10 “TỦ 0402 16V7K_ PCIE CTX DRX PT0 Gye] PCIE10_TXN PCIE4 TXN/USB31 4 TXN [B1

<52> PCIE_CTX_C_DRX_P10 5 — — — PCIE10 TXP —” PGIE4 TXP/USB31 4 TXP Ƒ————<

<67> SATA CRX DTX N0 oN PCIE11_RXN/SATAO_RXN PCIE5_RXN/USB31_5 RXN Lae

HDD <67> SATA_CRX_DTX_PO OW2 | PCIE11 RXP/SATA0 RXP PCIE5 RXP/USB31 5 RXP [E4 <

<67> SATA CTX DRX N0 CW PCIE11_TXN/SATAO_TXN PCIE5_TXN/USB31_5 TXN [BE3<

<67> SATA CTX DRX P0 CJ POIE11_TXP/SATA0_ TXP PCIE5_TXP/USB31_5 TXP ->——<

CJ7 PCIE6_RXN/USB31_6 RXN eye * ODD <67> SATA_CRX_DTX_P1 > CW5 PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6 RXP -ppT

<67> SATA_CTX_DRX_N1 PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN -pp2<

CW3 —— PCIE6 TXP/USB31 6 TXP Ƒ———*

L— <6] SATA GIX DAK Pt, CG7 PCIE12_TXP/SATA1A_TXP

DN8 USB20 Ni 72 [— <68> — | | PCIE13_RXN [ USB2N 1 BỊ </2>

<68> PCIE_CTX_DRX_N13 CTE | PCIE13_TXN DK1

<68> PCIE_CTX_DRX_P13 PCIE13_TXP USB2N_2 HN

CE6 PCle USB2P_2 <

<68> POIE CRX DTX N14 CE7 | PGIE14 RXN DP13

<68> POIE CRX DTX P14 CTe | POIE14 RXP USB2N_3 | BN13 USB20 N3 <71> ¬

ssp <68> PCIE_CTX_DRX_P14 PCIE14_TXP DK10

USB2N_ 4 USB20 N4 <73>

<68> PCIE_CRX_DTX_P15 CR3 PCIE15_RXP/SATA1B_RXP DL5

<68> PCIE_CTX_DRX_N15 GRa | PCIE15_TXN/SATA1B_TXN USB2N_5 Pps SS USB20 N5 <66> ¬

<68> PCIE CTX DRX P15 PCIE15 TXP/SATA1B TXP sce /sara USB2P_5 USB20 P5 <66> FP

sara} ssp | X88> POIE CHX DIX H16 Sp] PCIEI6_RXP/SATA2_RXP Uss2o USB2P_6 USB20 P6 <38> TS

| | <68> PCIE GTX DRX P18 RC402 @ PCIE16 TXP/SATA2_TXP USB2N_7 B13 USB20 N7 <38> ¬

USB_OCO# —— CTaa | GPP_E9/USB_OC0# USB2N 9 [DL£<

— GPP_A16/USB_OC3# USB2P_9 F———<

tự GPP_E4/DEVSLPO USB2N_10 ONG USB20 N10 <52> ¬ a8] GPP_E5/DEVSLP1 —— USB2P 10 USB20 P10 <B2> BT

RG401 1 210K 0402 5% USB OC0f was | GPP_H12/M2_SkT2 CFGO F——— DLii USB2_VBUSSENSE RC354_1 Th Oe 210K 0402 5% rom 1

T RC403 T1 2 10K 0402 5% USB OC37 V38 GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE

check list needs stuff even un-use | RG100 1 VY 2 100 0402 1% —SCTE-ACOMPE— PCIE.RCOMPN DNI DNa-] PCIE_RCOMPN _ x RSVD_81 S CD3 _ UFS_RESETZ = 1 >+@TP@ T328 `Ñ⁄

— PCIE_RCOMPP

8 of 19 From ACER HSIO

Please reference PCH EDS Tabel 1-2 @

Table 1-2 PCH HSIO Details

SKU

Flex 1/0 Lane / Table 6-24 SATA / PCI Express* Gen 2 and Gen 3 Capacitor Values

Premium U Premium Y Base U Condition PCI Express* PCI Express* SATA Only PCI Express* PCI Express*

NO AC capacitor is required for motherboard Rx channel This option DOES NOT support DC coupled

3 USB3.1 Gen1/Gen2, USB3.1 Gen1/Gen2, PCle* USB3.1 Gen1 ODDs / Devices

PCle* 3 For PCle* Gen 3/ SATA multiplexed configuration, motherboard Tx requires a 220 nF AC capacitor and

NO AC capacitor is required for motherboard Rx channel This option DOES NOT support DC coupled

4 USB3.1 Gen1/Gen2, USB3.1 Gen1/Gen2, PCle* PCle* ODDs / Devices

PCIe* 4, Design Constraint: For PCle* lane that needs to support either PCIe* Gen2 devices or PCIe* Gen3

devices, follow the PCle* Gen 3/5, TA multiplexed configuration, motherboard Tx requires a 220 nF AC

5 USB3.1 Gen1/Gen2, USB3.1 Gen1/Gen2, PCle* PCle* peace and NO AC capacitor is required for motherboard Rx channel This option DOES NOT support PCle* coupled ODDs / Devices

6 PCle*, GbE PCle*, GbE PCle*, GbE

7 PCle*, GbE PCle*, GbE PCle*, GbE

8 PCIe*, GbE PCIe*, GbE PCIe*, GbE

9 PCIe* PCle* PCle*

10 PCle*, SATA PCle*, SATA PCle*, SATA

11 PCle*, SATA PCle*, SATA PCle*, SATA

12 PCIe*, GbE PCIe*, GbE PCle*, GbE Security Classification Compal Secret Data Compal Electronics, Inc

14 PCIe*, SATA NA PCIe* -

: : THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Tg; ICL U(7/12)PCIE, USB,SA TA

15 PCIe*, SATA NA PCle* AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ze ocument Number

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS FHSLI M/B LA-H801P MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

ate: uesday, October 15, 2019 eet 13

D Tuesday, Ociob [Shi

Trang 14

Follow check list reserve +1.8VALW_PRIM

<Bra-] CSI E CLK P GPP_F9/EMMC DATA1

<a] CSI E DN 0 GPP F10/EMMC_DATA2

*“Gi4-| GSI E DP 0 GPP F11/EMMC_DATA3 Fz] GSI E DN † GPP F12/EMMC _DATA4

~<— “| csi E DP 1 GPP F13/EMMC_DATA5

0 enc GPP F14/EMMC_DATA6

*Tig-| 0SIF GLK_N GPP_F15/EMMC_DATA7

*—[§-| GSI F GLK_P GPP_F7/EMMC_CMD

<a] CSI_F_DN_0 GPP F16/EMMC_RCLK

*“MiT-| CSI F DP 0 GPP_F17/EMMC_CLK SGT] CSLE_DN_1 1.8V_ | cpe_Fiaemmc_RESET# EMMC RCOMP

>—g§-| GSI D DN 3/GSI G GLK N ose CNV_WR_DON N44 CNV GRX DTX N0 <52>

>~—””| GsI D DP 3/CSI € GLK P CNV_WR_DOP BG4z CNV GRX DTX P0 <52>

>—§§-| GSI H DP 2/GSI G DP 0 GPP_F2/CNV_RGI_DT/UART0_TXD [B[ãi—JGNV-BETCTX TT CNV_AGLGTX DRX <52>

Te] GSI H DN 3/GSI G GLK_N GPP_F0/CNV_BRI_DT/UART0_RTS# BNZg8—CNV-HGTCRX DTX CNV_BRILCTX_DRX <52>

>——~| GSI H DP 3/CSI G GLK P GPP F3/CNV RGI RSP/UART0 CTS# ———— CNV_RGLCRX_DTX <52>

B4 | csi_RCOMP GPP_F4/CNV_RF_RESET# eee $500 GPP Fe

GPP_F@/CNV_PA BLANKING [prs Igoc app ri GPP_D4/IMGCLKOUTO GPP F19/A4WP_PRESENT [BKog —SOC GPP TE 1 GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ | >9 TPo †;„¡

@

Follow 572907_ICL_UY_PDG

PC glitch free,it is recommended that a

pull-down resistor of 75K ohm on GPP_F4(CNV_RF_RESET#)

IORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

E TRANSFERED CUSTODY OF TH MPETENT DIVISION OF R&D

I

IT CONTAINS

Trang 15

: For Power consumption BB UG11 0 0603 5% Ọ ACT2 VCCINT VCCIN_52 -eietg

Ọ Measurement PREM@ |, > — 1 — ° Viä | VCOIN 2 VCGIN 53 ƑJ3Z

: 2 Úp >| VIN1 +1.2V_VGCPLL_OG : W12 | VCCIN 3 VCOIN 54 [ G34

: PREM@ +5VALW s VIN2 JUMP@_JPCS ; Yï3 | VCEIN 4 VCOIN_55 | G35

: 0 1U 0201 10V6K VIN thermal VOUT : 31] VCCIN_6 VCCIN_57 F Gnas

: 2 |[ 1 VBIAS JUMP_43X79 1 Imax : 0.182 A : 18 | ORIN VGGIN so | CP23

; CC308 : 4 23 | VERN VGCIN ao | C34

: 0_0402_5% 1.2 2 : ị BNT0 | VOCIN 1Í VCOIN_ê2 [ẾT33

: QI EMS201V_DFN8_3X3 : BPii_| VOCIN 12 VCCIN 63 [C734

: as —DENS_ : VCCIN_13 VCCIN_64 ers

: & I (Max) : 0.152 A(+1.2V VCCPLL OC) : VCCIN 16 VCCIN 67

: v drop 0.0005V : Bua] VCCIN_18 VCCIN_69 F554

: : BỰ8 | VOCIN_20 VGGIN_71 | AA1Z

: For Power consumption +» UC12 RC407 ° C23 VCCIN VCOIN- F2/

Measurement PREM@ |, ~~ 1 0 0603 5% : A23 | VCOIN 27 COIN_z8 [ F28

Ọ 2 2] VIN1 +1.8V_PRIM_SOC H C27 | VCCIN 28 VCCIN 79 Ƒ@

: PREM@ +5VALW ầ VIN2 JUMP@_JPC5 “ 3 § C29 | VCCIN 29 VCCIN_80 Gig

: CG107 z 7 6 +1.8V_PRIM_SOC_P 1 2 : CA36 | VCCIN_30 VCOIN_81 [G23

: 0 1U 0201 10V6K VIN thermal VOUT : Ag | VCOIN 31 VCOCIN_82 ay

: 2 |J[ 1 — 3 JUMP_43X79 Imax : 0.7 A : CB16 | VCCIN_32 VCCIN_83 [Ƒ@Z7

: CPU_C10_GATE# 1 PERO 2 OPU C10 GATERR 4 | en LS 0.1U_ 0201 10V6K : C38 | VCCIN 34 VOCIN-88 | T9

: ACN6 : CC6 | VCCIN ` | 8ô [ F23

0 0402_5% z 2 : CBi0] VCCIN 38 VGGIN 87 Fay

° a ° CE34 — — J20

: 2 lo : CEäm—] VCGIN 40 VGGIN 91 T55

: & < H Eia-| 1 VCCIN 41 — VCGIN 92 JS———‡ — 2

: Š I (Max) : 0.7 A(+1.8V_PRIM SOC) +8VALW PBIM : S T8 | VECIN a2 VOCIN- 92 Je

H RDS(Typ) : 3.5 mohm Q7 : ỐGi1 | VCCIN 43 VCGIN 94 F]sg ——}

: v drop 0.0024V : €G34-| VCGIN 44 VGGIN 95 FJ5g——‡

: Ì CGag : Ghế] VCCIN 46 VCCIN 97 [+8

: SUSP# RG1321 RRKM@2_0 0402 5% PREM@ : CHT] VOCIN 48 VCCIN_99 [2ã

: @ 5 4 VCCSTG EN L§ VGOSTG ÊN LS <16> 126118 VGOIN 1 ba [us

: 11> CPU G10 GATE# CPU_C10_GATE# 0 0402 5% PREM@ : ss ro VIDSOUT VSSIN_SENSE VSS_SENSE_VCCIN <88>

<88> OPU §VID ALERT#R <——] 0.0402 5% 2 A\ [H363 CPU SVID ALEHTf

<88> CPU §VID OLKR <<—] 0.0402 5% 2 A\ LHC364 CPU SVID CLK -

DEPARTMENT EXCEPT AS AUTH

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT B RED FROM THE Eco

IORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

E TRANSFERED CUSTODY OF TH MPETENT DIVISION OF R&D

I

IT CONTAINS

ICL-U(9/13)Power, SVID

Size | Document Number Rev

Trang 16

+1.2V_VDDQ

° UG1M

AG36 | VDDG_1 7 ALS8 | VDDQ_3

VDDQ_4 ANgữ-| VDDG 5 ARäE | VDDQ_7 ATS6 | VDDQ_9

BB36 | VDDQ_17 BDä6 | VDDQ_18

19

† —— B36 | DDQ 20

VDDQ_21 BE37 s ABBB | VDDQ_22 BEzg | VDDQ_23 Base | VDDQ_24

Bae | VDDQ_25

VDDQ_26 ie] VODa 27 BNg7 | VDDQ_28 VDDQ_ 30

VDDQ_31 VDDQ_ 32 VDDQ_ 34 VDDQ_36 VDDQ_38 VDDQ_ 40 VDDQ_41 VDDQ_42 VDDQ_44 VDDQ_46 RSVD_78 RSVD_2 VCC1P8A_1 VCC1P8A_2 VCC1P8A_ 4 VCC1P8A_5

VCCSTG_OUT 3 VCCSTG_OUT 4 VCCSTG_OUT_5

6 VCCSTG_OUT_7

cet VCCST Bvt VCCSTG

F33

+1.05VS_VGGSTG_OUT_LQG ƒ

VCCST

CC315 = 7

0.1U_0201_10V6K VIN thermal

2 1 VBIAS

VCCST_EN_LS_R 11> VCCST_EN_LS > 1 Xà _EN_L8_! 4) on

0_0402_5% =

VSo9

833 See saoo00sr600

6 +1.05V_VCCST_SINGLE 1 2 VOUT

GND 5 EM5201V_DFN8_3X3

0.455 A(+1.05V_VCCST)

3.5 mohm 0.0016V

+1.05V_VCCST_DUAL +1.05V_VCGST_P

GPAD

JW7110DFNC_ DFN14_2X3 SA0000BEL00

6 9

1 84 vine vourz LŠ 1000P_0402_50V7K +18VALW_PRM- @——L——— ins VOUT2

15

1.8VS_R % ] + _ RC136_1 A A, 2 0.0402 5%

1'38 +s aN Bs TT S8 s8 Sẽ 38

se a re mS mS oh eo oe

aN 23 5® 's@ ti ln ae 6S [Nese T49 J 2£ 3® 5 = 5 = 2 g 2 $ s$@ 2 5 = s =

cb2

+1.2V_VCCPLL_OC CG38

2

+1.2V_VDDQ TO +1.2V_VCCPLL_OC

Imax : 0.152 A

10uF* 2

+1.2V_VDDQ +1.2V_VDDQ

ọ

= = = = = = = = =

=8 _| =8 ot =8 fo) =8 3 =8 lại sy sơ >8 Sœ | Sơ | Sœ | Sẽ SR Sk Se Sel Sel Sel Sứ, 8 Sie Se 8k s.— s— Sử ER ER 7 © IP SSS 7 ASS FP SS OS | A OS | OS EN

Issued Date | Deciphered Date 2020/04/12 Title

Trang 17

+8VALW +3VALW_PRIM

JPC7 JUMP_43X39

@ +3VALW +8VALW_DSW

-Z02_6A_20%

RC248 heeds stuf£ 100 ohm when stuff LC15

RG248 0_0402_5% GC298

1U_0201_6.3V6M

@

—SÖ

GC246 22U_0603_6.3V6

26000 mA

SD028000080

AH a 1 30F3 DF23 % +3 VAL W ĐÁ VCGIN_AUX 1 PU POWER 3 OF VCCPRIM_3P3_2 bon R 0_0402_5%

VT] VCCIN_AUX 2 VCCPRIM_3P3_3 pase Qt rr ee nee eee

BAT HÀ * +1 BVALW_

eS JT] VCCIN_AUX_11 VCCPRIM_1P8_6 ' 01U 020110V@K 0

2 CNT0 | VCGIN_AUX_12 VCCPRIM_1P8_7 @RFe Ð '

ÉPTT-| VCCIN_AUX_13 VCCPRIM_1P8_8 BESđ—Ä 1 ẾRi0 | VCGIN_AUX_14 VCCPRIM 1P8_9 1 1

ẾUT0 | VCGIN_AUX_16 = VCCIN AUX 17 +085VO_VCCLDOSTD 1 TU CƠ CƠ CƠ CƠ: me a os ee tHn cHn cm cm tp na na GnÝ

CVT VCCIN_AUX_18 - 65 mA RF request

T0 | VCCIN_AUX_19 +1 øv_ vcfx HÀ, DO CY1T | VCCIN_AUX_20 ẾT | VCCIN_AUX_21 +1.24VO_VCCDPHY

ai "H va AT8 | VCGIN_AUX_33 BOs

+1.8VALW_PRIM š š AU10 | VCCIN_AUX_34 VCCPRIM 1P05_1

7 owl AV8 | VCCIN_AUX_35 DG29

VCC_VNNEXT_1P05 See]

[ VCCPGPPR VCCPRIM_3P3_1 a AUX_CORE_VIDO %

DD35 GPP_B0/CORE_VID0 [EJBÐ—VƯCN RUX-COFRE-VDT—— kết T pee VCGIN_AUX_CORE_VIDO_R <1/91>

VCCPRIM_1P8_1 GPP_B1/CORE_VID1 -enge ROOTS 50 40D EE VCCIN_AUX_CORE_VID1_R _ <11/88/91>

CET GPP_B2/VRALERT# = = = VCCIN_AUX_CORE_ALERT#.R <7>

near DG26 2 $ *CHGRTC GHNE02UPT SG703 CC84 0.1U_0201_10V@K - [ 1U 0201 6.3VôM G0143 4] GND GND

near DF23 near DG20 — 2 ACES_50271-0020N-001

#575412 WHL_U_PDG_RO.7 table11-11 7 table11- CONN@

Close to BR23 SP02000RO00

Issued Date | 2019/04/12 Deciphered Date 2020/04/12 Title

AND TRADE SECRET INFORMATION THIS SHEET M: E TRANSFERED

THIS SHEET OF ENGINEERING DRAWING IS THE TY NÓT BE PROPERTY or ara EU rO0y Q đi ANC AND CONTAINS CONFIDENTIAL, Size | Document Number

IE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY GOMPALE ELECTRONICS ING NEITHER: THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN GONSENT OF COMPAL ELECTRONICS, INC

Trang 18

U€19 UGIP UC1Q GND 1OF 3 GND2 OF 3 DJ33 GND 3 OF F1l Ait AF45 BT3 CR37 pias] VSs 207° °Vss_ 362 p33 A48 | VSS 1 VSS 75 [AE4Ƒ BT33 | VSS 149 VSS 223 [€Rxs Bj4Z | VSS 298 VSS 363 [EjS BA45 | VSS 2 VSS_7ô [AGI] BT4i | VSS 150 VSS 224 [CE2g DK3 | VSS 299 VSS 364 [T7 BAZZ | VSS 3 VSS 77 FAGTT BT42 | VSS 151 VSS 225 [ếTa; DKä | VSS 300 VSS 365 [Eg BBiT | VSS 4 VSS 78 AG2 BT42 | VSS 152 VSS 226 [ếTäg PK49 | VSS 301 VSS 366 [G5] BB3 | VSS 5 VSS 79 aaa 7 | VSS 153 VSS 227 [CT4za DKẽ | VSS 302 VSS 367 4 BB7 | VSS ô VSS 80 FAG3g BU45 | VSS 154 VSS 228 [@Tg DK§ | VSS 303 VSS 368 Ƒ@ã BG37 | VSS 7 VSS_81 FaGat BU4r | VSS 155 VSS 229 [GŨ4g [io | VSS 304 VSS 369 FSãi D23 | VSS 8 VSS 82 [FT] BVïi | VSS 156 VSS 230 [đũa [13 | VSS 305 VSS 370 FG3g BD238 | VSS 9 VSS_83 [G42 BV11 | VSS 157 VSS 231 FŨag [44 |VSS 306 VSS 371 49 BD26 | VSS 10 VSS 84 FƑAG43 BV2 | VSS 158 VSS 232 [Ca [47 | VSS 307 VSS 372 ƑGp BD4I | VSS 11 VSS 85 [G5 BV3 | VSS 159 VSS 233 [GỤaa DM47 | VSS 308 VSS 373 FT A48 | VSS 12 VSS 86 "Ago BV7 | VSS 160 VSS 234 [GỤag 5 | VSS_309 VSS 374 [H5] BDB42 | VSS 13 VSS_87 Fans BW3 | VSS 161 VSS 235 [QụỤs 9 | VSS 310 VSS 375 FH24 BD43 | VSS 14 VSS 88 [H37 BW37 | VSS 162 VSS 236 F@gg 24 | VSS 311 VSS 376 FHRãI BD4S |VSS 15 VSS 89 ana BWS | VSS 163 VSS 237 FØya 4| VSS 312 VSS 377 [ãa BD49 | VSS 16 VSS 90 [RH4g BWS | VSS 164 VSS 238 FØV4S 36 | VSS 313 VSS 378 F3 D8 | VSS 17 VSS 91 [AE BW7 | VSS 165 VSS 239 FØVag 42 | VSS 314 VSS 379 [H28 De | VSS 18 VSS_92 ays BY37 | VSS_166 VSS 240 [Øyg 45 | VSS_315 VSS 380 [2g D7} VSS_19 VSS_93 -aaq BY45 | VSS 167 VSS 241 13 Rag | VSS_316 VSS 381 [Tịg EEt | VSS 20 VSS_94 [K37 By49 | VSS_168 VSS 242 ƑB7 DTi | VSS 317 VSS 382 [ƑT{ã BE2 | VSS 21 VSS_95 [ATz ii | VSS 169 VSS 243 Bãi ø | VSS 318 VSS 383 [Tịg BE3 | VSS 22 VSS_96 Fara C14 | VSS 170 VSS 244 FB44 5 | VSS 319 VSS 384 [Tae A40 |VSS 23 VSS 97 A[4y Cĩa | VSS 171 VSS 245 [Bạp 50 | VSS 320 VSS 385 [T§ BE4S |VSS 24 VSS 98 LẠ, Ếĩr | VSS 172 VSS_246 pate 2; | VSS 321 VSS 386 [Ki BF47 | VSS 25 VSS_99 [M2 C VSS 173 VSS 247 [A33 3 | VSS 322 VSS 387 [K3 BE7 | VSS 26 VSS 100 [M37 C24 | VSS 174 VSS 248 FAg 32 | VSS 323 VSS 388 [§ BG? | VSS 27 VSS 101 [Nà Cái | VSS 175 VSS 249 BBa5 3| VSS 324 VSS 389 Tag BG41 | VSS 28 VSS 102 [N38 34 | VSS 176 VSS 250 B35 42 | VSS_325 VSS_390 F749 BG7 | VSS_29 VSS 103 [N26 36 |VSS 177 VSS 251 B38 4g | VSS 326 VSS 391 ƑTTi BHäA7 | VSS 30 VSS 104 [R36 C48 | VSS 178 VSS 252 B45 § |VSS 327 VSS 392 ƑT2 B7 | VSS 31 VSS_105 [N41 C46 | VSS 179 VSS 253 B47 DTZ | VSS 328 VSS 393 [28 B72 | VSS 32 VSS_106 [N42 6 |VSS 180 VSS 254 B48 DTa | VSS 329 VSS 394 [T28 Bj3 | VSS 33 VSS 107 [N43 CA3 | VSS 181 VSS 255 C3 Bui | VSS_330 VSS 395 F[27 RAd5 | VSS_34 VSS 108 [N48 CA28 | VSS 182 VSS 256 [B28 DUTï6 | VSS 331 VSS 396 0 BJái | VSS 35 VSS 109 [N49 CA4T | VSS 183 VSS 257 FPGS DŨï8 | VSS 332 VSS 397 3 BJ43 | VSS 36 VSS_110 ƑA CA42 | VSS 184 VSS 258 FPGG DƯE | VSS 333 VSS 398 36 BJ42 | VSS 37 VSS 111ƑAR CA43 | VSS 185 VSS 259 Ba? U20 | VSS 334 VSS 399 Ljj§ Bj49 | VSS 38 VSS_112 [E11 CA7 | VSS 186 VSS_260 42 27 | VSS 335 VSS 400 [N8 J7 | VSS 39 VSS_113 ARs CB37 | VSS 187 VSS 261 E10 Ũ232 | VSS 336 VSS 401 49 BMiT | VSS 40 VSS 114 ƑAES CBis-| VSS_188 VSS 262 [BETA 37 | VSS 337 VSS 402 Ƒpqi BM3 | VSS 4i VSS 115 "agg CB2y | VSS i89 VSS 263 [BETÿ U48 | VSS 338 VSS 403 [pzi BM45 | VSS 42 VSS 116 AB GG@3 | VSS 190 VSS 264 BETg U49 | VSS 339 VSS 404 bạ BM47 | VSS 43 VSS 117 ƑAE§ Cœ | VSS 191 VSS 265 [BEzo PU7 | VSS 340 VSS 405 Bã BMB | VSS 44 VSS 118 [ATã GESr | VSS 192 VSS 266 [BEaz——{ BVz | VSS 341 VSS 406 [Eäz AA47 | VSS 45 VSS 119 [T48 CE45 | VSS 193 VSS 267 FBE23—— DVv44 | VSS 342 VSS 407 ƑTị BMê | VSS 4ô VSS 120 [AT4Z CE2o | VSS 194 VSS 268 FBEsg——{ V48 | VSS 343 VSS 408 [Ta 7 |VSS 47 VSS 121 [ATs CEQ | VSS 195 VSS 289 FBEgsg——{ DV§ | VSS 344 VSS 409 [Ti ï | VSS 48 VSS_122 Fate C637 | VSS 196 VSS 270 E29 DWT | VSS 345 VSS 410 FT 5| VSS 49 VSS 123 [ATz CO36 | VSS 197 VSS 271 [BE ——| DWTð | VSS 346 VSS 411 LTzš 3| VSS 50 VSS 124 AUAZ COja | VSS 198 VSS 272 [BEXE PW2 | VSS 347 VSS 412 4ÿ BP43 | VSS 51 VSS_125 [V11 CG45 | VSS 199 VSS 273 ES 9) VSS 348 VSS 413 [TS BEy | VSS 52 VSS 126 agp Gaaz | VSS_200 V$S 274 FBEIS 7| VSS 349 VSS 414 Ffz B45 | VSS 53 VSS 127 ƑAV3 Gag | VSS 201 VSS 2/5 [PFZ2— | 4| VSS 350 VSS 415 [TS B49 | VSS 54 VSS 128 [ƑAỤ2g CHa3 |VSS 202 VSS 2/6 [ƑBPEZ8B——{ 46 | VSS 351 VSS 416 Ti AB |VSS 55 VSS 129 [AV3g CH§ | VSS 203 VSS 277 [BE3a 48 | VSS 352 VSS 417 Lụag AB3 | VSS 56 VSS_130 [ƑAva1 CT7 |VSS 204 VSS 278 F25 46 | VSS 353 VSS 418 [Ụag AB38 | VSS 57 VSS_131 [va C142 | VSS 205 VSS 279 F29 DW7 | VSS 354 VSS 419 LụỤgg AB29 | VSS 58 VSS 132 [A43 CJg | VSS_206 VSS 280 G10 Eii | VSS 355 VSS 420 Lụg AB4I | VSS 59 VSS 133 | AỤAS CK45 | VSS 207 VSS 281 2 E24 |VSS 356 VSS 421 [Wã7 A17 | VSS_60 VSS 134 | AỤag CK4g | VSS 208 VSS 282 3 E26 | VSS 357 VSS 422 [-yag AB42 | VSS 61 VSS_135 Fay CKg | VSS 209 VSS 283 5 E29 | VSS 358 VSS 423 [-yag AB43 | VSS 62 VSS 136 [A3 CL37_| VSS_210 VSS 284 [ƑBGzZ——{ E42 | VSS 359 VSS 424 -yq3 ABS | VSS 63 VSS_137 [R44 €i42 |VSS 211 VSS 285[ƑBGZ3 {| 6 | VSS_360 VSS 425 Lyg AB6 | VSS 64 VSS_138 [y7 CL49 | VSS_212 VSS 286 47 VSS 361 VSS 426 [pETg AC45 | VSS 65 VSS_139 [E17 M45 | VSS 213 VSS 287 Š VSS 427 AC4g | VSS 66 VSS_140 [E2 CM47 | VSS 214 VSS 288 Hi 17 0f 19 ADi0 | VSS 67 -VSS_141 ->g5;7-—4 ©Me | VSS 215 VSS 289 Ba GLU -BGATEOG ADI1 | VSS 68 VSS_142 ƑBZ4———] CN23 |VSS 216 VSS 290 H45 WZ ¬ VW AD24 | VSS 69 VSS 143 [gã CMã | VSS 217 VSS 291 FBng @ ABAr | VSS 70 VSS 144 [Bãi ÔNä6 | VSS 218 VSS 292 [Big A3 |VSS 71 VSS 145 [B18 TNE] VSS_219 VSS 293 [Bjzi AEa | VSS 72 VSS 146 [BAi ÉPa | VSS 220 VSS 294 Bjz; AEär |VSS 73 VSS 147 FBA2 CE22 | VSS 221 VSS 295 Nai VSS 74 VSS_148 VSS 222 VSS 296 15 of 19 16 of 19 ICL-U_BGA1526 ICL-U_BGA1526 V @ V V @ V Security Classification Compal Secret Data Compal Electronics, Inc Issued Date 2019/04/12 Deciphered Date 2020/04/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Tg; a iN (1 ⁄ ) E AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ze ocument Number ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS FHSLI M/B LA-H801P 1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Trang 19

+1:05V.VGOIO QUT UC1S

[cRess93 TT AVAYA 2 TC 0102 WY CrGt na AGT | CFG1 Sa `“ RSVD_TP_2 |——x

og 1 2 %o *ADø | CFG_2 AD — 1

Ỉ RC3994 ABA 1K 0402 5% : HS are CFG 2 RSVD 57 et

PDG NC this pin ABg | CFG 4 RSVD 58 |——

Ae | CFGS CT4 - E7 | CFG 6 RSVD TP 10 Proves’ 5.5.13 CFG Signals Functionality and Termination

| RCssos rRG3006 1 OY” 1 2 _1K 0402 5% 1K 0402 5% CFGB CFoo Wig] CRG? AJs | CFG 8 RSVD_TP_11 G15 Table 5-76 CFG Signals Functionality and Termination - SH oo

4 RC3998 TT AA A2 1K 0402 5% CEG12 ABi0 req RSVD TP 5 BW11 CFG0 CFG[0]: Stall reset sequence after Pull Up 1K Ohm

RC3999 1 ^^ 2 1K 0402 5% CFG13 AL? CFG 13 RSVD TP 6 CATT PCU PLL lock until de-asserted:

ae CFG 14 oO — 1 = (Default) Normal Operation; No stall

CFG16 Vệ VSS 429 CFG1,8,9,10,12,13 RSVD Pull Up 1K Ohm

V7 reqs RSVD 55 C2 CFG2,3,5,6,7,11,14,15 | RSVD No termination N/A

Ye " RSVD 56 | Aa - CFG4 CFG[4]: eDP enable: Pull Down 1K Ohm CFGI8 Yz | OFG 18 7 DP5 — 1 = Disabled

An external display port device is connected to <— RSVD_68 DH4

the embedded displayport R10 RSVD_TP_9 | Diag

T2s8 TP@@-a 1ÊKTOGC# C6 RSVD TP 26 ~

1289 TP@@+ AS | RSVD_77

>———] RSVD 64 19 of 19 ICL-U_BGA1526

RSVD_TP_28 RSVD_TP_35

RSVD TP2g NERVEDSIGNAIS GV _TP_36

RSVD_7 RSVD_TP_37 RSVD_TP_30 RSVD_32 RSVD_TP_31 RSVD_33 RSVD_TP_32 RSVD_34 RSVD_12 IST_TP_O RSVD_TP_33 IST TP 1 RSVD TP 34 IST_TRIG_O RSVD_TP_27 IST_TRIG_1

RSVD 52 IAN§

RSVD 53 FAN7

RSVD_ 54 [RE]

U42 RSVP 36 [ AE W42 | RSVD 42 RSVD 37 [Hg D32 | RSVD 43 RSVD 38 [p<

*Tã | RSVD 44 RSVD_39 [Ba

>———] RSVD 47 RSVD 41 ICL-U_BGA1526

@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Fg; ICL- U1 3/13)RSVD, CFG A AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ze ocument Number ev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS FH5LI M/B LA-H801P 1.0 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Date: Tuesday, October 15, 2019 102

Trang 20

Trang 21

Trang 22

Trang 23

+1.2V_VDDQ 3| VDD4 VDD14 3

4| VDD5 VDD15 |-754 39] VDDS VDD16 [g8

> 0-1U_9201_10V6K ves ves 06

vss VSS [67

li 4| VSS VSS [68

vss VSS TF vss VSS az vss VSS F7

q 5] VSS VSS 5ã

q 36] VSS VSS F379 7| VSS VSS [1ã

ø | vSS VSS aig 7] vss VSS a7

41 vSS VSS Faia

q 5] VSS vSS F§55 8] VSS VSS [Z2 ø8 | VSS VSS F528 72] VSS VSS ƑZ27 73] VSS vss 55g 77] VSS VSS 53]

78 | VSS VSS [Z4 a1] VSS VSS [535

4 aa] VSS VSS a3

q a5] VSS VSS F339

q 36] VSS VSS F543 3] VSS VSS Faq

ñ | vSS VSS [227 3-] VSS VSS ag 4] VSS VSS 353

q 38 | VSS VSS 553 vss vss

4 282 | sp ewp L8!

W FOX_AS0A821-H4SB-7H WY CONN@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDE MI

S AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI THE CUSTODY O F THE COMPETENT DIVISION OF

<8> DDR_A_DOQS#0 7| < ——— 508 A của JDIMM2A 508 A Đi

137 STD 8

DUR_A_CLRT 138 | CKO#(G) Dai Fag DUR-A-D56

<8z DDR A DQSI0.7] < ———— —DDF-A-CIK#T— T40] CKI() DQ2 ƑƑZ] DDE_A D57

| CK1#(C) DQ3 rq DDH_A_DED DDR_A_CKEO 109 DQ@4 DDR_A_D58

<8> DDR_A_MA[O 16] TT6 | CKE0 DQ5 746 DDR_A Doo

DDR_A_BAO 43VS — CKET DQ6 [T7 DDE.A D50

<> Ean _A BAO DDR A BA fo} DDR_A_CS#0 _ 148 ou paso) 3 DDR_A_DOST

<8> <8> DDR _A Í A BGO DDR_A_CS#T — aL] sis pasox(c) H4 DDR_A_DOS#7 —

<8> DDR_A BG1 X-Tgg-| S2#/C0 DDR A D44

<8> DDR_A ACT# = ~5%] S3#/C1 Das F5——mr+>-mr—

<8> DDR A PAR = 761] ODTO DGQ10 F4g———DpDRA D45

ODT1 DG11 Fð2——DDRAD4T—

<8> DDR A CLKI DDH_A_SAU | BÀI DQS1(T) -35-—DDR_A_DOSES

<8> DDR A GLK#1 — DDR_A MAO 44 BaQsi#(C)

DOR_A_MAT 33 no bois 50 DDR_A_D54 DDR_A_MAZ 32 49 DDR_A_D53

<8> DDR_A_CKEO DDR_A_MAS 31] A2 DQI7 Feo Al Data swap 12/12

<8> DDR A GKE1 TDDREA MAT — 128 | A2 DQ18 F 63 DDR_A_D48

<8> DDR_A_CS#0 —DDR_A_MAS 126 1] A4 DQ19 46 Tr]

<8> DDR_A_CS#1 TDURTA_LMAB 127,] A5 DQ20 [q5 DUR_A_D5T

—DDR-A- MAT ——132-] AS DQ21 /s3s—— DDR DS SƠC SMEDATATTTn —DDH-T MAR ae] AZ DQ22 FE8———DE “ni

<9,66> SOC_SMBCLK_1 = = ị DDR AMATO 46 | A9 DQS2(T) -53-——DDR_A_ DOSES” , — ¬

DDR_A_MATT 20 AIo_AP DOS2#(C) FC CC DORA ODTO 1 DDR_A_MAT2_119 7 DDR_A_D33

<8> DDR_A ODTO ESmr—— ị a i58 | Al2 DQ24 a DDHA D25

<8> DDR A ODT1 —— 7a iãi | A13 DQ25 DDR-A-D35 249 0402 1%

DDR_A_MATS T56 | A14 WE# DQ26 [B4 DDHA D22 —

TT ï52 | A15 _CAS# DQ27 DUE RA U30

— —| A186 RAS# DO28 DDE.A D37 DDR_ A ACT# 114 DQ29 7s DDRE A D54

AGT# DQ30 [gg DDR_A_ Dae

DDRAPAR 143 | airy D os30) [76 DDR ADOST

Layout Note: apes 2 1 240 0402 1% = ALERT# DOS3#(C) p74 PƯYACA UV oể

Place near JDIMM2 +1.2V_VDDQO ————— nạ EVENT# 74 DDR A D19

<8,24> DDR_DRAMRST# - = RESET# DQ82 [-473-—DDR Des

DQ33 77

0 BD1 1 ,.@, 2 470 0402 5% 87 DDHA DIE

GD30 2 || 1 1U 0402 18V7K 253 | SDA DO35 [T7B_——DDH.A DZI

SCL DO36 | Tạo ——DDH-A_DZZ —

——CNB CS TC LYš TCAIK CCYš meek oe as 24T | DM6#/DBI6E DQS5 [327 DDR_A_DOS3—

Na No NS ya Nis Nie Na No sẽ | DM7#/DBI7# DQS6(T) FðTg——DDHA DUEET

add 1 cap for MLCC downsize

INS

Title

DDR4 DIMMA

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At2/BG DQUS T At2/BG

13 DQU8 T a AIAWE DQU7 AIAWE

<8» DDH B BAO BAO Req BA

<$> DDR-B BÀI BÀI — BAI

7 ‘ee 9 0 0402_8% DDF-E-DUSD B7 Di ‘ee 9

DDP_B_BG1 DRG, TDEE DU? FT| 1 DDR_B_BG1_R

vss ri RD78 ost v9S Em MEMBST# P1 vss 0_0201_1% MEMBST# PHẾ vss

RESET DE@ 2 |DDH B BGi RESET

1 2_RD210 Fat og t 1 MEM@ 2 RD211 Fat og

ƒ 0402 1% DDR_A intel :549352) ƒ 0402 1%

1 Near SOC side

<@> DDH B AOTE DDR_B_ACT# 3 TET vsso 2 BI 15021 small then other oo er vsso DDR_B_BGO = ey BGO vssa CMD 25mils oT BGO vssa

Ð Vssỏ 3 Rơi teo2 small then 800mils _"——-—.— #Ð Vssỏ DDR_B_ALERT# FET ALERT vssa, Sore PAR ALERT vssa,

<8 DDI — PAR vssa —————=— eer vssa

T vssa T vssa

tH NC vssQ NC vssQ

128VO——†—Te | VPP vssa 189VO——†—ïg | VPP vssa

VPP SSO VPP SSO

<8» DDR_B MAI0.I0Ị << >> —— 96-BALL S80 96-BALL SSO

<> DDR_B_DOS#(0.7] <> SDRAM DRS SDRAM DRS

LuF*16 (SOC side} 200_1% | 121.1%

+ D237 H SDP@ H SDP@

d.ddd d.ddd d.ddd d.ddd 4q.4d.4.4.4, FR c30u peevy RD207 RD2og

d› d; d; 3 2iqegeqe Gegeqeqe d› d; d; 3 d› d; d; 3 Geqegege qeigeqe ge d› d; d; 3 a, 3d, 3, 3d, d, eR 4? ?.42.92.42 ê| soaooooesoo LD2_2V¬ 0 0402 5% 0 0402 5%

gg qgQq gg qgQq gg qgQq gg qgQq gqgaqaqq 330U 2V H1.9 SD028000080 SD028000080

qq q qq q q qq q q qq q q ‘ol ‘el ‘ol 9mohm POLY

qaaqagq dị qaaqagq dị qaaqagq dị qaaqagq dị

gag dị s 5 gag dị s 5 gag dị s 5 gag dị s 5 ä 3 3 3

2 as near each on board RAM device as possible ị

A for nh 2 as near each on board RAM device aS possible benefit forapdownsee ren

—rrrr“rm "71A5 DQU1 Fe DOB Daa

—TTH-E-WTD ag bou2 Fe DORE

—rrrrE MxTT AIDAP DQU3 Fe DORE

rT 11 Daus Fe DDR_B_Da

EAT A12/BG DQUS TH TT

TAT es AIANWE DQU6 DQU7 DH E5

DDR_B_BAO —— N2 sy BAO

BAI E2 +têV_VDDQ O——†—————D—F | DMUDEU

ĐMUDBIL DDR_B_CLKO — Kz zy Kt

a S99 TTTTHETNH— ——— T3Ị Nệm — ` S99 ssQ

T ssQ

Á4————r- NG vssa

1280—†——Rÿ | VPP ssQ

VPP ssQ g6-BALL V88G SDBAM DDEA

—nmrrrm Roy A? DQU0 PB DORE

ae Ary 48 baui fe DOSED ——

oar AIWAP DQU3 Fe TH DI CC

—rrrr“rm AI — Dau4 Fe DOR_B Dog

oe aT A12/BG DQUS DƯ B1

—trrrmr — es AIAIWE DQUS DQU7 DORE Des “

DDR_B_BAO ne BAO B3 +1.2V_VDDQ

BÀI ồ

soba, o— pF} opto DMLDBIL 7

DDR_B_CLKO 1M oy SDORECER —————— ROK ei:

ee KE

DDH_B_ODT0 «39 oor STO OD

TE ST E7 — J

DORE USTs Fr] DOsut vss Frye es

DOE oss 005L c vss Fat 9 S8

X78@

+1.2V_VDDQ

+0.8V8_VTT

MEM@\ 2 49 0201 1%

RD214 1 IWIEXI

+0.8V§_VTT DDR_B_BG1_R RD86 1 RDE@, 2 39 0201 1%

DEPARTMENT EXCEPT AS AUTHORIZE!

THIS SHEET OF ENGINEERING DRAWING IS 7 HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST! ODY OF THE COMPETENT DIVISION OF

D BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONT:

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+LCGDVDD UX1

Cx U_0402_16V7 EDP_TXP0_C

<6> EDP_TXPO OX U_0402_16V7 EDP-TXNỮC

<6> EDP_TXNO ona ee —————

<6> EDP TXPI căm " =———

<6> EDP TXNI ont ee —————

<6> EDPE TXNG CX16 U_0402 16V7 EDP TXN2 C

SẼ EDB TXra CX19 U_0402 16V7 EDP-TXPS-C

Sốc EDP TXN3 CX18 U_0402_16V7 EDP.TXN3 C

W=60mils W=60mils +3V§

HCB2012KF-221T30_0805

2200hm@100mhz nano ne 00 68P_0402_50V8.J P 5Š 0.1U_0201_10V6K 1U_0402_16V7K

EDF TXN2 C 244 23 25Q 24

9 EDP_TXP3_C j 264 29

<6,58> TS EN [> TS_EN 34 34

+3VSO USB20_N7_CAMERA 36C 25 For USE20_P7_CAMERA 3744 36

eDP Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Ƒer 5 Numb Fy

AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Cuero ocument Number “ 9

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS : MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC FH5LI M/B LA-H801P

Date: Tuesday, October 15, 2019 102

[Sheet 38 of

E

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h IN cys +HDMI 5V_OUTO RY27 „1 VV 2 22K 0402 5% HDMILCTRL_DAT HDMI_C_CLKP 2 AAAI ~Ì: HDMLR _CLKP

port 0, 2 swap for INTEL HDMI

GYi4 2 |] 1 01U 0201 10V@K HDMLC TX_P0 BY31 1 2_ 470 0402 5%

ee Boe DRO ND F< CYI5 2 || T 01U 0201 10V6K HDMILC TX N0 RY32_1 22 2470 0402 5%

<6> SOC DP2 P1 cYi2 2 1_01U_0201_10V6K_HDMI_C_TX_P1 RY33_1 ^^^ 2_470 0402 5% RY43 5.6 0402 5%

| | — —-XYX —-—————‡

‹ soo bp NO F< CYi1 2 || Ì 01U 0201 10VeK HDML_C_TX_N2 RY36 1 AVAVA 2 4/0 0402 5%

HDMI_R_TX_P2 † | D2 shield GND3 [ 20

DC232007600 CONN@

E TRANSFERED CUSTODY OF TH

IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

E B RED FROM THE E COMPETENT DIVISION OF R&D THORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION I

HDMI CONN

usio Size i Document Number FHSLI M/B LA-H801P

Rev 1.0

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