Acer aspire r7 571g compal LA a001p rev 1 0 схема

THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC.. THIS SHEET M

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Model Name : Ezel_CX

Board NO: LA-A001P

Compal Confidential

with On Board DRAM, 1Rx8, 8 pcs

DA8000WC210 PCB 0YO LA-A001P REV1 M/B 5 S DA8000WC200 PCB 0YO LA-A001P REV0 M/B 5 S PCB

*

updated for new panelization

Panelization Information Main Board

I/O Board Sensor Board LAN Board LED Board PWR Board E-Compass Board

LA-A001P LS-A001P LS-A002P LS-A004P LS-A005P LS-A006P LS-A007P

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

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SATA 3.0

HDD Connecotr

Port1 Port0

KB Connector Click Pad

Connector

User Interface DC/DC Interface

Intel Ivy Bridge ULV Processor 2C BGA1023

Page 12 Page 4~10

DMI Gen 2x 4 FDI x8

NVIDIA N14P-GT(35W) FCBGA908

PCIe Gen-2, 8-Lane, 5GT/s

PEG

GDDR5 1.5V

eDP Connector 4-Lane Reserved

Page 32

eDP

Cost Reduced HDMI Connector

Page 32

DPD

Page 33

Dongle Port Controller with TI HD3SS2521

PCIE BUS

Port3

1/2 Mini Card WLAN/WiFi

Port2

Page 35 USB port 8

Card Reader RTS5229 SD3.0

Page 37

I/O Board Connector

Page 32

On Sensor Board Page 37

Full Mini-Card mSATA

Page 35

HDA Codec ALC3225-CG

Page 40

Int SPKR CONN Right Side

Int SPKR CONN Left Side

Amplifier ALC1001-CGT

Page 41

DMIC Array

Page 41 Page 13~21

W25Q16CVSSIG(2MB)

Placeholder Reserved Only, Page 14

TPM SLB9655TT1.2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

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S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON ON ON ON

ON ON

ON ON ON ON

ON

OFF OFF OFF

OFF OFF OFF OFF OFF

LOW

LOW LOW LOW LOW

LOW LOW LOW LOW LOW LOW

HIGH HIGH HIGH HIGH

HIGH HIGH HIGH HIGH HIGH HIGH

On Board Thermal Senser 1001_101xb

dGPU@

with dGPU

USB3.0 port (lower)

USB 2.0 USB 1.1 Port 3 External USB Port

0 1 2 3 4 5 6 7 8 9 10 11 12 13

PCB Revision 0.1

BTO Option Table

Board ID / SKU ID Table for AD channel Vcc 3.3V +/- 5%

100K +/- 5%

Ra/Rc/Re

0 1 2 3

0 8.2K +/- 5%

0 V

0.436 V 0.712 V

0.503 V 0.819 V

0.538 V 0.875 V

1.036 V

1.935 V 2.500 V

2.200 V 3.300 V

2.341 V 1.185 V 1.264 V

USB3.0 port with charging (upper) Lightning-Bolt with TI solution

NGC6@

Mini-Card for WiFi External port- USB 2.0 only CMOS Camera Touch Panel Sensor Hub

Port USB 3.0

power supply for CPU System Agent Voltage +VCCSA

source from internal LDO of PU501, for DDR3 terminator +0.75VS

System Power Rails

AC or battery power rail for power circuit.

Adapter power supply (19V)

+1.05VS_VTT

B+

VIN

source from 5VALW, for CPU VCCIO and PCH Core Power Well

Power Supply for CPU Core Power Well

+5VALW_PCH

N/A

Description Power Plane

use 5VALW source, for DDR3 and for 1.5VS Gate

OFF

OFF OFF OFF

ON

OFF

ON OFF OFF

OFF OFF

OFF* OFF* OFF*

OFF*: always connected is not supported by default

ON

+1.5V

ON ON ON

N/A N/A N/A N/A

ON ON ON

ON ON

OFF OFF OFF OFF OFF

ON ON ON

ON

OFF OFF

ON

OFF OFF OFF OFF

+RTCVCC

S5

Battery power supply (12.6V) BATT+

use 3VALW source, for CPU VDDPLL and PCH LVDS power +1.8VS

5V Power Source from 3V/5V IC

from 5VALW, power supply for 5V device +5VS

5V Power Supply for PCH VccSus Power Well

+3VS_WLAN 3V power supply for WLAN

+3V_LAN 3V power supply for RTL8111GS-CG LAN IC(on D/B)

ON ON

ON*

ON

OFF OFF OFF OFF

reserved for EMC

RF@

RF solution

XEMC@

@ CONN@

no stuff Connector

HM77@

PCH HM77

HYNMFR@

VRAM Hynix-MFR

ON*: 1.5VSDGPU will be switched off by GC6 toggleed

0.2

0.3 0.4

Title

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1 1

1 PEG_RCOMPO and PEG_ICOMPI should be connected together with 4-mil width first Then be connected to R1 from ball of PEG_ICOMPI.

2 PEG_ICOMPO should be connected to R1 with width 12-mil.

3 No longer than 500-mil to above two.

eDP_COMPIO and eDP_ICOMPO should be connected to R3 respectively.

Trace Width to R3= 4-mil

Trace Spacing to Other Signals= 15-mil

Max Routing Length= 500-mil

Trace Width to R3= 12-mil

Trace Spacing to Other Signals= 15-mil

Routing Length= 500-mil

EDP_TXN0

EDP_TXP0CPU_EDP_HPD#

PEG_GTX_HRX_N0PEG_GTX_C_HRX_N0

PEG_GTX_HRX_N5

PEG_GTX_C_HRX_P3 PEG_GTX_HRX_P3PEG_GTX_C_HRX_P2 PEG_GTX_HRX_P2PEG_GTX_C_HRX_P1 PEG_GTX_HRX_P1PEG_GTX_C_HRX_P0 PEG_GTX_HRX_P0

PEG_GTX_C_HRX_P7 PEG_GTX_HRX_P7PEG_GTX_C_HRX_P6 PEG_GTX_HRX_P6PEG_GTX_C_HRX_P5 PEG_GTX_HRX_P5PEG_GTX_C_HRX_P4 PEG_GTX_HRX_P4

PEG_GTX_HRX_P11PEG_GTX_C_HRX_P11

PEG_GTX_C_HRX_P15 PEG_GTX_HRX_P15PEG_GTX_C_HRX_P14

PEG_HTX_C_GRX_N3PEG_HTX_GRX_N3

PEG_HTX_C_GRX_P3PEG_HTX_GRX_P3

Title

R21K_0402_5%

C26 dGPU@0.22U_0402_6.3V6KC26 1 2dGPU@0.22U_0402_6.3V6K

P6DMI_RX#[2]

P1DMI_RX#[3]

P10

DMI_RX[0]

N3DMI_RX[1]

P7DMI_RX[2]

P3DMI_RX[3]

P11

DMI_TX#[0]

K1DMI_TX#[1]

M8DMI_TX#[2]

N4DMI_TX#[3]

R2

DMI_TX[0]

K3DMI_TX[1]

W11FDI0_TX#[2]

W1FDI0_TX#[3]

AA6FDI1_TX#[0]

W6FDI1_TX#[1]

V4FDI1_TX#[2]

Y2FDI1_TX#[3]

AC9

FDI0_TX[0]

U6FDI0_TX[1]

W10FDI0_TX[2]

W3FDI0_TX[3]

AA7FDI1_TX[0]

W7FDI1_TX[1]

T4FDI1_TX[2]

AA3FDI1_TX[3]

AC8

FDI0_FSYNCAA11FDI1_FSYNCAC12

FDI_INTU11

FDI0_LSYNCAA10FDI1_LSYNCAG8

AA4eDP_TX[2]

AE10eDP_TX[3]

AE6

eDP_COMPIOAF3

eDP_HPD#

eDP_TX#[0]

AC3eDP_TX#[1]

AC4eDP_TX#[2]

AE11eDP_TX#[3]

AE7

C46 dGPU@0.22U_0402_6.3V6KC46 1 2dGPU@0.22U_0402_6.3V6KC47 dGPU@0.22U_0402_6.3V6KC47 1 2dGPU@0.22U_0402_6.3V6K

R124.9_0402_1%

R324.9_0402_1%

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1 1

For 2nd Generation IntelR Core processor family mobile, the output will be high.

For Mobile 3rd Generation IntelR Core processor family, the output will be low.

THERMALTRIP# will be asserted when CPU junction temperature exceeds approximately 130 °C

care should be taken to no stub caused by R10

SM_DRAMPWROK

Buffered Reset to CPU

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

Width

20-mil 20-mil 15-mil

C573 should be as close as possible to CPU

H_CPUPWRGD

XDP_TCKXDP_TMSXDP_TRST#

SM_RCOMP1H_PROCHOT#_R

+1.05VS_VTT+3VS

+3VS

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

R11200_0402_5%

PROC_DETECT#

C57PROC_SELECT#

F49

UNCOREPWRGOODB46

T5PAD

XEMC@ C5510.1U_0402_16V7K

XEMC@

1

2

R1543_0402_1%

T3PAD

XEMC@ C5730.1U_0402_16V7K

XEMC@

1

2

C680.1U_0402_16V7KC680.1U_0402_16V7K1

2

C670.1U_0402_16V7KC670.1U_0402_16V7K

1

2

R1275_0402_5%

T4PAD

MC74VHC1G09DFT2G_SC70-5

B1

SN74LVC1G07DCKR_SC70-5

NC1

A2

@ PADT2

@

T6PAD

@ PADT6

@

R91K_0402_5%

C650.1U_0402_16V7K

XEMC@

C650.1U_0402_16V7K

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S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH DRAM not reset

S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# low,DDR3 DRAMRST# low DRAM reset

for S3 Power ReductonDDR_A_D63

DDR_A_D8DDR_A_D3

DDR_A_D7DDR_A_D5

DDR_A_D59DDR_A_D57

DDR_A_D47DDR_A_D42

DDR_A_D61

DDR_A_D2DDR_A_D0

DDR_A_D55DDR_A_D51DDR_A_D48DDR_A_D50DDR_A_D52

DDR_A_D31

DDR_A_D14

DDR_A_D25DDR_A_D27

DDR_A_D30

DDR_A_D9

DDR_A_D13DDR_A_D10

DDR_A_D29

DDR_A_D19DDR_A_D16

DDR_A_D21DDR_A_D17

DDR_A_D22DDR_A_D18

DDR_A_D23

DDR_A_MA15DDR_A_MA0

DDR_A_MA14

DDR_A_MA5

DDR_A_MA1DDR_A_MA3

DDR_A_MA9DDR_A_MA7

DDR_A_MA12DDR_A_MA8DDR_A_MA11

DDR_B_D33DDR_B_D14

DDR_B_D29DDR_B_D24

DDR_B_D34

DDR_B_D4

DDR_B_D26

DDR_B_D13DDR_B_D10

DDR_B_D21DDR_B_D11

DDR_B_D57DDR_B_D44

DDR_B_D37

DDR_B_D48DDR_B_D36

DDR_B_D18DDR_B_D8

DDR_B_D47DDR_B_D9

DDR_B_D60DDR_B_D50

DDR_B_D62DDR_B_D52DDR_B_D2

DDR_B_D51

DDR_B_D56DDR_B_D39

DDR_B_D22

DDR_B_D28DDR_B_D6

DDR_B_D45DDR_B_D17

DDR_B_D58DDR_B_D61

DDR_B_MA15

DDR_B_MA0

DDR_B_MA9DDR_B_MA7

DDR_B_MA13

DDR_B_MA2DDR_B_MA4

DDR_B_MA11

DDR_B_MA3DDR_B_MA5

DDR_B_MA10DDR_B_MA8DDR_B_MA1

DDR_B_MA12DDR_B_MA14

DIMM_DRAMRST#_RSM_DRAMRST#

DDR_A_DQS#7

DDR_A_DQS#0DDR_A_DQS#2DDR_A_DQS#5DDR_A_DQS#3DDR_A_DQS#1

DDR_A_DQS#4DDR_A_DQS#6

DDR_A_DQS0DDR_A_DQS2

DDR_A_DQS6DDR_A_DQS4DDR_A_DQS7

DDR_B_DQS7

DDR_B_DQS0

DDR_B_DQS5DDR_B_DQS3DDR_B_DQS6

DDR_B_DQS#1

DDR_B_DQS#7DDR_B_DQS#5

DDR_B_DQS#0

DDR_B_DQS#3DDR_B_DQS#6DDR_B_DQS#2

R171K_0402_5%

C690.047U_0402_16V7KC690.047U_0402_16V7K

R194.99K_0402_1%

LBSS138LT1G_SOT-23-3Q1

13

R18 1K_0402_5%

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PEG DEFER TRAINING

PEG Wait for BIOS for training

(Default) PEG Trains immediately and follows xxRESETB de-assertion

CFG4

eDP Enable Strap

Enable (Default)Disable

CFG Straps for Processor

PCIe Static x16 Lane Numbering Reversal CFG2

Lane Reversed

(Default)Normal Operation Lane # definition matches socket pin map definition

2x8 PCI Express PCIE Port Bifurcation Straps

DC_TEST_C4_D3

DC_TEST_A59_C59DC_TEST_A61_C61

DC_TEST_BE59_BE61DC_TEST_BG59_BG61

DC_TEST_BE3_BG3DC_TEST_BE1_BG1

CFG2CFG0

CFG4

Title

R281K_0402_1%

R261K_0402_1%

C51CFG[2]

B54CFG[3]

D53CFG[4]

A51CFG[5]

C53CFG[6]

C55CFG[7]

H49CFG[8]

A55CFG[9]

H51CFG[10]

K49CFG[11]

K53CFG[12]

F53CFG[13]

G53CFG[14]

L51CFG[15]

F51CFG[16]

D52CFG[17]

VSS_VAL_SENSEK43

VAXG_VAL_SENSEH45

VSSAXG_VAL_SENSEK45

VCC_DIE_SENSEF48

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1 1

Place the PU resistors close to CPU

Place the PU resistors close to VR

4 0.675~0.9

29 0.65~1.25

System Agent Voltage

Refer to Mobile 3rd Generation IntelR Core Processor Family External Design Specification (EDS) Volume 1 of 2 Revision 2.2

CPU Power Rail Table

Processor Core Voltage Processor Uncore Voltage Memory Controller Voltage

VCC VCCIO VDDQ VCCSA VCCPLL VAXG

Processor PLL Voltage

Voltage Rail

0.65~1.2 33 Voltage S0 Iccmax Current(A)

Processor Graphics Voltage

VSSIO_SENSEVSSSENSE

VR_SVID_ALERT#

VR_SVID_CLKVR_SVID_DATAVCCIO_SEL

+1.05VS_VTT

+1.05VS_VTT+CPU_CORE

+1.05VS_VTT

Title

R3075_0402_5%

R32100_0402_1%

R29130_0402_5%

@PAD T46

@

R34100_0402_1%

A29VCC[3]

A31VCC[4]

A34VCC[5]

A35VCC[6]

A38VCC[7]

A39VCC[8]

A42VCC[9]

C26VCC[10]

C27VCC[11]

C32VCC[12]

C34VCC[13]

C37VCC[14]

C39VCC[15]

C42VCC[16]

D27VCC[17]

D32VCC[18]

D34VCC[19]

D37VCC[20]

D39VCC[21]

D42VCC[22]

E26VCC[23]

E28VCC[24]

E32VCC[25]

E34VCC[26]

E37VCC[27]

E38VCC[28]

F25VCC[29]

F26VCC[30]

F28VCC[31]

F32VCC[32]

F34VCC[33]

F37VCC[34]

F38VCC[35]

F42VCC[36]

G42VCC[37]

H25VCC[38]

H26VCC[39]

H28VCC[40]

H29VCC[41]

H32VCC[42]

H34VCC[43]

H35VCC[44]

H37VCC[45]

H38VCC[46]

H40VCC[47]

J25VCC[48]

J26VCC[49]

J28VCC[50]

J29VCC[51]

J32VCC[52]

J34VCC[53]

J35VCC[54]

J37VCC[55]

J38VCC[56]

J40VCC[57]

J42VCC[58]

K26VCC[59]

K27VCC[60]

K29VCC[61]

K32VCC[62]

K34VCC[63]

K35VCC[64]

K37VCC[66]

K39VCC[67]

K42VCC[68]

L25VCC[69]

L28VCC[70]

L33VCC[71]

L36VCC[72]

L40VCC[73]

N26VCC[74]

N30VCC[75]

N34VCC[76]

R3510_0402_5%

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+V_SM_VREF should be 20-mil trace width and 20-mil spacing

Place BOT OUT BGA Place TOP IN BGA

VCCPLL Plane Decoupling Recommendation from Intel PDDG Rev 1.0,

1 1x 330uF

*For ULV Only

0

VCCSA Output 1

1

0.9V 0.85V 0.775V 0.75V

Follow VDDQ 1.5V-Rail Decoupling Recommendation from Intel PDDG Rev 1.0,

R361K_0402_5%

AB47VAXG[3]

AB50VAXG[4]

AB51VAXG[5]

AB52VAXG[6]

AB53VAXG[7]

AB55VAXG[8]

AB56VAXG[9]

AB58VAXG[10]

AB59VAXG[11]

AC61VAXG[12]

AD47VAXG[13]

AD48VAXG[14]

AD50VAXG[15]

AD51VAXG[16]

AD52VAXG[17]

AD53VAXG[18]

AD55VAXG[19]

AD56VAXG[20]

AD58VAXG[21]

AD59VAXG[22]

AE46VAXG[23]

N45VAXG[24]

P47VAXG[25]

P48VAXG[26]

P50VAXG[27]

P51VAXG[28]

P52VAXG[29]

P53VAXG[30]

P55VAXG[31]

P56VAXG[32]

P61VAXG[33]

T48VAXG[34]

T58VAXG[35]

T59VAXG[36]

T61VAXG[37]

U46VAXG[38]

V47VAXG[39]

V48VAXG[40]

V50VAXG[41]

V51VAXG[42]

V52VAXG[43]

V53VAXG[44]

V55VAXG[45]

V56VAXG[46]

V58VAXG[47]

V59VAXG[48]

W50VAXG[49]

W51VAXG[50]

W52VAXG[51]

W53VAXG[52]

W55VAXG[53]

W56VAXG[54]

Y61

VCCPLL[3]

BC4

VAXG_SENSEF45VSSAXG_SENSEG45

V17VCCSA[14]

V18

VCCSA[4]

N20VCCSA[5]

N22VCCSA[6]

W20

VCCSA[2]

L21VCCSA[3]

R41100_0402_5%

R371K_0402_5%

C710.1U_0402_16V7KC710.1U_0402_16V7K

R40100_0402_5%

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A17VSS[3]

A21VSS[4]

A25VSS[5]

A28VSS[6]

A33VSS[7]

A37VSS[8]

A40VSS[9]

A45VSS[10]

A49VSS[11]

A53VSS[12]

A9VSS[13]

AA1VSS[14]

AA13VSS[15]

AA50VSS[16]

AA51VSS[17]

AA52VSS[18]

AA53VSS[19]

AA55VSS[20]

AA56VSS[21]

AA8VSS[22]

AB16VSS[23]

AB18VSS[24]

AB21VSS[25]

AB48VSS[26]

AB61VSS[27]

AC10VSS[28]

AC14VSS[29]

AC46VSS[30]

AC6VSS[31]

AD17VSS[32]

AD20VSS[33]

AD4VSS[34]

AD61VSS[35]

AE13VSS[36]

AE8VSS[37]

AF1VSS[38]

AF17VSS[39]

AF21VSS[40]

AF47VSS[41]

AF48VSS[42]

AF50VSS[43]

AF51VSS[44]

AF52VSS[45]

AF53VSS[46]

AF55VSS[47]

AF56VSS[48]

AF58VSS[49]

AF59VSS[50]

AG10VSS[51]

AG14VSS[52]

AG18VSS[53]

AG47VSS[54]

AG52VSS[55]

AG61VSS[56]

AG7VSS[57]

AH4VSS[58]

AH58VSS[59]

AJ13VSS[60]

AJ16VSS[61]

AJ20VSS[62]

AJ22VSS[63]

AJ26VSS[64]

AJ30VSS[65]

AJ34VSS[66]

AJ38VSS[67]

AJ42VSS[68]

AJ45VSS[69]

AJ48VSS[70]

AJ7VSS[71]

AK1VSS[72]

AK52VSS[73]

AL10VSS[74]

AL13VSS[75]

AL17VSS[76]

AL21VSS[77]

AL25VSS[78]

AL28VSS[79]

AL33VSS[80]

AL36VSS[81]

AL40VSS[82]

AL43VSS[83]

AL47VSS[84]

AL61VSS[85]

AM13VSS[86]

AM20VSS[87]

AM22VSS[88]

AM26VSS[89]

AM30VSS[90]

BG21VSS[183]

BG24VSS[184]

BG28VSS[185]

BG37VSS[186]

BG41VSS[187]

BG45VSS[188]

BG49VSS[189]

BG53VSS[190]

BG9VSS[191]

C29VSS[192]

C35VSS[193]

C40VSS[194]

D10VSS[195]

D14VSS[196]

D18VSS[197]

D22VSS[198]

D26VSS[199]

D29VSS[200]

D35VSS[201]

D4VSS[202]

D40VSS[203]

D43VSS[204]

D46VSS[205]

D50VSS[206]

D54VSS[207]

D58VSS[208]

D6VSS[209]

E25VSS[210]

E29VSS[211]

E3VSS[212]

E35VSS[213]

E40VSS[214]

F13VSS[215]

F15VSS[216]

F19VSS[217]

F29VSS[218]

F35VSS[219]

F40VSS[220]

F55VSS[221]

G51VSS[222]

G6VSS[223]

G61VSS[224]

H10VSS[225]

H14VSS[226]

H17VSS[227]

H21VSS[228]

H4VSS[229]

H53VSS[230]

H58VSS[231]

J1VSS[232]

J49VSS[233]

J55VSS[234]

K11VSS[235]

K21VSS[236]

K51VSS[237]

K8VSS[238]

L16VSS[239]

L20VSS[240]

L22VSS[241]

L26VSS[242]

L30VSS[243]

L34VSS[244]

L38VSS[245]

L43VSS[246]

Trang 11

1 1

All VREF_DQ and VREFCA should be rounted with width

at least 20-mil and with spacing at-least 20-mil.

1 +V_DDR_REFA

2 +V_REF_CA

Should be as close as possible to sink of JDIMM1

Should be as close as possible to sink of JDIMM1.203 and JDIMM1.204

+V_DDR_REFA

DDRA_CS0_DIMMA#

SA_ODT0SA_ODT1

SA_CLK_DDR1SA_CLK_DDR#1DDR_A_MA2DDR_A_MA4DDR_A_MA7DDR_A_MA11DDR_A_MA14

DDR_A_BS1DDR_A_RAS#

DDR_A_MA15DDRA_CKE1_DIMMA

DDR_A_DQS3DDR_A_DQS#0

DDR_A_D62

DDR_A0_DM4

DDR_A0_DM6DDR_A_DQS5

DDR_A_DQS7DDR_A_DQS#5

DDR_A_DQS#6DDR_A_D48

DDR_A_D33DDRA_CS1_DIMMA#

DDR_A_MA1DDR_A_MA5DDR_A_MA9

DDR_A_MA10DDR_A_MA12

DDR_A_MA13DDR_A_BS0DDR_A_BS2

DDR_A_CAS#

DDR_A_WE#

DDRA_CKE0_DIMMA

SA_CLK_DDR0SA_CLK_DDR#0

DDR_A_D0

DDR_A_D2DDR_A_D1

DDR_A_D3DDR_A_D8

DDR_A_DQS#2DDR_A_D17DDR_A_D9

DDR_A_D16

DDR_A_D25

DDR_A0_DM5DDR_A0_DM3

DDR_A0_DM7DDR_A0_DM0

DDR_A0_DM6DDR_A0_DM4DDR_A0_DM2

+V_DDR_REFA+VREF_CA

Title

VSS23

DQ05

DQ17

VSS49

DM011

VSS513

DQ215

DQ317

VSS719

DQ821

DQ923

VSS925

DQS#127

DQS129

VSS1131

DQ1033

DQ1135

VSS1337

DQ1639

DQ1741

VSS1543

DQS#245

DQS247

VSS1849

DQ1851

DQ1953

VSS2055

DQ2457

DQ2559

VSS2261

DM363

VSS2365

DQ2667

DQ2769

VSS2571

VDD587

A889

CKE073

VDD175

NC177

BA279

VDD381

A591

VDD793

A395

A197

VDD999

CK0101

A10/AP107

BA0109

VDD13111

A13119

NCTEST125

VSS27127

DQ32129

DQ33131

VSS29133

DQS#4135

DQS4137

VSS32139

DQ34141

DQ35143

VSS34145

DQ40147

DQ41149

VSS36151

DM5153

VSS37155

DQ42157

DQ43159

VSS39161

DQ48163

DQ49165

VSS41167

DQS#6169

DQS6171

VSS44173

DQ50175

DQ51177

VSS46179

DQ56181

DQ57183

VSS48185

DM7187

VSS49189

DQ58191

DQ59193

VSS51195

SA0197

VDDSPD199

SA1201

VTT1203

G1205

Trang 12

SB_CLK_DDR0DDR_B_ODT0

DIMM_DRAMRST#

DDR_B_CKE0SB_CLK_DDR#0

DDR_B_MA2

DDR_B_MA14

DDR_B_MA5DDR_B_MA3

DDR_B_MA15

DDR_B_MA1

DDR_B_MA12

DDR_B_BS0

DIMM_DRAMRST#

DDR_B_CKE0DDR_B_ODT0SB_CLK_DDR#0SB_CLK_DDR0

DDR_B_D15DDR_B_D11

DDR_B_CKE0SB_CLK_DDR#0SB_CLK_DDR0DDR_B_ODT0

DDR_B_MA7DDR_B_MA9

DDR_B_MA0

DDR_B_MA3

DDR_B_MA4DDR_B_MA2

DDR_B_MA14

DDR_B_MA12

DDR_B_MA1

DDR_B_MA6DDR_B_MA3

DDR_B_MA15

DDR_B_MA1

DDR_B_MA12

DDR_B_MA8DDR_B_MA10

DDR_B_DQS0DDR_B_DQS#0

DDR_B_D49

DDR_B_D53DDR_B_D55DDR_B_D51DDR_B_D48

DDR_B_MA7

SB_CLK_DDR#0SB_CLK_DDR0DDR_B_ODT0

DDR_B_MA14

DDR_B_MA3

DDR_B_MA4DDR_B_MA2

DDR_B_MA12

DDR_B_ODT0

DDR_B_MA15DDR_B_MA1

DDR_B_MA0

DDR_B_MA14

DDR_B_MA11

DDR_B_MA4DDR_B_MA2

DDR_B_MA7DDR_B_MA9DDR_B_MA10DDR_B_MA6DDR_B_MA3

DDR_B_MA13

DDR_B_MA15

DDR_B_MA1

DDR_B_MA12DDR_B_MA8

DDR_B_RAS#

DDR_B_DQS#2DDR_B_DQS2

DDR_B_D42

DDR_B_D47DDR_B_D40

DDR_B_D27DDR_B_D24

DDR_B_D29DDR_B_D31DDR_B_D28DDR_B_D25

DDR_B_D30

DIMM_DRAMRST#

DDR_B_CKE0SB_CLK_DDR#0SB_CLK_DDR0DDR_B_ODT0

DDR_B_D20DDR_B_D17

DDR_B_D22

DDR_B_ODT0SB_CLK_DDR#0SB_CLK_DDR0

DDR_B_MA7DDR_B_MA9

DDR_B_MA0

DDR_B_MA6DDR_B_MA3

DDR_B_MA15

DDR_B_MA1

DDR_B_MA12

DDR_B_MA8DDR_B_MA10

DDR_B_D34

DDR_B_MA15

DDR_B_MA14

DDR_B_MA11

DDR_B_MA4DDR_B_MA2

DDR_B_D5DDR_B_D1

DDR_B_D6DDR_B_D2DDR_B_DQS#6

DDR_B_CS0# <6>DDR_B_BS2 <6>DDR_B_BS1 <6>DDR_B_BS0 <6>

DIMM_DRAMRST# <11,6>

DDR_B_RAS# <6>DDR_B_CAS# <6>DDR_B_WE# <6>

+0.75VS

+VREF0+1.5V

+VREF1

+VREF1+VREF0

Title

Trang 13

1 1

SATA Port 0 is for HDD Connector

SATAICOMPO and SATACOMPI should be connected together then to R63.

SATA3ICOMPO and SATA3COMPI should be connected together then to R66.

Trace Impedance= 50-ohm Keep-out to other Signals, especially to CLK= 15-mil

Both JCMOS1 and JME2 should

be placed close to JDIMM1

INTVRMEN(Internal Voltage Regulator Enable) for DcpSus well

H: Integrated VRM enable L: Integrated VRM disable

*

32.768 for Real Time Clock

for HDA_SYNC Potential Leakage Concern

On-Die PLL Voltage Regulator Voltage Select

for VccVRM

H: 1.5V for VccVRM (for Mobile platform)

L: 1.8V for VccVRM (for Desktop platform), weak internal pull low

*

follow design guide 2.0 to cancel series resistor

In accordance with design guide 2.0 page 274, if default boot destination is SPI, no external pull-up/-down resistors

on the board are necessary.

SATA1GP/GPIO19 (BBS0) GTN1#/GPIO51 (BBS1)

Routing Reserved LPC SPI Reserved

1 1

0

Boot BIOS Destination Selection

keep R still be stuff for safety SMT, then check

if it is okay to remove or not

*

8MB SPI ROM for System BIOS

20mil 20mil

20mil

PCH

SATA Port 0 is for SSD

←On Board DRAM Flag

Swichable Graphic Supported

Check with SW if this selection is still required

YES

Low

placeholder for U19 is just reserved as back-up

not be shown on mask layer

SERIRQ

PCH_GPIO19

SATA_COMP

RBIAS_SATA3SATA3_COMP

HDA_BITCLK_PCHHDA_RST_PCH#

HDA_SDOUT_PCHHDA_SYNC_PCH_R

PCH_GPIO23

PCH_RTCRST#

PCH_SRTCRST#

PCH_INTVRMENSM_INTRUDER#

PCH_RTCX1PCH_RTCX2

HDA_SYNC_PCHHDA_SYNC_PCH

PCH_SPI_CS0#

PCH_SPI_MISO_1SPI_WP1#

PCH_SPI_CS1#

SPI_WP2#

SPI_HOLD2#

PCH_SPI_CLK_2PCH_SPI_MISO_2

PCH_SPI_MOSI_2

PCH_SATALED#

SERIRQ

PCH_GPIO21PCH_SATALED#

PCH_GPIO21

PCH_SPI_MISO_1PCH_SPI_MOSI_2

PCH_SPI_MOSI_1SPI_HOLD1#

PCH_SPI_CLK_1

PCH_SPI_MISOPCH_SPI_MOSI

+RTCVCC+RTCVCC

+3VS

Title

Y132.768K 12.5PF 1TJF125DP1A000D

LBSS138LT1G_SOT-23-3Q2

13

DO(IO1)2

/WP(IO2)3

/CS1

@

JME2SHORT PADS

@

R27510K_0402_5%

C1670.1U_0402_16V4ZC1670.1U_0402_16V4Z1

2

C1691U_0603_10V6KC1691U_0603_10V6K

@

JCMOS1SHORT PADS

@R27610K_0402_5%

R641M_0402_5%

W25Q64FVSSIQ_SO8

GND4

DO(IO1)2/WP(IO2)3

/CS1

RTCX2C20

INTVRMENC17INTRUDER#

K22

HDA_BCLKN34

HDA_SYNCL34

HDA_RST#

K34

HDA_SDIN0E34

HDA_SDIN1G34

HDA_SDIN2C34

HDA_SDOA36

HDA_DOCK_EN# / GPIO33C36

HDA_DOCK_RST# / GPIO13N32

SPI_MISOU3

JTAG_TCKJ3

JTAG_TMSH7

JTAG_TDIK5

JTAG_TDOH1

SPKRT10

Trang 14

Directly to WLAN on JMINI1

for S3 Power Reduction

1 Thermal Sensor for DRAM

2 Thermal Sensor for VRAM

3 dGPU

4 EC

1 SO-DIMM

2 Click-Pad Below items had been assigned to function field 2.3, which is for DRAM

Card Reader on D/B

Mini-Card for WiFi

Card Reader

NOT used in Full Clock Integration mode

CLKIN_GND1_P (BG30) and CLKIN_GND1_N (BJ30) can share the same PD resistor <Design Guide 2.0 Page 395>

blocking circuit, for dGPU SRC request

PCH_SML1CLKPCH_SML1DATA

XCLK_RCOMP

CLK_CPU_DMICLK_CPU_DMI#

PCH_GPIO46

PCIE_PTX_DRX_N2PCIE_PRX_DTX_N2

PCIE_PTX_DRX_P2

MINI1_CLKREQ#

PCH_GPIO45

XTAL25_OUTXTAL25_IN

RST_GATE#

PCH_SML1CLKPCH_SML1DATA

EC_SMB_CK2EC_SMB_DA2

CLKIN_GND1#

CLKIN_GND1PCH_GPIO47

PCH_SMBCLK

CLK_BUF_CPU_DMI#

CLK_BUF_CPU_DMI

CLK_BUF_DREF_96MCLK_BUF_DREF_96M#

CLK_BUF_PCIE_SATACLK_BUF_PCIE_SATA#

PCH_GPIO44

PCH_GPIO29

CARD_CLKREQ#

PCIE_PTX_DRX_N3PCIE_PRX_DTX_N3

PCIECLKRQ3#

CLK_PCI_LPBACKPEG_CLKREQ#_R

PCH_GPIO46PCH_GPIO74

PCH_GPIO47

PCH_GPIO73

PCH_GPIO20

PCH_SMBDATAPCH_SML1CLKPCH_SMBCLK

dGPU@

R8810K_0402_5%

Y2

25MHZ_10PF_7V25000014

GND233

GND4

R8590.9_0402_1%

dGPU@

D S

Q41LBSS138LT1G_SOT-23-3

Q3BDMN66D0LDW-7_SOT363-6

PERN2BE34PERP2BF34

PERN3BG36PERP3BJ36

PERN4BF36PERP4BE36

PERN5BG37PERP5BH37

PERN6BJ38PERP6BG38

PERN7BG40PERP7BJ40

PERN8BE38PERP8BC38

PETN1AV32PETP1AU32

PETN2BB32PETP2AY32

PETN3AV34PETP3AU34

PETN4AY34PETP4BB34

PETN5AY36PETP5BB36

PETN6AU36PETP6AV36

PETN7AY40PETP7BB40

PETN8AW38PETP8AY38

CLKOUT_PCIE0NY40

CLKOUT_PCIE0PY39

CLKOUT_PCIE1NAB49

CLKOUT_PCIE1PAB47

CLKOUT_PCIE2NAA48

CLKOUT_PCIE2PAA47

CLKOUT_PCIE3NY37

CLKOUT_PCIE3PY36

CLKOUT_PCIE4NY43

CLKOUT_PCIE4PY45

CLKOUT_PCIE5NV45

CLKOUT_PCIE5PV46

PCIECLKRQ1# / GPIO18M1

PCIECLKRQ2# / GPIO20V10

PCIECLKRQ3# / GPIO25A8

PCIECLKRQ4# / GPIO26L12

PCIECLKRQ5# / GPIO44L14

CLKOUT_PEG_B_P

AB42

CLKOUT_PCIE6NV40

CLKOUT_PCIE6PV42

PCIECLKRQ7# / GPIO46K12

CLKOUT_PCIE7NV38

CLKOUT_PCIE7PV37

CLKOUT_BCLK0_N / CLKOUT_PCIE8NAK14

CLKOUT_BCLK0_P / CLKOUT_PCIE8PAK13

R804.7K_0402_5%

R8610K_0402_5%

UMAO@

R8610K_0402_5%

UMAO@

R814.7K_0402_5%

Trang 15

1 1

Let DPWROK connect to RSMRST# since DS3 is not supported

Ball BJ24 and Ball BG25 should be short together then

be connected to R94, no longer then 500-mil.

DSWODVREN - On Die DSW VR Enable

FDI_LSYNC1FDI_LSYNC0

FDI_CTX_PRX_N0FDI_CTX_PRX_N2FDI_CTX_PRX_N4FDI_CTX_PRX_N6

FDI_CTX_PRX_P0FDI_CTX_PRX_P2FDI_CTX_PRX_P4FDI_CTX_PRX_P6

H_PM_SYNC

PCH_PWROKPCH_PWROK PCH_APWROK

B2

R9810K_0402_5%

DMI0RXPBE24DMI1RXPBC20DMI2RXPBJ18DMI3RXPBJ20

DMI0TXNAW24DMI1TXNAW20DMI2TXNBB18DMI3TXNAV18

DMI0TXPAY24DMI1TXPAY20DMI2TXPAY18DMI3TXPAU18

DMI_ZCOMPBJ24

DMI_IRCOMPBG25

BATLOW# / GPIO72E10

PWROKL22

APWROKL10

DMI2RBIASBH21

RB751V-40_SOD323-2

Trang 16

If the LVDS interface is not implemented, all signals associated with the interface can be left as No Connects

The supply pins VCCTX_LVDS and VCCA_LVD can be connected to ground

Base on recommendation from TI, AC coupling capacitors should be placed close to transmitt device

CRT_IREF

INVTPWMENBKL

PCH_DPB_HPDPCH_DPB_N0PCH_DPB_N1PCH_DPB_P0PCH_DPB_P1PCH_DPB_N2PCH_DPB_P2PCH_DPB_N3PCH_DPB_P3

SDVO_SCLKSDVO_SDATAPCH_ENVDD

PCH_DPD_N2PCH_DPD_N3

PCH_DPD_N2_CPCH_DPD_N3_C

PCH_DPD_N0PCH_DPD_N1

PCH_DPD_AUX_NPCH_DPD_AUX_PPCH_DPD_HPD

PCH_DDPD_CTRLCLKPCH_DDPD_CTRLDATA

R1012.2K_0402_5%

L_CTRL_CLKT45L_CTRL_DATAP39L_DDC_CLKT40L_DDC_DATAK47

L_VDD_ENM45

LVDSA_CLK#

AK39LVDSA_CLKAK40

LVDSA_DATA#0AN48

LVDSA_DATA#1AM47

LVDSA_DATA#2AK47

LVDSA_DATA#3AJ48

LVDSA_DATA0AN47LVDSA_DATA1AM49LVDSA_DATA2AK49LVDSA_DATA3AJ47

LVDSB_CLK#

AF40LVDSB_CLKAF39

LVDSB_DATA#0AH45

LVDSB_DATA#1AH47

LVDSB_DATA#2AF49

LVDSB_DATA#3AF45

LVDSB_DATA0AH43

LVD_VREFHAE48LVD_VREFLAE47

LVD_IBGAF37LVD_VBGAF36

CRT_DDC_CLKT39

CRT_DDC_DATAM40

CRT_GREENP49

CRT_HSYNCM47

CRT_IRTNT42

CRT_REDT49

CRT_VSYNCM49

DAC_IREFT43

Trang 17

Connect USBRBIAS and USBRBIAS# (impedance= 50-ohm single-end) together first, then connect to R158 from USBRBIAS#

(no longer than 500-mil) Keep-out 15-mil to other signals

CR CPU PD

PU, Set to 1 DMI,FDI Termination Voltage DF_TVS

USB30 External Port (Far Away from End-User) USB30 External Port (Close to End-User) Docking Port

Default for iRST supported

In accordance with design guide 2.0 page 274, if default

boot destination is SPI, no external pull-up/-down resistors

on the board are necessary.

SATA1GP/GPIO19 (BBS0) GTN1#/GPIO51 (BBS1)

ALL Unused GPIO will be set asto GPO,

and PU/PD resistors are only stuff for first version

ALL Unused GPIO will be set asto GPO, and PU/PD resistors are only stuff for first version

need to set GPIO50 and GPIO54 as GPO to reduce external PU resistors

CLK_PCI0

CLK_PCI3

USB20_P0USB20_N0

PCH_GPIO14

USB_OC4#

PCH_GPIO9PCH_GPIO10PCH_GPIO42USB_OC1#

DF_TVS

PCH_GPIO2

USB20_N8USB20_P8

USB20_N10

USB20_N1USB20_P1

PCH_GPIO50

PCH_GPIO5

PCH_USB3_TX3_P_C

USB20_P9USB20_N9

USB20_P11USB20_P12

PLT_RST#

iRST_RST#_R

CLK_PCI2

PCH_GPIO14PCH_GPIO9PCH_GPIO41PCH_GPIO42PCH_GPIO73PCH_GPIO57

PCH_GPIO5PCH_GPIO55

PCH_GPIO51

PCH_GPIO2

PCH_GPIO72

PCH_GPIO53PCH_GPIO3

+3VS+3VS

Title

B2

dGPU@

R113100K_0402_5%

R1042.2K_0402_5%

K38PIRQC#

H38PIRQD#

G38

REQ1# / GPIO50C46

REQ2# / GPIO52C44

REQ3# / GPIO54E40

GNT1# / GPIO51D47

GNT2# / GPIO53E42

GNT3# / GPIO55F46

PIRQE# / GPIO2G42

PIRQF# / GPIO3G40

PIRQG# / GPIO4C42

PIRQH# / GPIO5D44

TP6AH38TP7AH37TP8AK43TP9AK45

TP16Y13TP17K24TP18L24TP19AB46TP20AB45

TP21B21TP22M20TP23AY16

TP25BE28TP26BC30TP27BE32TP28BJ32TP29BC28TP30BE30TP31BF32TP32BG32TP33AV26TP34BB26TP35AU28TP36AY30TP37AU26TP38AY26TP39AV28TP40AW30

TP4BJ16TP5BG16

R112100K_0402_5%

Trang 18

1 1

Project Code GPIO69 GPIO70

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

1

ELPIDA(F-Die) 512MbX8

GPIO22 GPIO23

On Board DRAM Flag→

On-Die PLL Voltage Regulator for VccVRM

H: enable On-Die PLL Voltage Regulator

*

0 0 1 1

Being configured by ALT Group

For common BIOS code

PU resisotr for GPIO8 will be disabled after RSMRST# de-assertion.

NV Optimus Enable W/Optimus W/O Optimus High

Low

On Board DRAM Flag→

and PU/PD resistors are only reserved for first version

DDR3/DDR3L DDR3 DDR3L High Low

Check with SW if this selection is still required

GPIO71 is for GDDR3/GDDR5 selection.

PCH_GPIO39 is reserved only for first version

and PU/PD resistors are only stuff for first version

w/TPM

Currently, to be the same configuration as Sage, use GPIO69 and GPIO70 to define SKUs has TPM solution or not updated on 2013/01/15

PCH_GPIO39

PCH_GPIO37OPTIMUS_EN#

PCH_GPIO27

SNSR_HUB_PWR_GATE

mSATA_DET#

PCH_GPIO0

PCH_GPIO69 PCH_GPIO70PCH_GPIO28

PCH_GPIO23 PCH_GPIO22PCH_GPIO39

R27210K_0402_5%

R12610K_0402_5%

R12810K_0402_5%

@

R12810K_0402_5%

@

R27710K_0402_5%

R13010K_0402_5%

@

R13010K_0402_5%

GPIO28P8GPIO24 / MEM_LEDE8

GPIO57D6

LAN_PHY_PWR_CTRL / GPIO12C4

VSS_NCTF_1A4

VSS_NCTF_2A44

VSS_NCTF_3A45

VSS_NCTF_4A46

VSS_NCTF_5A5

VSS_NCTF_6A6

VSS_NCTF_7B3

VSS_NCTF_8B47

VSS_NCTF_9BD1

VSS_NCTF_10BD49

VSS_NCTF_11BE1

VSS_NCTF_12BE49

TACH2 / GPIO6H36

TACH0 / GPIO17D40

TACH3 / GPIO7E38

SATA3GP / GPIO37M5

SATA5GP / GPIO49V3

SCLOCK / GPIO22T5

SLOAD / GPIO38N2

SDATAOUT0 / GPIO39M3

SDATAOUT1 / GPIO48V13

BMBUSY# / GPIO0T7

GPIO15G2

TACH1 / GPIO1A42

SATA2GP / GPIO36V8

STP_PCI# / GPIO34K1

GPIO35K4

SATA4GP / GPIO16U2

VSS_NCTF_14BF49

@R27810K_0402_5%

@

R13110K_0402_5%

@

R11810K_0402_5%

R11910K_0402_5%

@

R11910K_0402_5%

@ 1

R13310K_0402_5%

@

R13310K_0402_5%

@

R27310K_0402_5%

@R27310K_0402_5%

36

45

RP43

27

36

45

R12710K_0402_5%

@

R12710K_0402_5%

@

C4720.1U_0402_16V4Z

ESD@

12

Trang 19

Be close to ball AA23

Be close to ball AN21, AN16 and AN33

Be close to ball BH29

C96 should be shared with AU20, but should be close to AT20

share C96 with AT20

Be close to ball U48

0.178 3.3

1.73 1.05

0.075 1.05 0.075 1.05

3.799 1.05

0.002 1.05 0.047

1.8

0.01 3.3 1.05 0.803

0.01 3.3

0.05

1.05 1.05 0.095 0.075 1.05

0.001 3.3

V_PROC_IO V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB

Display DAC Analog Power This power is supplied by the core well.

Voltage Rail

VccCore VccDMI

1.05 0.002 Voltage S0 Iccmax Current(A)

Display PLL A power

VccIO VccASW VccSPI VccDSW3_3 VccDFTERN

VccSus3_3 VccSusHDA VccVRM VccCLKDMI

VccALVDS VccTX_LVDS

Display PLL B power Internal Logic Voltage DMI Voltage Core Well I/O buffers 1.05 V Supply for Intel Management Engine and Integrated LAN

3.3 V Supply for SPI Controller Logic 3.3v supply for Deep Sx well 1.8V power supply for DF_TVS RTC Battery Voltage Suspend Well I/O Buffer Voltage High Definition Audio Controller Suspend Voltage

VccVRM voltage supplies for

AC23VCCCORE[3]

AD21VCCCORE[4]

AD23VCCCORE[5]

AF21VCCCORE[6]

AF23VCCCORE[7]

AG21VCCCORE[8]

AG23VCCCORE[9]

AG24VCCCORE[10]

AG26VCCCORE[11]

AG27VCCCORE[12]

AG29VCCCORE[13]

AJ23VCCCORE[14]

AJ26VCCCORE[15]

VCCFDIPLLBG6

2

C2001U_0402_6.3V6KC2001U_0402_6.3V6K1

2

C2030.1U_0402_16V7KC2030.1U_0402_16V7K1

2

C19310U_0603_6.3V6MC19310U_0603_6.3V6M1

L1FBMA-L11-201209-221LMA30T_0805

12

Trang 20

Check sequence between VCC5REF_SUS and VCCSUS3_3

remove R479 if no any sequence issue

+VCCAPLL_CPY_PCH+PCH_VCCDSW+VCCACLK

+1.05VM_VCCSUS

+1.05VS_VCCA_A_DPL+1.05VS_VCCA_B_DPL

+1.05VS_VTT

+3VALW_PCH +5VALW_PCH

+3VS +5VS

+1.05VS_VTT+1.05VS_VTT

+1.05VS_VTT

+3VALW_PCH+1.05VS_VTT

+5VALW_PCH+5VALW

Title

D4RB751V-40_SOD323-2

C2081U_0402_6.3V6KC2081U_0402_6.3V6K1

Q39AO3419L_SOT23-3

13

2

U28

G5243T11U_SOT23-5U28

G5243T11U_SOT23-5

IN5

IN4

2

C2211U_0603_10V6KC2211U_0603_10V6K

2

C2090.1U_0402_16V7KC2090.1U_0402_16V7K1

@J16JUMP_43X39

@

11

C2120.1U_0402_16V7KC2120.1U_0402_16V7K1

R135100_0402_5%

T35PAD

@ T35PAD

Y49

VCCACLKAD49

DCPRTCN16

VCCASW[4]

AA26

VCCIO[9]

AF34VCCIO[7]

AF17

DCPSSTV16

AL29

VCCAPLLDMI2BH23

DCPSUS[2]

V19

VCCDSW3_3T16

@J17JUMP_43X39

@

11

2

C2221U_0402_6.3V6KC2221U_0402_6.3V6K1

R136100_0402_5%

Trang 21

AA2VSS[3]

AA3

VSS[5]

AA34VSS[6]

AB11VSS[7]

AB14VSS[8]

AB39VSS[9]

AB4VSS[10]

AB43VSS[11]

AB5VSS[12]

AB7VSS[13]

AC19VSS[14]

AC2VSS[15]

AC21VSS[16]

AC24VSS[17]

AC33VSS[18]

AC34VSS[19]

AC48VSS[20]

AD10VSS[21]

AD11VSS[22]

AD12VSS[23]

AD13VSS[24]

AD19VSS[25]

AD24VSS[26]

AD26VSS[27]

AD27VSS[28]

AD33VSS[29]

AD34VSS[30]

AD36VSS[31]

AD37

VSS[33]

AD39VSS[34]

AD4VSS[35]

AD40VSS[36]

AD42VSS[37]

AD43VSS[38]

AD45VSS[39]

AD46

VSS[43]

AF10VSS[44]

AF12

VSS[46]

AD16VSS[47]

AF16VSS[48]

AF19VSS[49]

AF24VSS[50]

AF26VSS[51]

AF27VSS[52]

AF29VSS[53]

AF31VSS[54]

AF38VSS[55]

AF4VSS[56]

AF42VSS[57]

AF46

VSS[59]

AF7VSS[60]

AF8VSS[61]

AG19VSS[62]

AG2VSS[63]

AG31VSS[64]

AG48VSS[65]

AH11VSS[66]

AH3VSS[67]

AH36VSS[68]

AH39VSS[69]

AH40VSS[70]

AH42VSS[71]

AH46VSS[72]

AH7VSS[73]

AJ19

VSS[76]

AJ33VSS[77]

AJ34VSS[78]

AK12VSS[79]

AY42VSS[161]

AY46VSS[162]

AY8VSS[163]

B11VSS[164]

B15VSS[165]

B19VSS[166]

B23VSS[167]

B27VSS[168]

B31VSS[169]

B35VSS[170]

B39VSS[171]

B7

VSS[173]

BB12VSS[174]

BB16VSS[175]

BB20VSS[176]

BB22VSS[177]

BB24VSS[178]

BB28VSS[179]

BB30VSS[180]

BB38VSS[181]

BB4VSS[182]

BB46VSS[183]

BC14VSS[184]

BC18VSS[185]

BC2VSS[186]

BC22VSS[187]

BC26VSS[188]

BC32VSS[189]

BC34VSS[190]

BC36VSS[191]

BC40VSS[192]

BC42VSS[193]

BC48VSS[194]

BD46VSS[195]

BD5VSS[196]

BE22VSS[197]

BE26VSS[198]

BE40VSS[199]

BF10VSS[200]

BF12VSS[201]

BF16VSS[202]

BF20VSS[203]

BF22VSS[204]

BF24VSS[205]

BF26VSS[206]

BF28VSS[207]

BD3VSS[208]

BF30VSS[209]

BF38VSS[210]

BF40VSS[211]

BF8VSS[212]

BG17VSS[213]

BG21VSS[214]

BG33VSS[215]

BG44VSS[216]

BG8VSS[217]

BH11VSS[218]

BH15VSS[219]

BH17VSS[220]

BH19

VSS[222]

BH27VSS[223]

BH31VSS[224]

BH33VSS[225]

BH35VSS[226]

BH39VSS[227]

BH43VSS[228]

BH7VSS[229]

D3VSS[230]

D12VSS[231]

D16VSS[232]

D18VSS[233]

D22VSS[234]

D24VSS[235]

D26VSS[236]

D30VSS[237]

D38VSS[240]

D42VSS[241]

D8VSS[242]

E18VSS[243]

E26VSS[244]

G18VSS[245]

G20VSS[246]

G26VSS[247]

G28VSS[248]

G36VSS[249]

G48VSS[250]

H12VSS[251]

H24VSS[254]

H26VSS[255]

H30VSS[256]

H32VSS[257]

H34VSS[258]

Trang 22

PSI

FRM_CLK

GPIO18 GPIO19

GPIO20 GPIO21

I

I I I

O HPD_C

GPIO12 GPIO13 GPIO14

I O

I HPD_A PWR_LEVEL

HPD_D HPD_E HPD_F or HPD_B

Reserved Reserved

Place Under AE8,AD7

PWM_VID

150mA SM010028480 1500ma 180ohm@100mhz DCR 0.18

O

GPIO20,21 N14P-GV/-GV2/N14M-LP/GS = availbleN14M-GE/GL = NC

O

O O

OVERT

FB_CLAMP_MON GPIO0

GPIO5

GPIO1

GPIO2 GPIO3

GPIO4

GPIO6

GPIO7 GPIO8

GPIO9 GPIO10

GPIO11

NV DG PLL_VDD 0.1Ux1, Under GPU 22Ux1,30ohm(ESR0.05)x1, Near GPU

NV DG SP_PLLVDD,VID_PLLVDD 0.1Ux2 Under GPU 4.7Ux1,22Ux1, Near GPU 180ohm(ESR0.2)x1

LCD_BLEN Reserved FB_CLAMP_TGL_REQ

O

I/O O

16mils 16mils

GPU P/N : SA00005W200 S IC N14P-GT-A2 FCBGA 908P GPU Use N13P symbol.

NV FAE comment : 1107

XTALOUT

GPIO9_ALERTGPIO8_OVERT

PEX_TSTCLK_OUT+

DACA_VDD

I2CS_SCL

I2CS_SDA+GPU_PLLVDD

ACIN_BUF

PEX_TERMP

PEX_TSTCLK_OUT-XTALINXTAL_OUTBUFFXTAL_SSINXTALOUT

I2CS_SCL

I2CB_SCL

VGA_DDC_CLKVGA_DDC_DATAI2CB_SDAVGA_LCD_CLKVGA_LCD_DATA

I2CS_SDA

+PLLVDD

PSIDGPU_VIDGC6_TGL_REQ#

ACIN_BUF

GPIO8_OVERTGPIO9_ALERT

+GPU_PLLVDDGC6_CLAMP_MON

VGA_LCD_CLKVGA_LCD_DATAVGA_DDC_CLKVGA_DDC_DATA

GC6_TGL_REQ#

GPIO9_ALERT_GATE

GPIO8_OVERTGPIO9_ALERTGPIO9_ALERT_GATEACIN_BUF

XTAL_SSIN XTAL_OUTBUFF

GPU_CLAMP_ENGC6_CLAMP_MON

EC_SMB_DA2 <14,27,37>EC_SMB_CK2 <14,27,37>

+3VSDGPU

+3VSDGPU+3VSDGPU

+3VSDGPU

Title

N14P PEG 1/9

CustomDate of EOP

Compal Electronics, Inc.

Title

N14P PEG 1/9

CustomDate of EOP

Title

N14P PEG 1/9

CustomDate of EOP

Y327MHZ_10PF_7V27000050

dGPU@

D5RB751V-40_SOD323-2

dGPU@

12

dGPU@

61

dGPU@

61

GC6@

R3601K_0402_5%

GC6@

R15410K_0402_5%

GC6@

R15410K_0402_5%

GC6@

C2420.1U_0402_16V4Z

dGPU@

C2420.1U_0402_16V4Z

dGPU@

12

dGPU@

34

R14610K_0402_5%

dGPU@R14610K_0402_5%

dGPU@

R14710K_0402_5%

dGPU@R14710K_0402_5%

dGPU@

C24610P_0402_50V8J

dGPU@

C24122U_0603_6.3V6M

dGPU@

1

2

C24710P_0402_50V8J

dGPU@

C24710P_0402_50V8J

dGPU@

1

2

R13810K_0402_5%

dGPU@

R13810K_0402_5%

dGPU@

C24522U_0603_6.3V6M

dGPU@

1

2

RP4610K_8P4R_5%

dGPU@

RP4610K_8P4R_5%

dGPU@

18273645

Q47LBSS138LT1G_SOT-23-3

GC6@

13

C2444.7U_0603_6.3V6K

dGPU@

C2444.7U_0603_6.3V6K

2

R15010K_0402_5%

GC6@

R15010K_0402_5%

GC6@

C2430.1U_0402_16V4Z

dGPU@

C2430.1U_0402_16V4Z

dGPU@

12

R1550_0402_5%

NGC6@

R1550_0402_5%

NGC6@

Trang 23

30ohm@100Mhz(ESR0.01ohm) x1 Near GPU

Place Near GPU

GPU P/N : SA00005W200 S IC N14P-GT-A2 FCBGA 908P GPU Use N13P symbol.

DQMA0DQMA2DQMA4DQMA6

DQSA3DQSA1

DQSA4DQSA6

MDA56

MDA62MDA59MDA61MDA58MDA60

MDA45

MDA57

MDA44MDA40

MDA47MDA41

MDA46MDA42

MDA33MDA35

MDA43

MDA28

MDA38MDA34

MDA39MDA36

MDA20

MDA23

MDA30MDA32

MDA21

MDA25MDA22

MDA26MDA24

MDA29

MDA2

MDA15MDA13

MDA16MDA11

MDA5MDA7

MDA14

MDA19

MDA6

MDA17MDA4

CMDA2

CMDA9

CMDA22CMDA16CMDA3

CMDA28

CMDA10

CMDA23CMDA17

MDC56

MDC62MDC59MDC61MDC58MDC60

MDC45

MDC57

MDC44MDC40

MDC47MDC41

MDC46MDC42

MDC33MDC35

MDC43

MDC28

MDC38MDC34

MDC39MDC36

MDC20

MDC23

MDC30MDC32

MDC21

MDC25MDC22

MDC26MDC24

MDC29

MDC15MDC13

MDC27MDC18

MDC9

MDC12MDC3

MDC16MDC11

MDC5MDC7

MDC14

MDC19

MDC6

MDC17MDC4

DQSC0DQSC3DQSC5DQSC7

CMDC2

CMDC9

CMDC22CMDC16CMDC3

CMDC28

CMDC10

CMDC23CMDC17

FBA_WCK23FBA_WCK23#

FBA_WCK45#

FBA_WCK67FBA_WCK67#

FBA_WCK45

FBB_WCK45#

FBB_WCK67FBB_WCK67#

FBB_WCK45

FBB_WCK01FBB_WCK01#

FBB_WCK23FBB_WCK23#

Title

dGPU@

C2490.1U_0402_16V4Z

dGPU@

1

2

C2500.1U_0402_16V4Z

dGPU@

C2500.1U_0402_16V4Z

dGPU@

C24822U_0805_6.3V6M

dGPU@

1

2

L7BLM18PG330SN1_2P

dGPU@

L7BLM18PG330SN1_2P

dGPU@

C2510.1U_0402_16V4Z

dGPU@

1

2

Trang 24

MULTI LEVEL STRAPS

GPU P/N : SA00005W200 S IC N14P-GT-A2 FCBGA 908P GPU

Pull-up 1000 10K

15K 20K

Pull-down

1001

24.9K 30.1K

0000

34.8K 45.3K

1010

0001

1011 1100 1101

0010

1110 1111

0011 0100 0101 0110 0111

R

PU 45KR

PD 5K

Memory Size

For N14P-GT-A2(QS) strap table

Device ID : 0xFE4

R

PD 25KR

PD 5KR

PD 45K

R

PU 5K

24.9K Strap 0x4 ROM_SI GDDR5

Hynix Vendor

R

PD 15KHynix

STRAP3 STRAP2

ROM_SI ROM_SCLK STRAP4

PCI_DEV[4],SUB_VENDOR, PCI_DEV[5],PEX_PLL_EN_TERM

PEG_SPEED_CHANGE_GEN3, PEX_MAX_SPEED,DP_PLLVDD33V STRAP1

ROM_SCLKROM_SIROM_SO

ROM_SCLKROM_CS#

ROM_SOROM_SI

JTAG_RSTJTAG_TCK

STRAP0STRAP2MULTI_STRAP_REF0_GNDTESTMODE

STRAP3

STRAP0

STRAP3

JTAG_TDIJTAG_TDO

VSSSENSE_VGA_RVCCSENSE_VGA_R

TESTMODEJTAG_RSTDACA_VDD

dGPU@

R16145.3K_0402_1%

dGPU@

R1724.99K_0402_1%

dGPU@

R1724.99K_0402_1%

dGPU@

R1704.99K_0402_1%

dGPU@

R1704.99K_0402_1%

@

R17530K_0402_1%

PAD @

R1664.99K_0402_1%

@

R1664.99K_0402_1%

@

R1624.99K_0402_1%

@

R1624.99K_0402_1%

@

R16320K_0402_1%

@

T40PADT40@

PAD @

R16510K_0402_1%

@

R16510K_0402_1%

@

R17124.9K_0402_1%

dGPU@

R17124.9K_0402_1%

dGPU@

R1674.99K_0402_1%

dGPU@

R17345.3K_0402_1%

dGPU@

R17434.8K_0402_1%

HYNAFR@

R17434.8K_0402_1%

@

R1684.99K_0402_1%

@

R1644.99K_0402_1%

@

R1644.99K_0402_1%

@

R17615K_0402_1%

dGPU@

R17615K_0402_1%

dGPU@

RP4710K_8P4R_5%

dGPU@

RP4710K_8P4R_5%

dGPU@

18273645

T39PADT39@

@

R1694.99K_0402_1%

@

Trang 25

Under GPU (one per pin)

Near GPU Under GPU

Under GPU Under GPU

if use N14M-GE/GL,use bead 120ohm@100MHz(ESR=0.18)

NV 14x DG FBVDDQ(GDDR5) GB4-128

0.1Ux4,1Ux4 Under GPU

4.7Ux4,10Ux2,22Ux2 Near GPU

NV DG PEX_IOVVD/Q combined 1Ux4 Under GPU

4.7Ux2 Near GPU 10Ux4,22Ux4 Midway GPU & Power supply

Midway GPU & Power supply

PEX_SVDD/PLL_HVDD connect to NV3V3 0.1Ux1,4.7Ux2 Near GPU

NV DG PEX_PLLVDD 0.1Ux1 Under GPU 1Ux1,4.7Ux1 Near GPU

NV DG VDD33/3VSMISC 0.1Ux3 Under GPU 1Per pin 1Ux1,4.7Ux1 Near GPU

Near GPU Near GPU

+IFPAB_IOVDD

+IFPEF_PLLVDD+IFPEF_IOVDD

+IFPAB_PLLVDD

+IFPC_IOVDD+IFPC_PLLVDD

+IFPD_IOVDD+IFPD_PLLVDD

FB_VDDQ_SENSE

FB_GND_SENSE

+VDD33

+IFPD_IOVDD+IFPD_PLLVDD+IFPC_IOVDD+IFPC_PLLVDD

+IFPEF_IOVDD+IFPEF_PLLVDD+IFPAB_PLLVDD+IFPAB_IOVDD

+1.05VSDGPU

+1.05VSDGPU+1.5VSDGPU

dGPU@

C2821U_0402_6.3V6K

dGPU@

C2810.1U_0402_16V4Z

dGPU@

1

2

C2834.7U_0603_6.3V6K

dGPU@

C2834.7U_0603_6.3V6K

dGPU@

R1860_0603_5%

Trang 26

Trang 27

CMD4 CMD3 CMD2

CMD6 CMD5

CMD10 CMD9 CMD8 CMD7

CMD19 CMD18 CMD17 CMD16 CMD15

CMD22 CMD21 CMD20

CMD28 CMD29 CMD30

ABI#

A4_BA2

RAS#

A7_A8 A5_BA1

CAS#

A6_A11

A2_BA0 CS#

A1_A9

A3_BA3

A12_RFU A0_A10

A6_A11 ABI# WE# CKE#

CKE# A5_BA1

Near ball Near ball

S IC W83L771AWG-2 TSSOP 8P SENSOR

External VRAM Thermal Sensor

BYTE1 BYTE2

BYTE3

BOT / M501 TOP / M3

DQMA0DQMA2

FBA_WCK01FBA_WCK01#

+FBA_VREFD1+FBA_VREFC1

+FBA_VREFD1

CLKA0

MDA7MDA1

MDA5MDA3MDA6MDA0

CMDA10CMDA9

CMDA4

CMDA6CMDA1

CMDA14

+FBA_VREFD1

DQSA2DQSA0MDA[15 0]

MDA12MDA9MDA16

MDA18

MDA22

MDA17MDA20

MDA30MDA26MDA24

MDA28MDA31DQMA3

DQMA1

DQSA1DQSA3

FBA_WCK01#

FBA_WCK01FBA_WCK23FBA_WCK23#

DQSA[3 0]

CMDA14

CMDA9CMDA11CMDA6CMDA10CMDA4CMDA1

CMDA8CMDA15CMDA5CMDA12CMDA0

+1.5VSDGPU

Title

Issued Date Deciphered Date

Ezel_CX MB_LA-A001P N14P GDDR5 6/9

Custom

1.0Title

Security Classification Compal Secret Data

Custom

1.0Title

C2950.01U_0402_16V7KdGPU@

dGPU@

R1961K_0402_1%

MF=0 MF=1 MF=1 MF=0

U5

H5GQ1H24AFR-T2L_BGA170SA00004GD50 @

170-BALLSGRAM GDDR5

MF=0 MF=1 MF=1 MF=0

U5

S

Q82N7002K_SOT23-3dGPU@

GD

S

R202549_0402_1%dGPU@

C3080.01U_0402_16V7KdGPU@

C3090.1U_0402_16V4ZdGPU@

1 2

R2071.33K_0402_1%

dGPU@

R2071.33K_0402_1%

dGPU@

R2041.33K_0402_1%

R205549_0402_1%dGPU@

SA00003PU00U24

W83L771AWG-2 TSSOP8PdGPU@

MF=0 MF=1 MF=1 MF=0

U6

H5GQ1H24AFR-T2L_BGA170SA00004GD50@

170-BALLSGRAM GDDR5

MF=0 MF=1 MF=1 MF=0

U6

dGPU@

R1971K_0402_1%

dGPU@

C3070.01U_0402_16V7KdGPU@

C3020.01U_0402_16V7KdGPU@

Trang 28

CKE#

RESET#

CLKA1CLKA1#

CMDA20

CMDA22CMDA17

CMDA29CMDA31

CMDA19

CMDA24CMDA30

CLKA1

MDA56

MDA62MDA59MDA61MDA58MDA60MDA57

MDA45MDA40

MDA47MDA41

MDA46MDA42

MDA35

MDA38MDA34

MDA39MDA36MDA32

MDA52

MDA55MDA50MDA48

MDA53

FBA_WCK67#

FBA_WCK67

FBA_WCK45FBA_WCK45#

DQSA6DQSA4

DQMA4DQMA6

FBA_WCK45FBA_WCK45#

FBA_WCK67#

FBA_WCK67

CMDA19CMDA18

CMDA26CMDA22CMDA25

CMDA24CMDA21CMDA16

DQSA7DQSA5

DQMA7DQMA5

+1.5VSDGPU

Title

dGPU@

R2191.33K_0402_1%

dGPU@

GD

SQ92N7002K_SOT23-3

dGPU@

GD

SQ92N7002K_SOT23-3

MF=0 MF=1 MF=1 MF=0U8

H5GQ1H24AFR-T2L_BGA170

@SA00004GD50

170-BALLSGRAM GDDR5

@SA00004GD50

G1

VSS

B10T5 VSSVSS

L5 VSS

G5B5 VSSVSS

dGPU@

R217549_0402_1%

dGPU@

R220549_0402_1%

dGPU@

R220549_0402_1%

dGPU@

R2111K_0402_1%

dGPU@

R2221.33K_0402_1%

dGPU@

C3210.01U_0402_16V7K

dGPU@

C3220.01U_0402_16V7K

dGPU@

C3220.01U_0402_16V7K

dGPU@

C3290.01U_0402_16V7K

dGPU@

170-BALLSGRAM GDDR5

@SA00004GD50

170-BALLSGRAM GDDR5

@SA00004GD50

G1

VSS

B10T5 VSSVSS

dGPU@

C3300.01U_0402_16V7K

dGPU@

R2121K_0402_1%

Trang 29

CMD4 CMD3 CMD2

CMD6 CMD5

CMD22 CMD21 CMD20

CMD28 CMD29 CMD30

ABI#

A4_BA2

RAS#

A7_A8 A5_BA1

CAS#

A6_A11

A2_BA0 CS#

A1_A9

A3_BA3

A12_RFU A0_A10

A6_A11 ABI# WE# CKE#

CKE# A5_BA1

Near ball Near ball

BYTE3

BOT / M504 TOP / M1

CKE#

RESET#

DQMC0DQMC2

FBB_WCK01FBB_WCK01#

+FBB_VREFD1+FBB_VREFC1

+FBB_VREFD1

CLKC0

MDC7MDC1

MDC5MDC3MDC6MDC0

CLKC0#

+FBB_VREFC1

CLKC0CLKC0#

CMDC10CMDC9

CMDC4

CMDC6CMDC1

CMDC14

+FBB_VREFD1

DQSC2DQSC0MDC[15 0]

MDC12MDC9MDC16

MDC18

MDC22

MDC17MDC20

MDC30MDC26MDC24

MDC28MDC31DQMC3

DQMC1

DQSC1DQSC3

FBB_WCK01#

FBB_WCK01FBB_WCK23FBB_WCK23#

DQSC[3 0]

CMDC14

CMDC9CMDC11CMDC6CMDC10CMDC4CMDC1

CMDC8CMDC15CMDC5CMDC12CMDC0

Title

Custom

Date of EOP

1.0Title

Custom

Date of EOP

1.0Title

C3460.01U_0402_16V7KdGPU@

MF=0 MF=1 MF=1 MF=0

U9

170-BALLSGRAM GDDR5

MF=0 MF=1 MF=1 MF=0

U9

C3590.01U_0402_16V7KdGPU@

R233549_0402_1%dGPU@

C3580.01U_0402_16V7KdGPU@

dGPU@

R2381.33K_0402_1%

dGPU@

R2271K_0402_1%

dGPU@

R2271K_0402_1%

dGPU@

C3530.01U_0402_16V7KdGPU@

R2351.33K_0402_1%

dGPU@

R2351.33K_0402_1%

S

GD

S

2

R2281K_0402_1%

dGPU@

R2281K_0402_1%

R236549_0402_1%dGPU@

170-BALLSGRAM GDDR5

MF=0 MF=1 MF=1 MF=0

U10

170-BALLSGRAM GDDR5

MF=0 MF=1 MF=1 MF=0

U10

Trang 30

RESET#

CKE#

CLKC1CLKC1#

CMDC20

CMDC22CMDC17

CMDC29CMDC31

CMDC19

CMDC24CMDC30

CLKC1

MDC56

MDC62MDC59MDC61MDC58MDC60MDC57

MDC45MDC40

MDC47MDC41

MDC46MDC42

MDC35

MDC38MDC34

MDC39MDC36MDC32

MDC52

MDC55MDC50MDC48

MDC53

FBB_WCK67#

FBB_WCK67

FBB_WCK45FBB_WCK45#

DQSC6DQSC4

DQMC4DQMC6

FBB_WCK45FBB_WCK45#

FBB_WCK67#

FBB_WCK67

CMDC19CMDC18

CMDC26CMDC22CMDC25

CMDC24CMDC21CMDC16

DQSC7DQSC5

DQMC7DQMC5

+1.5VSDGPU

Title

dGPU@

C3810.01U_0402_16V7K

dGPU@

R2421K_0402_1%

dGPU@

R2421K_0402_1%

dGPU@

C3730.01U_0402_16V7K

SQ112N7002K_SOT23-3

dGPU@

GD

SQ112N7002K_SOT23-3

dGPU@

C3800.01U_0402_16V7K

@SA00004GD50

170-BALLSGRAM GDDR5

@SA00004GD50

G1

VSS

B10T5 VSSVSS

L5 VSS

G5B5 VSSVSS

@SA00004GD50

170-BALLSGRAM GDDR5

@SA00004GD50

G1

VSS

B10T5 VSSVSS

dGPU@

R2431K_0402_1%

dGPU@

R2531.33K_0402_1%

dGPU@

R2531.33K_0402_1%

dGPU@

C3720.01U_0402_16V7K

dGPU@

R2501.33K_0402_1%

dGPU@

R248549_0402_1%

Trang 31

Cost Reduced Level Shifter Topology

Change to short pad for experiment for the first PCB version , request by EMI

D9 should be as close as possible to JHDMI1

Pin Mapping for HDMI by Port B

TMDSB_DATA1 TMDSB_DATA1#

TMDSB_DATA0 TMDSB_DATA0#

TMDSB_CLK TMDSB_CLK#

NA NA HDMIB_HPD HDMIB_CTRLCLK HDMIB_CTRLDATA

HDMI_R_D1-HDMI_R_D2+

HDMI_R_D1+

HDMI_TX2-

HDMI_R_D2-HDMI_TX2+

HDMI_R_D0+

HDMI_R_CLK+

HDMI_R_D0- HDMI_CLK-

HDMI_R_CLK-HDMI_CLK+

HDMI_TX0+

HDMI_TX0- HDMI_TX1+

HDMI_TX1-HDMI_SDATA HDMI_SCLK

HDMI_SCLK

HDMI_GND

HDMI_HPD

HDMI_R_CLK+

HDMI_R_D2-HDMI_SCLK HDMI_SDATA HDMI_HPD

HDMI_SDATA

SDVO_SCLK SDVO_SDATA

HDMI_TX0+

HDMI_TX0- HDMI_CLK+

HDMI_CLK- HDMI_TX1+

HDMI_TX1-HDMI_TX2+

HDMI_TX2- HDMI_CLK+

HDMI_CLK- HDMI_TX1+

HDMI_TX1- HDMI_TX2+

HDMI_TX2- HDMI_TX0+

Q12A DMN66D0LDW-7_SOT363-6

3 4

Q13A DMN66D0LDW-7_SOT363-6

3 4

RP33 680_8P4R_5%

R263 20K_0402_5%

C399 0.1U_0402_16V7K C399 2 1 0.1U_0402_16V7K

U26

AP2330W-7_SC59-3 U26

AP2330W-7_SC59-3

IN 1

R259 @ 0_0402_5%

R259 1 @ 2 0_0402_5%

GSD

Q12B DMN66D0LDW-7_SOT363-6

GSD

2

RP34 680_8P4R_5%

D9 YSLC05CH_SOT23-3

XEMC@

SCA00000U10

D9 YSLC05CH_SOT23-3

C398 0.1U_0402_16V7K C398 2 1 0.1U_0402_16V7K

RP35 2.2K_0804_8P4R_5%

S D

6 1

C397 0.1U_0402_16V7K C397 2 1 0.1U_0402_16V7K

C402 0.1U_0402_16V7K C402 2 1 0.1U_0402_16V7K

C405 0.1U_0402_16V4Z

@

C405 0.1U_0402_16V4Z

@ 1

2

R261 1M_0402_5%

Trang 32

eDP PANEL Connector

For CMOS Camera

For Touch Screen For Sensor Hub

Purpose: no any increasement for cable's gauge

request from ESD need to put close to JSNSR1

after confirming, home key will not support wake-up function by Ezel_CX

EDP_TXN3_CEDP_TXN3

EDP_TXN2_CEDP_TXN2

EDP_TXP1_CEDP_TXP1

EDP_TXP0_CEDP_TXP0

INVTPWMBKOFF#

HK_INT#

HK_I2C_SDATAHK_I2C_SCLKUSB20_N10_R

USB20_N11TOUCH_PANEL_INT#

+LCDVDD+INVPWR_B+

+3VS

+3VALW+3VLP

EMI@C4101000P_0402_50V7K

C446

ESD@

100P_0402_50V8JC446

1

2

C424 1U_0402_16V7KC4241 2 1U_0402_16V7K

C418 1U_0402_16V7KC4181 2 1U_0402_16V7K

C423 1U_0402_16V7KC4231 2 1U_0402_16V7K

C417 1U_0402_16V7KC4171 2 1U_0402_16V7K

GD

SQ142N7002K_SOT23-3GD

SQ142N7002K_SOT23-3

EMI@

L12FBMA-L11-201209-221LMA30_2P

C420 1U_0402_16V7KC4201 2 1U_0402_16V7KC419 1U_0402_16V7KC4191 2 1U_0402_16V7K

R307 EMI@ 0_0402_5%

R3071 EMI@2 0_0402_5%

R298 0_0402_5%

R2981 2 0_0402_5%

Tiêu đề	Acer Aspire R7 571g Compal LA A001P Rev 1 0 Schematic
Trường học	Compal Electronics, Inc.
Chuyên ngành	Electronics Engineering
Thể loại	Engineering Drawing
Năm xuất bản	2013
Thành phố	Taipei

Định dạng
Số trang	64
Dung lượng	1,71 MB