Acer aspire e5 474g compal LA c611p rev 1 0 схема

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.. NEITHER THIS SHEET NOR THE INF

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2015.07.17 Rev: 1.0 LA-C611P

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Part Number Description

A4WAS_PCB_REV10

DAZ1DR00100 PCB A4W AS LA-C611P LS-C341P

DAX

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USB 2.0 conn x1

page 40

USB 3.0 conn x2

page 38

page 39

ENE KB9022

page 39 page 36

port 8

SATA CDROM Conn.

page 36

SATA HDD Conn

PCIe 1.0 2.5GT/s

page 20~28

port 1-4

Nvidia N16x with DDR3 x4

Title

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PCB Revision 0.1

0.3

EC AD3

0x00 - 0x0B 0x0C - 0x1C 0x1D - 0x26

BOM Structure Table

0x31 - 0x3B 0.691 V 0.702 V 0.713 V

0x3C - 0x46 0.807 V 0.819 V 0.831 V

0x47 - 0x54 0.978 V 0.992 V 1.006 V

0x55 - 0x64 1.169 V 1.185 V 1.200 V

ON +0.675VS_VTT DDR +0.675VS power rail for DDR terminator

+1.8VALW_PRIM +1.8V Always power rail

+1.35V_VDDQ

ON ON +VCC_CORE

Voltage Rails

+19V_VIN +19VB

Adapter power supply

AC or battery power rail for power circuit.

Processor IA Cores Power Rail

Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.

S0

ON ON

N/A

N/A Power Plane Description

+VCC_GT Processor Graphics Power Rails

S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

ON ON ON

ON

OFF OFF OFF

OFF OFF OFF OFF OFF LOW LOW LOW

LOW LOW LOW HIGH

HIGH HIGH

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power State

Board ID Table for AD channel

+VCC_SA System Agent power rail

SPI ROM 8M*1 8M_SINGLE@

BOM Option Table

VRAM BOM Select X76@/X7601@ ~

X7614@

Address(7 bit)

Device Write Address(8bit) Read

I2C Address Table

1DMIC@

DMIC*1

IOAC@

For Acer IOAC

No Acer IOAC NIOAC@

CPU Code PreES:QH7Y@

SR@/DR@

Single/Dual Rank

0xA0 0xA4

DIMM1

SOC_SMBCLK +3VS DIMM2

0x9E SOC_SML1CLK +3VS N16S-GT (VGA)

+1.0V_VCCSTU Sustain voltage for processor in Standby modes ON

+5V Always power rail

ON

ON +1.05VSDGPU +1.05VS power rail for GPU

OFF OFF OFF OFF OFFON

OFF OFF OFF OFF

S3 S4/S5

OFF

N/A N/A

N/A N/AOFF OFF OFFN/A N/A

OFF OFF

OFF OFF OFF OFF OFF OFF

OFF OFF

ON ONOFFONOFF OFF

ONOFFON ON*1OFFON

ON*1OFF

ES@

For ES Sampel Only

/

MP:SR2EU@, SR2EY@, SR2EZ@

Security Classification Compal Secret Data

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.0

Power Map

Custom

4 60 Thursday, July 16, 2015

A4WAS M/B LA-C611P

Title

Size Document Number Re v

1.0

Power Map

Custom

Title

Size Document Number Re v

1.0

Power Map

Custom

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tCPU09 Min : 1 ms

tCPU16 Min : 0 ns tCPU00 Min : 1 ms

tPLT05 Min : Platform dependent

Title

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HDMI DDC (Port C)

Rev_0.53

DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):

DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):

(Sampled:Rising edge of PCH_PWROK)

Display Port B/C/D Detected

0 =Port is not detected.

1 =Port is detected

Functional Strap Definitions

PDG0.9 P.771 PROC_POPIRCOMP/PCH_OPIRCOMP

PD 50ohm

#543016 PDG0.9 P.775

#544669 CRB RVP7 1.0 EDRAM_OPIO_RCOMP/EOPIO_RCOMP PD50ohm

SPI touch INT follow CRB

SPI touch RST follow CRB #544669 P.8

#545659 PCH EDS 0.7 P.108SCI capability is available on all GPIOs, while NMI and SMI capability is available onselected GPIOs only

Below are the PCH GPIOs that can be routed togenerate SMI# or NMI:

Trace width=20 mils,Spacing=25mil,Max length=100mils

COMPENSATION PU FOR eDP

XDP CONN

#543016 PDG0.9 P.753

PH 1K to VCCST

CPU over 130 degree will output low force S0->S5

Reserved for ESD 2014/9/17

EC_SCI# SOC internal PU

Place to CPU side

Follow 544924_Skylake_EDS_Vol_1_Rev_0.93

Place to CPU side

Reserved CATERR# for

EDP_COMP

SOC_DP1_AUXNSOC_DP1_AUXP

SOC_DP2_CTRL_DATASOC_DP2_CTRL_CLK

SOC_DP1_HPD

EC_SCI#

CPU_EDP_HPDENBKLSOC_BKL_PWMSOC_ENVDDSOC_DP1_CTRL_DATA

H_PECI

TP_INT#

CPU_POPIRCOMPPCH_OPIRCOMPEDRAM_OPIO_RCOMPEOPIO_RCOMP

CPU_XDP_TCK0

SOC_XDP_TMSSOC_XDP_TRST#

SOC_XDP_TDISOC_XDP_TDO

CPU_XDP_TCK0SOC_XDP_TMSSOC_XDP_TRST#

PCH_JTAG_TCK1SOC_XDP_TDISOC_XDP_TDO

H_PROCHOT#_RH_THERMTRIP#

XDP_TMSXDP_TRST#

XDP_TDIXDP_TCK0XDP_TDOXDP_PREQ#

XDP_PRDY#

XDP_HOOK0XDP_HOOK6XDP_PRSENT_PCH

CFG9CFG11

CFG15

CFG16

CFG10

CFG14CFG8

CFG13

CFG18CFG12

CFG19CFG17

CFG3 XDP_PRSENT_CPU

XDP_SPI_SI XDP_HOOK3PCH_JTAG_TCK1 XDP_TCK1CPU_XDP_TCK0 XDP_TCK0XDP_SPI_IO2

SOC_XDP_TDI XDP_TDI

XDP_PRSENT_PCH

SOC_XDP_TRST# XDP_TRST#

SOC_XDP_TDO XDP_TDOSOC_XDP_TMS XDP_TMS

XDP_HOOK0EC_RSMRST#

XDP_ITP_PMODE XDP_HOOK6

SOC_XDP_TDO

SOC_XDP_TMSSOC_XDP_TDI

SOC_XDP_TDO

XDP_ITP_PMODE

XDP_PRSENT_CPUXDP_PRSENT_PCH

CPU_XDP_TCK0PCH_JTAG_TCK1

CFG0

XDP_SPI_SI

H_CATERR#

SOC_DP1_N031SOC_DP1_P031SOC_DP1_N131SOC_DP1_P131

SOC_DP2_N030SOC_DP2_P030SOC_DP2_N130SOC_DP2_P130SOC_DP2_N230SOC_DP2_P230SOC_DP2_N330SOC_DP2_P330

EDP_TXP0 29EDP_TXN0 29EDP_TXP1 29EDP_TXN1 29

EDP_AUXP 29EDP_AUXN 29

SOC_DP1_AUXN 31SOC_DP1_AUXP 31

SOC_DP2_CTRL_CLK30

SOC_DP2_CTRL_DATA30

SOC_DP1_HPD 31SOC_DP2_HPD 30

SOC_BKL_PWM 29ENBKL 38SOC_ENVDD 29EC_SCI# 38

H_PECI38H_PROCHOT#

17 CFG417CFG617CFG717CFG1717CFG1617CFG817CFG917CFG1017CFG1117CFG1217CFG1317CFG1417CFG1517CFG1817CFG1917

XDP_PREQ# 12XDP_PRDY# 12

XDP_SPI_SI8XDP_SPI_IO28

EC_RSMRST#

10,38

XDP_ITP_PMODE17

+1.0VS_VCCSTG

+3VALW_PRIM+3VALW

+3VS

+1.0V_XDP+1.0VS_VCCSTG

11223344556677

17171818GND19GND20

E58DDI1_TXN[2]

F53DDI1_TXN[3]

F56

DDI1_TXP[0]

F55DDI1_TXP[1]

F58DDI1_TXP[2]

G53DDI1_TXP[3]

C52DDI2_TXN[2]

A50DDI2_TXN[3]

D51

DDI2_TXP[0]

D50DDI2_TXP[1]

D52DDI2_TXP[2]

B50DDI2_TXP[3]

C51

EDP_RCOMPE52

GPP_E19/DDPB_CTRLDATAL12

GPP_E20/DDPC_CTRLCLKN7

GPP_E21/DDPC_CTRLDATAN8

GPP_E22/DDPD_CTRLCLKN11

GPP_E23/DDPD_CTRLDATAN12

RC54 2 @ 1 0_0402_5%

OBS DATACMC_DEBUG_36PJTAG/RC/HOOKSJPCMC1

INTEL_CMC_PRIMARY

CONN@

DATA_613DATA_49DATA_511DATA_25DATA_37

DATA_118DATA_1210DATA_1312DATA_1414DATA_1516DATA_CLK_2P18DATA_CLK_2N20

DATA_82DATA_CLK_1N

17DATA_715

OPCE_RCOMPH66

GPP_B3/CPU_GP2BA5

GPP_B4/CPU_GP3AY5

GPP_E3/CPU_GP0A6

GPP_E7/CPU_GP1A7

BPM#[0]

C55BPM#[1]

D55BPM#[2]

B54BPM#[3]

PECIA54PROCHOT#

C65SKTOCC#

C63

RC21210K_0402_5%

RC231CMC@2 1K_0402_5%

RC6 2 149.9_0402_1%

T166

@

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#543016 PDG0.9 P.117 W=12-15 Space= 20/25 L=500mil

#543016 PDG0.9 P.163 RC place near SODIMM

DDR_VTT_CNTL to DDRVTT supplied ramped

<35uS(tCPU18)

Reserve for cost test.

DDR_DRAMRST#

SM_RCOMP0SM_RCOMP2

DDR_A_D57DDR_A_D59

DDR_A_D48

DDR_A_D56DDR_A_D54DDR_A_D51DDR_A_D53DDR_A_D49

DDR_A_D61DDR_A_D55DDR_A_D52

DDR_A_D60DDR_A_D62

DDR_A_D7

DDR_A_D13DDR_A_D8

DDR_A_D15DDR_A_D11

DDR_A_D18

DDR_A_D22

DDR_A_D29

DDR_A_D20DDR_A_D16

DDR_A_D25

DDR_A_D47DDR_A_D39

DDR_A_D33DDR_A_D35

DDR_A_D42

DDR_A_D38DDR_A_D40

DDR_A_D34DDR_A_D36

DDR_A_D43DDR_A_D37

DDR_A_D45DDR_A_D41

DDR_A_D46DDR_A_D44DDR_A_D32

DDR_A_ODT0

DDR_A_MA5DDR_A_MA6

DDR_A_CLK0DDR_A_CLK#0

DDR_A_CLK1DDR_A_CLK#1

DDR_A_MA8

DDR_A_CKE1

DDR_A_CS#1

DDR_A_MA7DDR_A_MA12DDR_A_MA15

DDR_A_MA13DDR_A_WE#

DDR_A_RAS#

DDR_A_BS0DDR_A_BS1DDR_A_MA10DDR_A_MA1DDR_A_MA3

DDR_A_DQS#0DDR_A_DQS0DDR_A_DQS#1DDR_A_DQS1DDR_A_DQS#2DDR_A_DQS2DDR_A_DQS#3DDR_A_DQS#4DDR_A_DQS3DDR_A_DQS4DDR_A_DQS#5DDR_A_DQS5DDR_A_DQS#6DDR_A_DQS6DDR_A_DQS#7DDR_A_DQS7

DDR_B_D3

DDR_B_D8

DDR_B_D13DDR_B_D4

DDR_B_D14

DDR_B_D7

DDR_B_D10

DDR_B_D2DDR_B_D0

DDR_B_D31

DDR_B_D17

DDR_B_D25

DDR_B_D28DDR_B_D30DDR_B_D27DDR_B_D22DDR_B_D18

DDR_B_D24DDR_B_D16

DDR_B_D32DDR_B_D34

DDR_B_D56

DDR_B_D60

DDR_B_D54

DDR_B_D57DDR_B_D53

DDR_B_D62DDR_B_D51

DDR_B_D61DDR_B_D58

DDR_B_MA5DDR_B_MA6DDR_B_MA7DDR_B_MA12DDR_B_MA15

DDR_B_MA13DDR_B_WE#

DDR_B_RAS#

DDR_B_BS0DDR_B_BS1DDR_B_MA10DDR_B_MA1DDR_B_MA3

DDR_B_DQS#0DDR_B_DQS0DDR_B_DQS#1DDR_B_DQS1DDR_B_DQS#2DDR_B_DQS2DDR_B_DQS#3DDR_B_DQS#4DDR_B_DQS3DDR_B_DQS4DDR_B_DQS#5DDR_B_DQS5DDR_B_DQS#6DDR_B_DQS6DDR_B_DQS#7DDR_B_DQS7

DDR_B_CLK1DDR_B_CLK#1DDR_B_CLK0

DDR_A_CS#0 18DDR_A_CS#1 18

DDR_A_BS2 18

DDR_A_CAS# 18DDR_A_WE# 18DDR_A_RAS# 18DDR_A_BS0 18DDR_A_BS1 18

DDR_A_MA5 18DDR_A_MA9 18DDR_A_MA6 18DDR_A_MA8 18DDR_A_MA7 18DDR_A_MA12 18DDR_A_MA11 18DDR_A_MA15 18DDR_A_MA14 18

DDR_A_MA2 18DDR_A_MA10 18DDR_A_MA1 18DDR_A_MA0 18DDR_A_MA3 18DDR_A_DQS#0 18DDR_A_MA4 18DDR_A_DQS0 18DDR_A_DQS#1 18DDR_A_DQS1 18DDR_A_DQS#2 18DDR_A_DQS2 18DDR_A_DQS#3 18DDR_A_DQS3 18DDR_A_DQS#4 18DDR_A_DQS4 18DDR_A_DQS#5 18DDR_A_DQS5 18DDR_A_DQS#6 18DDR_A_DQS6 18DDR_A_DQS#7 18DDR_A_DQS7 18

DDR_B_MA5 19DDR_B_MA9 19DDR_B_MA6 19DDR_B_MA8 19DDR_B_MA7 19DDR_B_MA12 19DDR_B_MA11 19DDR_B_MA15 19DDR_B_MA14 19

DDR_B_MA2 19DDR_B_MA10 19DDR_B_MA1 19DDR_B_MA0 19DDR_B_MA3 19DDR_B_DQS#0 19DDR_B_MA4 19DDR_B_DQS0 19DDR_B_DQS#1 19DDR_B_DQS1 19DDR_B_DQS#2 19DDR_B_DQS2 19DDR_B_DQS#3 19DDR_B_DQS3 19DDR_B_DQS#4 19DDR_B_DQS4 19DDR_B_DQS#5 19DDR_B_DQS5 19DDR_B_DQS#6 19DDR_B_DQS6 19DDR_B_DQS#7 19DDR_B_DQS7 19DDR_B_MA13 19

DDR_B_CLK#0 19DDR_B_CLK0 19DDR_B_CLK#1 19DDR_B_CLK1 19DDR_B_CKE0 19DDR_B_CKE1 19

DDR_B_CS#0 19DDR_B_CS#1 19DDR_A_ODT0 18

DDR_B_ODT1 19

SM_PG_CTRL 47

+0.675V_VREFCA+0.675V_A_VREFDQ

+1.35V_VDDQ+3VS

+1.35V_VDDQ

Title

@

CC57.1U_0402_16V7K 2 1

AF64DDR1_DQ[2]/DDR0_DQ[18]

AK65DDR1_DQ[3]/DDR0_DQ[19]

AH71DDR1_DQ[11]/DDR0_DQ[27]

AT66DDR1_DQ[17]/DDR0_DQ[49]

AU66DDR1_DQ[18]/DDR0_DQ[50]

AP65DDR1_DQ[19]/DDR0_DQ[51]

AN65DDR1_DQ[20]/DDR0_DQ[52]

AR40DDR1_DQ[37]/DDR1_DQ[21]

AP30DDR1_DQ[48]

AU27DDR1_DQ[49]

AT27DDR1_DQ[50]

AT25DDR1_DQ[51]

AU25DDR1_DQ[52]

AP27DDR1_DQ[53]

AN27DDR1_DQ[54]

AN25DDR1_DQ[55]

AP25DDR1_DQ[56]

AT22DDR1_DQ[57]

AU22DDR1_DQ[58]

AU21DDR1_DQ[59]

AT21DDR1_DQ[60]

AN22DDR1_DQ[61]

AP22DDR1_DQ[62]

AP21DDR1_DQ[63]

@1

AL68DDR0_DQ[2]

AN68DDR0_DQ[3]

AN69DDR0_DQ[4]

AL70DDR0_DQ[5]

AL69DDR0_DQ[6]

AN70DDR0_DQ[7]

AN71DDR0_DQ[8]

AR70DDR0_DQ[9]

AR68DDR0_DQ[10]

AU71DDR0_DQ[11]

AU68DDR0_DQ[12]

AR71DDR0_DQ[13]

AR69DDR0_DQ[14]

AU70DDR0_DQ[15]

BB65DDR0_DQ[17]/DDR0_DQ[33]

AW65DDR0_DQ[18]/DDR0_DQ[34]

AY63DDR0_DQ[20]/DDR0_DQ[36]

BA65DDR0_DQ[21]/DDR0_DQ[37]

74AUP1G07GW_TSSOP5GND3A2NC1

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SPI ROM ( 8MByte )

To SPI ROMDual SPI ROM_CS1#

RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

ESPI / LPC Bus

ESPI : +1.8V LPC : +3.3VRev_0.53

RPC5 and RC52 are close UC2

RPC23 and RC59 are close UC9

Change RC144~RC147, RC45 to 15ohm when use ESPISOC_SPI_CS#0

SOC_SPI_CLK_0_R

SOC_SPI_IO2SOC_SPI_IO2_0_R

SOC_SPI_CS#0

SOC_SPI_SI_0_RSOC_SPI_SO_0_R

SOC_SPI_CS#0

SOC_SPI_SI_0_RSOC_SPI_IO3_0_RSOC_SPI_SO_0_R

SOC_SPI_IO2

SOC_SPI_IO2_0_R

SOC_SPI_CLKSOC_SPI_SISOC_SPI_SO

EC_KBRST#_RTPM_SERIRQ

SOC_SPI_CS#1

SOC_SML1ALERT#

SOC_SML0CLKSOC_SML0DATASOC_SML1CLKSOC_SML1DATA

SOC_SMBCLK_1SOC_SMBDATA_1

SOC_SML0ALERT#

ESPI_CLKCK_LPC_TPM_RPM_CLKRUN#

LPC_FRAME#

LPC_AD2LPC_AD0LPC_AD3LPC_AD1

ESPI_RST#

SOC_SPI_CLK_1_RSOC_SPI_CS#1

SOC_SPI_SI_1_RSOC_SPI_IO3_1_RSOC_SPI_SO_1_R

SOC_SPI_SO

SOC_SPI_CLKSOC_SPI_SISOC_SPI_IO3SOC_SPI_SO_1_R

SOC_SPI_SI_1_R

SOC_SPI_IO3_1_RSOC_SPI_CLK_1_R

SOC_SML0CLKSOC_SML0DATAPM_CLKRUN#

SOC_SMBCLK_1SOC_SMBDATA_1

SOC_SPI_SISOC_SPI_SI_0_R

SOC_SPI_CLKSOC_SPI_CLK_0_R

SOC_SPI_SOSOC_SPI_SO_0_R

TPM_SERIRQ

SOC_SPI_SISOC_SPI_IO2

SOC_SMBDATA_1

SOC_SMBCLK

SOC_SMBCLKSOC_SMBDATASOC_SML1CLK

SOC_SML1DATA

EC_KBRST#_R38

TPM_SERIRQ38,39

ESPI_CLK_R 38ESPI_RST# 38

CK_LPC_TPM 39

LPC_AD2_R 38,39LPC_AD1_R 38,39

SOC_SMBCLK 18,19,41

SOC_SMBDATA 18,19,41

SOC_SML1CLK 20,31,38SOC_SML1DATA 20,31,38

Title

GPP_A1/LAD0/ESPI_IO0 AY13GPP_A2/LAD1/ESPI_IO1 BA13GPP_A3/LAD2/ESPI_IO2 BB13GPP_A4/LAD3/ESPI_IO3 AY12GPP_A5/LFRAME#/ESPI_CS# BA12GPP_A14/SUS_STAT#/ESPI_RESET# BA11

GPP_A9/CLKOUT_LPC0/ESPI_CLK AW9GPP_A10/CLKOUT_LPC1 AY9GPP_A8/CLKRUN# AW11

Q2017BDMN66D0LDW -7_SOT363-6

RC240_0402_5%

CLK 6GND

4

DI(IO0) 5DO(IO1)

2

/WP(IO2)

3

VCC 8/HOLD(IO3) 7/CS

1

Q2017ADMN66D0LDW -7_SOT363-6

RC2024.7K_0402_5% 2ESPI@ 1

UC2

W 25Q64FVSSIQ_SO88M_SINGLE@

CLK 6GND

4

DI(IO0) 5DO(IO1)

2

/WP(IO2)

3

VCC 8/HOLD(IO3) 7/CS

1

UC2

W 25Q64FVSSIQ_SO88M_DUAL@

SA000039A30

8M_DUAL@

12

JC1

ACES_91960-0084N_MX25L3206EM2ICONN@

CS#

1

SO/SIO1 2WP#

3

GND

4

VCC 8HOLD#

@EMC@

RC211CMC@ 2 1K_0402_1%

CC8.1U_0402_16V7K

RC260_0402_5%

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SPKR / GPP_B14 (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. -> AAX05 Use

1 = Enable TOP Swap Mode.

#543016 PDG0.9 P.321 Terminating Unused SDIO/SDXC Signals SDIO signals are multiplexed with GPIOs and default to GPIO functionality (as input) If SDIO interface is not used, the signals can be used as GPIOs instead If the GPIO functionality is also not used, the signals can

HDA_BIT_CLKHDA_SYNC

HDA_RST#

HDA_SDIN0HDA_SDOUT

HDA_SYNCHDA_SDOUTHDA_BIT_CLK

HDA_SDIN0HDA_RST#

ME_EN38HDA_SDIN040

SPKR40

HDA_SYNC_R40

HDA_SDOUT_R40

HDA_BIT_CLK_R40

HDA_RST#_R40

PCH_DMIC_CLK40

PCH_DMIC_DATA40

+3VALW _1.8VALW _PGPPD

Title

UMA@

SKL-UAUDIO

SDIO/SDXC

7 OF 20UC1G

GPP_F23 AF13

RC13410K_0402_5%

GPP_F13/EMMC_DATA0 AP2GPP_F14/EMMC_DATA1 AP1GPP_F15/EMMC_DATA2 AP3GPP_F16/EMMC_DATA3 AN3GPP_F17/EMMC_DATA4 AN1GPP_F18/EMMC_DATA5 AN2GPP_F19/EMMC_DATA6 AM4GPP_F20/EMMC_DATA7 AM1GPP_F21/EMMC_RCLK AM2GPP_F22/EMMC_CLK AM3GPP_F12/EMMC_CMD AP4EMMC_RCOMP AT1

RC80 2 1100_0402_1%

@

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Rev_0.53Follow 543016_SKL_U_Y_PDG_0_9

PH at DGPU side

Place at RAM DOOR

XCLK_BIASREF T:50ohm S:12/15 L:1000 Via:2

#543016 PDG0.9 P.526 PROCPWRGD is used only for power sequence debug and is not required to be connected to anything on the platform.

WAKE# (DSX wake event)

10 KΩ pull-up to VccDSW3_3.

The pull-up is required even

if PCIe* interface is not used on the platform.

LAN WAKE: LAN Wake Indicator from the GbE PHY.

Pull high @ VGA side

Reserved for ESD 2014/9/17

Follow 2014MOW48 Skylake U PU 2.7k ohm to 1V Cannonlake U PD 60.4 ohm

H_CPUPW RGD

EC_VCCST_PG

SYS_PW ROKPCH_PW ROKPCH_DPW ROKSUSPW RDNACKSUSACK#

PM_BATLOW #PM_BATLOW #

PBTN_OUT#_RSOC_VRALERT#

CLKREQ_PCIE#4

CLKREQ_PCIE#1CLK_PCIE_P1CLK_PCIE_N1

CLKREQ_PCIE#2

CLK_PCIE_N2CLK_PCIE_P2

CLKREQ_PCIE#5

SUSCLKSOC_XTAL24_INSOC_XTAL24_OUT

SOC_RTCX2SOC_SRTCRST#

SOC_RTCRST#

CLKREQ_PCIE#1CLKREQ_PCIE#2CLKREQ_PCIE#3

EC_RSMRST#

LAN_W AKE#

CLKREQ_PCIE#4CLKREQ_PCIE#5

PBTN_OUT#_R

PCH_PW ROKSYS_PW ROK

CLKREQ_PCIE#0

SOC_RTCX1SOC_RTCX2CLKREQ_PCIE#3

6,38

EC_VCCST_PG_R

38,42

SYS_PW ROK38,42

SUSPW RDNACK38

PM_SLP_S0# 6,38PM_SLP_S3# 6,38,42PM_SLP_S4# 6,38,42PM_SLP_S5# 6

PM_SLP_A# 6

CLK_PCIE_P0

20 CLK_PCIE_N020

CLKREQ_PCIE#1

33 CLK_PCIE_P1

33 CLK_PCIE_N133

CLK_PCIE_N235

CLK_PCIE_P235

CLKREQ_PCIE#235

PCH_PW ROK38,42

13

CC50.1U_0402_16V7K

@EMC@

12

YC124MHZ_12PF_7V24000020

4RC941 2 1M_0402_5%

T89 @

R157100K_0402_5%

R1072.2K_0402_5%

XCLK_BIASREF E42RTCX1 AM18RTCX2 AM20SRTCRST# AN18RTCRST# AM16

UC3MC74VHC1G08DFT2G_SC70-5

@

SKL-USYSTEM POWER MANAGEMENT

11 OF 20UC1K

GPP_A11/PME# AU11INTRUDER# AP16

GPP_B11/EXT_PWR_GATE# AM10GPP_B2/VRALERT# AM11

RC104 1K_0402_5%

T165@

CC158.2P_0402_50V8D

@EMC@

12

@

Trang 11

SPKR / GPP_B14 (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. -> AAX05 Use

1 = Enable TOP Swap Mode.

GSPI0_MOSI /GPP_B18 (Internal Pull Down):

(Rising edge of PCH_PWROK)

No Reboot

0 = Disable No Reboot mode > AAX05 Use

1 = Enable No Reboot Mode (PCH will disable the TCO

Timer system reboot feature) This function is useful

when running ITP/XDP.

GSPI1_MOSI / GPP_B22 (Internal Pull Down):

(Rising edge of PCH_PWROK)

Boot BIOS Strap Bit

0 = SPI Mode > AAX05 Use

1 = LPC Mode

SML0ALERT# / GPP_C5 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# )

eSPI or LPC

0 = LPC is selected for EC > For KB9022/9032 Use

1 = eSPI is selected for EC > For KB9032 Only.

SMBALERT# / GPP_C2 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# )

TLS Confidentiality

0 = Disable Intel ME Crypto Transport Layer Security

(TLS) cipher suite (no confidentiality).

1 = Enable Intel ME Crypto (TLS) (with confidentiality)

Must be pulled up to support Intel AMT with TLS and Intel

SBA (Small Business Advantage) with TLS.

HDA_SDO/I2S_TXD0 (Internal Pull Down):

(Sampled: Rising edge of PCH_PWROK ) Flash Descriptor Security Override

0 = Enable security measures defined in the Flash Descriptor

1 = Disable Flash Descriptor Security (override) This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY

DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):

DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):

(Sampled:Rising edge of PCH_PWROK) Display Port B/C/D Detected

0 =Port D is not detected.

*

1 1

A4WAS

Project_ID0 Project_ID1

Reserved Reserved

<Reserved for Touch PNL>

VGA_ID

1

0 GM

GL

RANK_ID SR DR

GPP_D9

0 1 GPP_D10

TS_ENGC6_FB_EN_RGSPI0_MOSI

EC_LID_OUT#

GSPI1_MOSI

GPU_EVENT_R#

UART_2_CTXD_DRXDUART_2_CRTS_DCTS

I2C_0_SCLI2C_0_SDA

I2C_1_SDAI2C_1_SCLI2C_2_SDAI2C_2_SCLI2C_3_SDAI2C_3_SCLI2C_4_SDAI2C_4_SCL

SOC_GPIOD13

SOC_GPIOD16

ISH_I2C0_SDAISH_I2C0_SCL

DGPU_HOLD_RST#

DGPU_PWR_EN

UART_2_CTXD_DRXDUART_2_CRXD_DTXD

UART_2_CRTS_DCTSUART_2_CCTS_DRTS

I2C_5_SDAI2C_5_SCL

ISH_I2C1_SCLISH_I2C1_SDA

ISH_I2C0_SDAISH_I2C0_SCL

PROJECT_ID0

PROJECT_ID1VGA_ID

DGPU_HOLD_RST# 20DGPU_PWR_EN 42

UART_2_CTXD_DRXD35

UART_2_CRXD_DTXD35

EC_LID_OUT#

38

I2C_1_SDA39I2C_1_SCL39

G_INT# 41

GPU_EVENT# 20

GC6_FB_EN 20

I2C_0_SDA29I2C_0_SCL29

+3VALW_PGPPC

Title

2

T108@T110@

SKL-U_BGA1356

@

GPP_A12/BM_BUSY#/ISH_GP6 AP13

GPP_A18/ISH_GP0 AY8GPP_A19/ISH_GP1 BA8GPP_A20/ISH_GP2 BB7GPP_A21/ISH_GP3 BA7GPP_A22/ISH_GP4 AY7GPP_A23/ISH_GP5 AW 7

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U1

GPP_D16/ISH_UART0_CTS#/SML0BALERT# U4GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U2

GPP_D15/ISH_UART0_RTS# U3

GPP_D5/ISH_I2C0_SDA M4GPP_D6/ISH_I2C0_SCL N3GPP_D7/ISH_I2C1_SDA N1GPP_D8/ISH_I2C1_SCL N2GPP_D9 P2

GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD11GPP_F11/I2C5_SCL/ISH_I2C2_SCL AD12

T128 @

Trang 12

USB2 Port 2

GPIO USB_OC0#

USB_OC1#

DEVSLP0

DEVSLP2 DEVSLP1

USB_OC2#

USB_OC3#

DEVICE CONTROL USB2 Port 1

NA NA

NA SATA_GP0 SATA_GP1 SATA_GP2

NA

NA NA

#543016 P.239 PCIE_RCOMPN/PCIE_RCOMPP BO=4 W=12 S=12 R=100ohm

DEVSLP[2:0] ImplementationDEVSLP is a host-controlled hardware signal which enables a SATA host and device to enter an ultra-low interface power state, including the possibility to completely power down host and device PHYs

The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U

When high, DEVSLP requests the SATA device to enter into the DEVSLP power state

‧

When low, DEVSLP requests the SATA device to exit from the DEVSLP power state

‧

and transition to active state

SATA General Purpose (SATAGP[2:0]) SignalsThe processor provides three SATA general purpose input signals,SATAGP[2:0] for SKL U

‧

These signals can be configured as interlock switch inputs corresponding to a given SATA port When used as an interlock switch status indication, this signal should be driven to 0

‧

to indicate that the switch is closed and to a 1 to indicate that the switch is open

If mechanical presence switches will not be used on the platform, SATAGP[2:0]

‧

signals can be configured as GPP_E[2:0] GPIOs signals

Acer HSIO def i ne

DGPU

NGFF WLAN+BT(Key E)

GLAN+CR

When PCIE8/SATA1A is used

as SATA Port 1 (ODD), then

USB20_N1USB20_P1USB20_P2

USB20_N6USB20_P6USB20_P7USB20_N7

PCIE_RCOMPNXDP_PRDY#

USB2_COMP

USB_OC0#

USB20_N5USB20_P5

PCIE_CTX_GRX_P3PCIE_CRX_GTX_P3

PCIE_CTX_GRX_N4PCIE_CRX_GTX_N4

PCIE_CTX_DRX_N5PCIE_CRX_DTX_N5PCIE_CTX_DRX_P5PCIE_CRX_DTX_P5

PCIE_CRX_DTX_N6PCIE_CTX_DRX_P6

USB2_IDUSB2_VBUSSENSE

USB20_N6 29USB20_P6 29

USB20_N1 37USB20_P1 37USB20_N2 37USB20_P2 37

USB3_CRX_DTX_P1 37USB3_CRX_DTX_N1 37USB3_CTX_DRX_N1 37USB3_CTX_DRX_P1 37

XDP_PREQ#

6 XDP_PRDY#

6

USB3_CRX_DTX_P2 37USB3_CRX_DTX_N2 37USB3_CTX_DRX_N2 37USB3_CTX_DRX_P2 37

USB_OC0# 37

USB20_N5 35USB20_P5 35

USB20_N7 29USB20_P7 29

SATA_CTX_DRX_N036

SATA_CRX_DTX_N036

SATA_CTX_DRX_P036

SATA_CRX_DTX_P036

SATA_CTX_DRX_P136

SATA_CRX_DTX_N136

SATA_CTX_DRX_N136

SATA_CRX_DTX_P136

USB20_P3 37USB20_N3 37

USB_OC1# 37

PCIE_CRX_GTX_P120

PCIE_CRX_GTX_N120

PCIE_CTX_C_GRX_N120

PCIE_CTX_C_GRX_P120

PCIE_CRX_GTX_N220

PCIE_CRX_GTX_P220

PCIE_CTX_C_GRX_N220

PCIE_CTX_C_GRX_P220

PCIE_CTX_C_GRX_N320

PCIE_CRX_GTX_N320

PCIE_CRX_GTX_P320

PCIE_CTX_C_GRX_P320

PCIE_CTX_C_GRX_N420

PCIE_CRX_GTX_N420

PCIE_CRX_GTX_P420

PCIE_CTX_C_GRX_P420

PCIE_CTX_C_DRX_P533

PCIE_CTX_C_DRX_N5

3333 PCIE_CRX_DTX_P5PCIE_CRX_DTX_N533

PCIE_CRX_DTX_P6

35 PCIE_CRX_DTX_N635

PCIE_CTX_C_DRX_P635

PCIE_CTX_C_DRX_N635

+3VALW _PRIM+3VALW _PRIM

Title

USB2N_4 AD9USB2P_4 AD10USB2N_5 AJ1USB2P_5 AJ2USB2N_6 AF6USB2P_6 AF7

USB2N_7 AH1USB2P_7 AH2USB2N_8 AF8USB2P_8 AF9USB2N_9 AG1USB2P_9 AG2

USB2N_10 AH7USB2P_10 AH8USB2_COMP AB6USB2_ID AG3USB2_VBUSSENSE AG4

GPP_E9/USB2_OC0# A9GPP_E10/USB2_OC1# C9GPP_E11/USB2_OC2# D9GPP_E12/USB2_OC3# B9GPP_E4/DEVSLP0 J1GPP_E5/DEVSLP1 J2GPP_E6/DEVSLP2 J3

GPP_E0/SATAXPCIE0/SATAGP0 H2GPP_E1/SATAXPCIE1/SATAGP1 H3GPP_E2/SATAXPCIE2/SATAGP2 G4GPP_E8/SATALED# H1

C3803 1 2.1U_0402_16V7KCC262 1.1U_0402_16V7KCC17 VGA@1 2 0.22U_0402_16V7K

Trang 13

543016_SKL_PDG_1_0 +1.35V_VDDQ_CPU : 2x 10uF 0402 (Placeholder) 4x 1uF 0201 (Placeholder) 4x 10uF 0402

For Power consumption Measurement

BSC Side PSC Side

543016_SKL_PDG_1_0 +1.0V_VCCSFR : 1x 1uF 0402

543016_SKL_PDG_1_0 +1.0V_VCCST : 1x 1uF 0402

543016_SKL_PDG_1_0 +1.0VS_VCCSTG : 1x 1uF 0402 (Placeholder)

PSC Side

BSC Side

543016_SKL_PDG_1_0 +1.35V_VDDQC : 1x 1uF 0201 (Placeholder) 1x 10uF 0402

PSC Side

6.35A 2.73A

6A

0.09A 0.04A 0.04A 0.26A 0.12A

VCCSA_SENSE

VCCIO_SENSEVSSIO_SENSEVSSSA_SENSE

EN_1.8VSEN_1.0V_VCCSTU

SUSP#

38,42,45,47,49

SYSON38,42,47

+VCC_SA+1.35V_VDDQ_CPU

+1.35V_VDDQ_CPU

+1.35V_VDDQ

+1.0VS_VCCSTG

+1.0V_VCCST+1.0VS_VCCSTG+1.35V_VCCSFR_OC+1.0V_VCCSFR

+1.35V_VDDQC+1.35V_VDDQ_CPU

CC951000P_0402_50V7K

CC96.1U_0402_16V7K1

@

CC49 1 2 1U_0402_6.3V6KCC55 1 2 1U_0402_6.3V6K

@12

CC48 1 2 1U_0402_6.3V6KUC6

TPS22961DNYR_W SON8

GND 5ON

4

VOUT 6VIN2

2

SKL-UCPU POWER 3 OF 4

14 OF 20UC1N

VCCIO_SENSE AM23

VCCSA AK23VCCSA AK25VCCSA G23VCCSA G25VCCSA G27VCCSA G28VCCSA J22VCCSA J23VCCSA J27VCCSA K23VCCSA K25VCCSA K27VCCSA K28VCCSA K30

VSSIO_SENSE AM22

VSSSA_SENSE H21VCCSA_SENSE H20

7

CT1 12VOUT1 14

VOUT2 8

VOUT1 13VIN1

VOUT 7VOUT 8VIN

2

Trang 14

+CHGRTC BAT54C(VF) +3VL_RTC

Power Rail Voltage

3.383V(MAX)

240 mV 3.143V Result : Pass

CC77,CC78 near AK17 (<3 mm)

CC86 near A10 (<3 mm) CC87 near K17 (<3 mm)

+1.0VALW _CLK6_24TBT+RTCVCC

+1.0VALW _APLL+1.0VALW _CLK4_F100OC

+1.0VALW _PRIM

+1.0VALW _MPHYAON

+1.0VALW _AMPHYPLL+1.0VALW _APLL

+1.0VALW _CLK5_F24NS

+1.0VALW _PRIM+3VALW _DSW

+3VALW _HDA+3VALW _SPI

+3VALW _PGPPC+3VALW _1.8VALW _PGPPD+3VALW _PGPPE+1.8VALW _PRIM+3VALW _PGPPG

+1.0VALW _SRAM

+3VALW _PRIM

+1.0VALW _PRIM+1.0VALW _APLLEBB

+3VALW _1.8VALW _PGPPA+3VALW _PGPPB

+1.0VALW _CLK6_24TBT+1.0VALW _PRIM

+1.0VALW _PRIM +3VALW _PRIM +1.8VALW _PRIM

+1.0VALW _MPHYPLL+1.0VALW _PRIM

+RTCBATT

+RTCVCC+CHGRTC

+3VALW _SPI

+1.0VALW _MPHYGT

+1.0VALW _VCCCLK2

+3VALW _PRIM+1.8VALW _PRIM+3VALW _1.8VALW _PGPPA

+1.8VALW _PRIM+3VALW _1.8VALW _PGPPD +3VALW _PRIM

+1.8VALW _PRIM

+3VALW _PRIM

+3VALW _PRIM+3VALW _RTC

+1.0VALW _CLK6_24TBT +1.0VALW _PRIM

+1.0VALW _VCCCLK2 +1.0VALW _PRIM

+1.0VALW _CLK4_F100OC +1.0VALW _PRIM

+1.0VALW _CLK5_F24NS +1.0VALW _PRIM

+1.0VALW _MPHYAON+1.0VALW _PRIM

CC861U_0402_6.3V6K @

12

CC911U_0402_6.3V6K

@12

RC1870_0402_5% 2 @ 1

2

CC871U_0402_6.3V6K

RC175 1 @ 2 0_0402_5%

15 OF 20UC1O

SKL-U_BGA1356

@

GPP_B0/CORE_VID0 AN11GPP_B1/CORE_VID1 AN13

DC1

BAS40-04_SOT23-31

2

3

RC209 1 @ 2 0_0603_5%

CC78.1U_0402_16V7K

12

RC1670_0402_5% 2 @ 1

RC1960_0402_5% 2ESPI@ 1

RC198 1 @ 2 0_0402_5%

CC731U_0402_6.3V6K @

12

RC148 1 @ 2 0_0603_5%

C151.1U_0402_16V7K1

12

CC631U_0402_6.3V6K

12

CC1021U_0402_6.3V6K @

12

CC741U_0402_6.3V6K @

12

CC721U_0402_6.3V6K

12

CC771U_0402_6.3V6K

12

CC671U_0402_6.3V6K @

12

CC831U_0402_6.3V6K @

12

CC681 2 1U_0402_6.3V6K

RC1690_0402_5% 2 @ 1

RC156 1 @ 2 0_0402_5%

RC1710_0402_5% 2 @ 1

RC176 1 @ 2 0_0603_5%

RC1620_0402_5% 2 @ 1

RC149 1 @ 2 0_0603_5% CC61 1U_0402_6.3V6K

@

CC12422U_0603_6.3V6M @

12

CC761U_0402_6.3V6K

2

CC751U_0402_6.3V6K @

12

CC851U_0402_6.3V6K

12

RC1970_0402_5% 2 @ 1

RC154 1 @ 2 0_0402_5%

RC1640_0603_5% 2 @ 1

CC12322U_0603_6.3V6M

@

RC1630_0402_5% 2 @ 1

2

RC1610_0402_5% 2 @ 1

2

Trang 15

1 1

Trace Length < 25 mils

For CPU2+3e SKU

Trace Length < 25 mils

SVID ALERT

SVID DATA

Place the PU resistors close to CPU

#544924 Skylake EDS P.121 VCCGT U(15W)-dual core GT2 40A(MAX) 0.55-1.15V

VCCGT_SENSEVSSGT_SENSE

VCCOPC_SENSE

VCCEOPIO_SENSEVSSEOPIO_SENSE

SOC_SVID_CLKSOC_SVID_ALERT#

SOC_SVID_ALERT#

VCCGTX_SENSEVSSGTX_SENSE

SOC_SVID_DAT

VCCGT_SENSE50

VSSGT_SENSE50

VCCSENSE 50VSSSENSE 50

Title

T155@T133 @

T219@

RC180 220_0402_5%

RC181100_0402_1%

13 OF 20UC1M

VCCGTX_AK42 AK42VCCGTX_AK43 AK43VCCGTX_AK45 AK45VCCGTX_AK46 AK46VCCGTX_AK48 AK48VCCGTX_AK50 AK50VCCGTX_AK52 AK52VCCGTX_AK53 AK53VCCGTX_AK55 AK55VCCGTX_AK56 AK56VCCGTX_AK58 AK58VCCGTX_AK60 AK60VCCGTX_AK70 AK70VCCGTX_AL43 AL43VCCGTX_AL46 AL46VCCGTX_AL50 AL50VCCGTX_AL53 AL53VCCGTX_AL56 AL56VCCGTX_AL60 AL60VCCGTX_AM48 AM48VCCGTX_AM50 AM50VCCGTX_AM52 AM52VCCGTX_AM53 AM53VCCGTX_AM56 AM56VCCGTX_AM58 AM58VCCGTX_AU58 AU58VCCGTX_AU63 AU63VCCGTX_BB57 BB57VCCGTX_BB66 BB66VCCGTX_SENSE AK62VSSGTX_SENSE AL61VSSGT_SENSE

J69T137 @

12 OF 20UC1L

VIDALERT# B63VIDSCK A63VIDSOUT D64VCCSTG_G20 G20

RSVD_K32

K32

VSS_SENSE E33RSVD_AK32

AK32

Trang 16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

17 OF 20UC1Q

BA45

VSS BA49VSS BA53VSS BA57VSS BA6VSS BA62VSS BA66VSS BA71VSS BB18VSS BB26VSS BB30VSS BB34VSS BB38VSS BB43VSS BB55VSS BB6VSS BB60VSS BB64VSS BB67VSS BB70VSS C1VSS C25VSS C5VSS D10VSS D11VSS D14VSS D18VSS D22VSS D25VSS D26VSS D30VSS D34VSS D39VSS D44VSS D45VSS D47VSS D48VSS D53VSS D58VSS D6VSS D62VSS D66VSS D69VSS E11VSS E15VSS E18VSS E21VSS E46VSS E50VSS E53VSS E56VSS E6VSS E65VSS E71VSS F1VSS F13VSS F2VSS F22VSS F23VSS F27VSS F28VSS F32VSS F33VSS F35VSS F37VSS F38VSS F4VSS F40VSS F42VSS

F68

SKL-UGND 1 OF 3

16 OF 20UC1P

SKL-UGND 3 OF 3

18 OF 20UC1R

Trang 17

Display Port Presence Strap

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

1 : Disabled; No Physical Display Port

attached to Embedded Display Port

For 2+3e Solution PM_ZVM#

Zero Voltage Mode: Control Signal to OPC

VR, when low OPC VR output is 0V.

PM_MSM#

Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solution for OPC).

CFG16CFG18

CFG0CFG2CFG4CFG6CFG8CFG10CFG12CFG14

CFG06CFG16CFG26CFG36CFG46CFG56CFG66CFG76CFG86CFG96CFG106CFG116CFG126CFG136CFG146CFG156

XDP_ITP_PMODE6

+1.0V_VCCST+1.8VALW _PRIM

Title

T157@

SKL-URESERVED SIGNALS-1

19 OF 20UC1S

SKL-U_BGA1356

@

RSVD_BA4 BA4RSVD_BB4 BB4

RSVD_A69 A69RSVD_B69 B69

RSVD_TP_BB68 BB68RSVD_TP_BB69 BB69

RSVD_TP_AK13 AK13RSVD_TP_AK12 AK12

TP4 BB5

TP5 AU5TP6 AT5

RSVD_B3 B3RSVD_A3 A3

@1

2T159@

T215 @

T225@

SKL-USPARE

20 OF 20UC1T

T216@

T221@T223@

T199@

T214@T156@

2

RC184 @ 100K_0402_5%

Trang 18

Interleaved Memory

2-3A to 1 DIMMs/channel Reverse Type

SGA00009S00 330U 2V H1.9

Follow MA51

Place near to SO-DIMM connector.

2015MOW02, Can't install Cap on DRAMRST

SOC_SMBDATASOC_SMBCLK

DDR_A_BS1

DDR_A_CLK#1DDR_A_CLK1DDR_A_RAS#

DDR_A_CS#0

SOC_SMBDATASOC_SMBCLK

DDR_A_D47DDR_A_D45

DDR_A_D46

DDR_A_D53

DDR_A_DQS6DDR_A_DQS#6

DDR_A_D55

DDR_A_MA1DDR_A_MA5DDR_A_MA9

DDR_A_MA10DDR_A_MA12

DDR_A_MA13DDR_A_BS0

DDR_A_BS2

DDR_A_CLK0DDR_A_CLK#0DDR_A_CKE0

DDR_A_CAS#

DDR_A_WE#

DDR_A_D60DDR_A_D58

DDR_A_D37

DDR_A_D38DDR_A_D32

DDR_A_D39DDR_A_DQS4DDR_A_DQS#4DDR_A_CS#1

DDR_A_D17

DDR_A_D18DDR_A_DQS2DDR_A_DQS#2

DDR_A_D15DDR_A_DQS1DDR_A_DQS#1

DDR_A_D3

DDR_A_D5

DDR_A_D2DDR_A_D12

DDR_A_MA7DDR_A_MA11

DDR_A_MA4DDR_A_MA2

DDR_A_CLK1DDR_A_CLK#1DDR_A_BS1DDR_A_RAS#

DDR_A_CS#0DDR_A_ODT0

DDR_A_D19

DDR_A_D16

DDR_A_D25

DDR_A_D26DDR_A_DQS3DDR_A_DQS#3DDR_A_D24DDR_A_D10

DDR_A_CKE1

DDR_A_MA14

DDR_A_D62

DDR_A_D36

DDR_A_D34DDR_A_D41

DDR_A_D43DDR_A_D52

DDR_A_D50DDR_A_D57

@1

12

@1

2

CD17.1U_0402_16V7K1

2

RD1224.9_0402_1%

RD1470_0402_5%

CKE1 74VDD 76A15 78A14 80VDD 82A11 84A7 86VDD 88A6 90A4 92VDD 94A2 96A0 98VDD 100CK1 102CK1# 104VDD 106BA1 108RAS# 110VDD 112S0# 114ODT0 116VDD 118ODT1 120

NC 122VDD 124VREF_CA 126VSS 128DQ36 130DQ37 132VSS 134DM4 136VSS 138DQ38 140DQ39 142VSS 144DQ44 146DQ45 148VSS 150DQS5# 152DQS5 154VSS 156DQ46 158DQ47 160VSS 162DQ52 164DQ53 166VSS 168DM6 170VSS 172DQ54 174DQ55 176VSS 178DQ60 180DQ61 182VSS 184DQS7# 186DQS7 188VSS 190DQ62 192DQ63 194VSS 196EVENT# 198SDA 200SA1

207

BOSS2 208

CD210.022U_0402_16V7K1

Trang 19

Layout Note:

Place near JDIMM2.199

From CPU10mils

10mils

2-3A to 1 DIMMs/channel Standard Type

Place near to SO-DIMM connector.

2015MOW02, Can't install Cap on DRAMRST

+0.675VS_VTTSOC_SMBDATASOC_SMBCLK

DDR_DRAMRST#

DDR_B_BS2DDR_B_BS0

DDR_B_CKE0

DDR_B_CLK0DDR_B_CLK#0

DDR_B_WE#

DDR_B_CAS#

DDR_B_CS#1DDR_B_CKE1

DDR_B_CLK1DDR_B_CLK#1

DDR_B_BS1

DDR_B_RAS#

DDR_B_ODT0DDR_B_CS#0

DDR_B_ODT1

SOC_SMBCLKSOC_SMBDATA

DDR_B_D59

DDR_B_CKE0

DDR_B_BS2DDR_B_MA12DDR_B_MA9DDR_B_MA8

DDR_B_MA3

DDR_B_CLK0DDR_B_CLK#0DDR_B_MA10DDR_B_BS0DDR_B_WE#

DDR_B_CAS#

DDR_B_MA13DDR_B_CS#1

DDR_B_D24

DDR_B_D3DDR_B_D1

DDR_B_D2

DDR_B_DQS#0DDR_B_DQS0DDR_B_D5

DDR_B_D22

DDR_B_D17DDR_B_DQS#2DDR_B_DQS2

DDR_B_D27

DDR_B_D13

DDR_B_D14DDR_B_D11

DDR_B_D34

DDR_B_D37

DDR_B_DQS4DDR_B_DQS#4

DDR_B_D35

DDR_B_D57

DDR_B_D42

DDR_B_DQS#6DDR_B_D49

DDR_B_D56

DDR_B_D43DDR_B_D44

DDR_B_D55DDR_B_DQS6DDR_B_D45DDR_B_D36

DDR_B_D10DDR_B_D12

DDR_B_CKE1

DDR_B_MA14DDR_B_MA7DDR_B_MA11

DDR_B_MA6

DDR_B_MA2

DDR_B_CLK1DDR_B_CLK#1DDR_B_MA0

DDR_B_BS1DDR_B_RAS#

DDR_B_ODT0DDR_B_CS#0

DDR_B_ODT1

DDR_B_D29

DDR_B_D21

DDR_B_D23DDR_B_D6

DDR_B_D19DDR_B_D20

DDR_B_D31DDR_B_DQS3DDR_B_D30DDR_B_DQS#3

DDR_B_D38DDR_B_D33

DDR_B_DQS7DDR_B_D60

DDR_B_D62

DDR_B_DQS5DDR_B_D47

DDR_B_D63

DDR_B_D51DDR_B_D52

DDR_B_D54

DDR_B_D40DDR_B_D39

DDR_DRAMRST# 7,18

DDR_B_BS27DDR_B_BS07

DDR_B_CKE07

DDR_B_CS#17

DDR_B_CAS#

7DDR_B_WE#

7

DDR_B_CLK07

DDR_B_CLK#07

DDR_B_CKE17

DDR_B_CLK17

DDR_B_CLK#17

DDR_B_BS17

DDR_B_RAS#

7

DDR_B_CS#07

DDR_B_ODT07

DDR_B_ODT17

SOC_SMBDATA8,18,41

SOC_SMBCLK8,18,41

CD30.1U_0402_16V7K

@1

RD170_0402_5%

CD310.022U_0402_16V7K1

3

DQ4 4DQ0

5

DQ5 6DQ1

7

VSS3 8VSS4

9

DQS#0 10DM0

11

DQS0 12VSS5

13

VSS6 14DQ2

15

DQ6 16DQ3

17

DQ7 18VSS7

19

VSS8 20DQ8

21

DQ12 22DQ9

23

DQ13 24VSS9

25

VSS10 26DQS#1

27

DM1 28DQS1

29

RESET# 30VSS11

31

VSS12 32DQ10

33

DQ14 34DQ11

35

DQ15 36VSS13

37

VSS14 38DQ16

39

DQ20 40DQ17

41

DQ21 42VSS15

43

VSS16 44DQS#2

45

DM2 46DQS2

47

VSS17 48VSS18

49

DQ22 50DQ18

51

DQ23 52DQ19

53

VSS19 54VSS20

55

DQ28 56DQ24

57

DQ29 58DQ25

59

VSS21 60VSS22

61

DQS#3 62DM3

63

DQS3 64VSS23

65

VSS24 66DQ26

67

DQ30 68DQ27

69

DQ31 70VSS25

85

A7 86VDD5

87

VDD6 88A8

75

VDD2 76NC1

77

A15 78BA2

79

A14 80VDD3

93

VDD8 94A3

95

A2 96A1

97

A0 98VDD9

99

VDD10 100CK0

101

CK1 102CK0#

103

CK1# 104VDD11

105

VDD12 106A10/AP

107

BA1 108BA0

109

RAS# 110VDD13

115

ODT0 116VDD15

117

VDD16 118A13

119

ODT1 120S1#

121

NC2 122VDD17

123

VDD18 124NCTEST

125

VREF_CA 126VSS27

127

VSS28 128DQ32

129

DQ36 130DQ33

131

DQ37 132VSS29

133

VSS30 134DQS#4

135

DM4 136DQS4

137

VSS31 138VSS32

139

DQ38 140DQ34

141

DQ39 142DQ35

143

VSS33 144VSS34

145

DQ44 146DQ40

147

DQ45 148DQ41

149

VSS35 150VSS36

151

DQS#5 152DM5

153

DQS5 154VSS37

155

VSS38 156DQ42

157

DQ46 158DQ43

159

DQ47 160VSS39

161

VSS40 162DQ48

163

DQ52 164DQ49

165

DQ53 166VSS41

167

VSS42 168DQS#6

169

DM6 170DQS6

171

VSS43 172VSS44

173

DQ54 174DQ50

175

DQ55 176DQ51

177

VSS45 178VSS46

179

DQ60 180DQ56

181

DQ61 182DQ57

183

VSS47 184VSS48

185

DQS#7 186DM7

187

DQS7 188VSS49

189

VSS50 190DQ58

191

DQ62 192DQ59

193

DQ63 194VSS51

195

VSS52 196SA0

197

EVENT# 198VDDSPD

199

SDA 200SA1

201

SCL 202VTT1

203

VTT2 204G1

Trang 20

17mA SM01000AG00 2A 300ohm@100mhz DCR 0.1

SP_PLLVDD+VID_PLLVDD 0.1Ux2, 10Ux1,47Ux1 300ohm(ESR0.2)x1

O

I

GPIO

I I/O USAGE

+PLLVDD

I2CS_SCLI2CS_SDA

PEG_CLKREQ#

PEX_TSTCLK_OUT+

PEX_TSTCLK_OUT-PLTRST_VGA#

PEX_TREMP

ACIN_BUF

GPIO8_OVERTGPIO9_ALERTDGPU_VIDPSI

3VSDGPU_MAIN_ENGC6_FB_EN

GPU_EVENT#_1

GPU_PEX_RST_HOLD#

I2CS_SCLI2CS_SDA

+PLLVDD

+GPU_PLLVDD

XTAL_SSINXTAL_OUTBUFF

GPU_EVENT#_1

PCIE_CRX_C_GTX_P1PCIE_CRX_C_GTX_N1PCIE_CRX_C_GTX_P2PCIE_CRX_C_GTX_N2PCIE_CRX_C_GTX_P3PCIE_CRX_C_GTX_N3PCIE_CRX_C_GTX_N4PCIE_CRX_C_GTX_P4

GPU_OVERT 38

GPU_ALERT 38

1.5VS_DGPU_PWR_EN 42,53

SYS_PEX_RST_MON# 22DGPU_HOLD_RST#

11

PLT_RST#

10,38,39

DGPU_PWROK10,42,54,55

DGPU_AC_DETECT 11,38

CLK_PCIE_P010CLK_PCIE_N010PEG_CLKREQ#

10

DGPU_VID 55PSI 55

3VSDGPU_MAIN_EN 42,55GC6_FB_EN 11

GPU_EVENT# 11

PCIE_CTX_C_GRX_N1

12 PCIE_CTX_C_GRX_P112

PCIE_CTX_C_GRX_N2

12 PCIE_CTX_C_GRX_P212

PCIE_CTX_C_GRX_P312

PCIE_CTX_C_GRX_N312

PCIE_CTX_C_GRX_P412

PCIE_CTX_C_GRX_N412

VGA@

CV15 VGA@1 20.22U_0402_16V7K

C200747U_0805_6.3V6M

VGA@

Q2001ADMN66D0LDW-7_SOT363-6

VGA@

61

VGA@

61

R2056 2 @ 1 10K_0402_5%

CV16 VGA@1 20.22U_0402_16V7K

RP200110K_0804_8P4R_5%

GC6@

18273645

CV17 VGA@ 1 20.22U_0402_16V7K

R2005 1VGA@ 2 1.8K_0402_1%

D2011RB751V-40_SOD323-2

GC6@

12

RP200010K_0804_8P4R_5%

VGA@

18273645

R201710K_0402_5%

VGA@

C200610U_0603_6.3V6M

VGA@

C200322U_0603_6.3V6M

VGA@

GND233

GND4

R2014200K_0402_1%

NGC6@

R20230_0402_5%

@

D2000RB751V-40_SOD323-2

VGA@

12

R2001 1VGA@ 2 1.8K_0402_1%

Q2001BDMN66D0LDW-7_SOT363-6

VGA@

34

R201810K_0402_5%

@

PEX_RX0_NAG7

PEX_RX2_NAF9

PEX_REFCLKAE8

NCAB15

PEX_CLKREQ_NAC6

NCAC16

NCAF15

NCAG24

NCAD17

NCAG25

NCAE21

PEX_RX1_NAE7

NCAF12

NCAC15

NCAG13

NCAD14

PEX_RX3AG9

PEX_REFCLK_NAD8

NCAF16

NCAB13

NCAG21

NCAC20

NCAE15

NCAG19

PEX_TSTCLK_OUT_NAE22

PEX_RX2AE9

NCAE10

NCAB21

PEX_TX2_NAC11

NCAF13

NCAG16

PEX_TSTCLK_OUTAF22

PEX_RX3_NAG10

NCAD23

PEX_TX1AB10PEX_TX0AC9

NCAG22

NCAC19

PEX_TX3AC12

NCAG18

NCAB19

NCAE23NCAF24

NCAE12

NCAB18NCAC17

NCAE16

PEX_TX2AD11

NCAE13

PEX_TERMPAF25

PEX_RX0AG6

NCAE18

PEX_RST_NAC7

NCAG12

NCAD20

NCAF10

PEX_TX0_NAB9

NCAG15

NCAC14

NCAC21

NCAF18

NCAC18

NCAC13

NCAF21

NCAE24

PEX_RX1AF7

PEX_TX3_NAB12

NCAF19

VGA@

34

Trang 21

SM010019400 3000ma 33ohm@100mhz DCR 0.05

NV 15x DG-06803-V03

15+55mA

PVT modify 01/13 DQSA, DQSA# reverse

change to 1.35VSDGPU

A5MUB exchange A5MUB exchange

A5MUB exchange

A5MUB exchange A5MUB exchange

MDA45

MDA57

MDA44MDA40

MDA47MDA41

MDA46MDA42

MDA33MDA35

MDA43

MDA28

MDA38MDA34

MDA39MDA36

MDA20

MDA23

MDA30MDA32

MDA21

MDA25MDA22

MDA26MDA24

MDA29

MDA2

MDA15MDA13

MDA16MDA11

MDA5MDA7

MDA14

MDA19

MDA6

MDA17MDA4

CMDA2

CMDA9

CMDA22CMDA16CMDA3

CMDA28

CMDA10

CMDA23CMDA17

CMDA31DQMA0DQMA2DQMA4DQMA6

FBA_CMD34FB_CLAMP

DQSA3DQSA1

DQSA4

CMDA27

CMDA23CMDA21

CMDA24CMDA26

CMDA10CMDA22

CMDA4CMDA12

CMDA8CMDA14

CMDA29CMDA9

CMDA13CMDA5

CMDA6CMDA7

CMDA28CMDA25

CMDA15CMDA11

CMDA[31 0] 25,26,27,28

DQMA[3 0] 25,26

DQMA[7 4] 27,28

CLKA0 25,26CLKA0# 25,26CLKA1# 27,28CLKA1 27,28

MDA[15 0]

25,26

MDA[63 48]

27,28MDA[47 32]

27,28MDA[31 16]

+1.5VSDGPU

+1.5VSDGPU+1.5VSDGPU

+1.5VSDGPU +1.5VSDGPU

+1.5VSDGPU+1.5VSDGPU

+1.5VSDGPU

Title

@12

R202260.4_0402_1% 1 @ 2

@12

C2084.1U_0402_16V7K

@12

C2092.1U_0402_16V7K

@12

L2002CHILISIN PBY160808T-330Y-N

VGA@

12

@12

C2090.1U_0402_16V7K

@12

C2085.1U_0402_16V7K

@12

R202810K_0402_5%1 VGA@ 2

@12

GM108-ES-S-A1_FCBGA595

@

FBA_D00E18FBA_D01F18FBA_D02E16FBA_D03F17FBA_D04D20FBA_D05D21FBA_D06F20FBA_D07E21FBA_D08E15FBA_D09D15FBA_D10F15FBA_D11F13FBA_D12C13FBA_D13B13FBA_D14E13FBA_D15D13FBA_D16B15FBA_D17C16FBA_D18A13FBA_D19A15FBA_D20B18FBA_D21A18FBA_D22A19FBA_D23C19FBA_D24B24FBA_D25C23FBA_D26A25FBA_D27A24FBA_D28A21FBA_D29B21FBA_D30C20FBA_D31C21FBA_D32R22FBA_D33R24FBA_D34T22FBA_D35R23FBA_D36N25FBA_D37N26FBA_D38N23FBA_D39N24FBA_D40V23FBA_D41V22FBA_D42T23FBA_D43U22FBA_D44Y24FBA_D45AA24FBA_D46Y22FBA_D47AA23FBA_D48AD27FBA_D49AB25FBA_D50AD26FBA_D51AC25FBA_D52AA27FBA_D53AA26FBA_D54W26FBA_D55Y25FBA_D56R26FBA_D57T25FBA_D58N27FBA_D59R27FBA_D60V26FBA_D61V27FBA_D62W27FBA_D63W25

FB_VREF_PROBED23

FBA_CMD34F22

FBA_CMD35J22

FB_PLLAVDD_2P22

@12

C2091.1U_0402_16V7K

@12

Trang 22

For GC62.0 use N14x for CEC ,NC N15x for GPIO8

N16S-GT

0x1 (SA000077K20) Micron MT41J256M16HA-093G:E0x4 (SA000076P20) Samsung K4W4G1646D-BC1A0x9 (SA00008DN10) Hynix H5TC4G63CFR-N0C

1GHz

N C

0xC (SA00008DN10) Hynix H5TC4G63CFR-N0C

0x2 (SA000076P20) Samsung K4W4G1646D-BC1A

PU 4.99K

Dual Rank

Singal RankRANK

256Mx16x42GB0x5 (SA00008DN10) Hynix H5TC4G63CFR-N0C0x1 (SA000077K20) Micron MT41J256M16HA-093G:E

PD 10K+1.5V

VRAMVottage

+1.35V

256Mx16x42GB

256Mx16x84GB

900MHz

0x2 (SA00008DN10) Hynix H5TC4G63CFR-N0C

0x5 (SA000076P20) Samsung K4W4G1646D-BC1A0x4 (SA000077K20) Micron MT41J256M16HA-093G:E1GHz

0x4 (SA000077K20) Micron MT41J256M16HA-093G:E0x5 (SA000076P20) Samsung K4W4G1646D-BC1A

0xE (SA00008DN10) Hynix H5TC4G63CFR-N0C

2GB

0xC (SA000076P20) Samsung K4W4G1646D-BC1A0xD (SA000077K20) Micron MT41J256M16HA-093G:E0xA (SA00008DN10) Hynix H5TC4G63CFR-N0CSingal Rank

900MHz 256Mx16x84GB900MHz

Dual RankSingal Rank

STRAP4 ->

ROM_SO

ROM_SI pull down 15kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x2ROM_SI pull down 10kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x1ROM_SI pull down 25kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x4ROM_SI pull up 35kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0xEROM_SI pull up 30kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0xDROM_SI pull down 30kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x5ROM_SI pull up 25kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0xCROM_SCLK ->

N16SGT Option Component

ROM_SI pull down 4.99kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x0ROM_SI pull down 10kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x1ROM_SI pull down 15kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x2ROM_SI pull down 20kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x3ROM_SI pull down 25kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x4ROM_SI pull down 30kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x5

X76629BOL01 X76629BOL02 X76629BOL03

X76629BOL04 X76629BOL05 X76629BOL06

STRAP2STRAP0

STRAP4

ROM_SOROM_SCLK

ROM_SIROM_SOROM_SCLK

VCCSENSE_VGA

VSSSENSE_VGA

STRAP2STRAP4STRAP0SYS_PEX_RST_MON#

MULTI_STRAP_REF0_GND

JTAG_TCK_VGA

JTAG_RST

JTAG_TDIJTAG_TDOTESTMODE

VCCSENSE_VGA 55

VSSSENSE_VGA 55

SYS_PEX_RST_MON# 20

+3VSDGPU_MAIN+3VSDGPU_AON

Title

R20374.99K_0402_1%

@

NCT3

NCAD3

NCP4

NCT4

NCAE1

NCN1NCM1

NCJ5

NCN2

NCU4

NCY3NCAA2

NCT1

NCH4

NCAB3

NCR1

NCAB1

NCJ2

NCAD1

NCY4NCAC3

NCAA4

NCK1

NCAB4

NCR3

NCJ3

NCR4

NCL3

NCN3

NCN5NCP3

NCAB5

NCR2

NCT5

NCAA1

NCL4

NCAB2NCAD2

NCJ4NCK4

NCM3

NCJ1

NCM2

NCR5

NCAC4

NCK2

NCAD5

NCK3

NCN4

NCH3

NCK5

NCAA5

NCU3

NCAD4

NCM5

NCT2

NCAA3

NCM4

NCV3NCV4

R203310K_0402_1%

@

R20304.99K_0402_1%

SGT@

R20324.99K_0402_1%

@

T3PAD@

R2039 VGM@ 45.3K_0402_1%SD034453280

T1PAD@

R203530K_0402_1%

@

R204015K_0402_1%

@

R20414.99K_0402_1%

@

R203934.8K_0402_1%

@

R20444.99K_0402_1%

X76@

R20464.99K_0402_1%

SGT@

R20454.99K_0402_1%

SGT@

R20364.99K_0402_1%

@

Trang 23

Under GPU Near GPU

Near GPU

NV 15x DG-06803-V03

1.275A 3.24A

286mA

56mA

Near GPU change to 1.35VSDGPU

NCP6

NCR6

NCH6

NCW7

NCN7

NCK7

NCR7

FBVDDQ_01B26FBVDDQ_02C25FBVDDQ_03E23FBVDDQ_04E26FBVDDQ_05F14FBVDDQ_06F21FBVDDQ_08G14FBVDDQ_09G15FBVDDQ_10G16FBVDDQ_11G18FBVDDQ_12G19FBVDDQ_13G20FBVDDQ_14G21FBVDDQ_AONH24FBVDDQ_AONH26FBVDDQ_AONJ21FBVDDQ_AONK21FBVDDQ_19L22FBVDDQ_20L24FBVDDQ_21L26FBVDDQ_22M21FBVDDQ_23N21FBVDDQ_24R21FBVDDQ_25T21FBVDDQ_26V21FBVDDQ_27W21

NCT6

IFPD_RSETU6

NCK6

FBVDDQ_07G13

NCJ6

NCM7

IFPD_PLLVDD_2T7

NCJ7

Trang 24

@

VDD_001K10VDD_002K12VDD_003K14VDD_004K16VDD_005K18VDD_006L11VDD_007L13VDD_008L15VDD_009L17VDD_010M10VDD_011M12VDD_012M14VDD_013M16VDD_014M18VDD_015N11VDD_016N13VDD_017N15VDD_018N17VDD_019P10VDD_020P12

@

GND_001A2GND_002A26GND_003AB11GND_004AB14GND_005AB17GND_006AB20GND_007AB24GND_008AC2GND_009AC22GND_010AC26GND_011AC5GND_012AC8GND_013AD12GND_014AD13GND_015AD15GND_016AD16GND_017AD18GND_018AD19GND_019AD21GND_020AD22GND_021AE11GND_022AE14GND_023AE17GND_024AE20GND_025AF1GND_026AF11GND_027AF14GND_028AF17GND_029AF20GND_030AF23GND_031AF5GND_032AF8GND_033AG2GND_034AG26GND_035B1GND_036B11GND_037B14GND_038B17GND_039B20GND_040B23GND_041B27GND_042B5GND_043B8GND_044E11GND_045E14GND_046E17GND_047E2GND_048E20GND_049E22GND_050E25GND_051

GND_054H23

GND_055H25

Trang 25

RST A14

CMD22 CMD23

CMD30

CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD15

Mode E

CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD16 CMD17 CMD18 CMD19 CMD20

A11 CAS*

A10

BA1 A13 A1

A5 A2

BA2 WE*

A8 A0

A1 A3

A10

RAS*

A0

A14 ODT

BA0

A7 A4 A6

ODT CS1*

Group1Group2

CMDA4CMDA5CMDA6CMDA7

CMDA8

CMDA9CMDA10

CMDA11

CMDA12

CMDA13CMDA14

CMDA15

CMDA20

CMDA21CMDA22

CMDA23CMDA24

CMDA25CMDA26

CMDA27

CMDA28

CMDA29

CMDA8

CMDA9CMDA10

CMDA12

CMDA21CMDA22

CMDA23CMDA24

CMDA25CMDA26

CMDA0CMDA3

CMDA11CMDA13

CMDA15CMDA27

CMDA28

CLKA0#

CLKA0CMDA29

CMDA20

DQMA0DQSA0

DQSA#0

CMDA0CMDA16CMDA20

MDA6MDA4MDA5MDA7

MDA27MDA26

MDA25MDA24

MDA12MDA9MDA14MDA13MDA15MDA8

MDA17

DQSA[7 0]

21,26,27,28DQSA#[7 0]

21,26,27,28DQMA[7 0]

21,26,27,28MDA[63 0]

21,26,27,28CMDA[30 0]

21,26,27,28

CLKA021,26

VGA@

1

2

R2081243_0402_1%

H5TQ2G63BFR-11C_FBGA96

X76@

WEL3RASJ3CASK3CS/CS0L2CKE/CKE0K9CKJ7CKK7

DQSUB7

BA0M2BA1N8

A2P3A3N2A4P8A5P2A6R8A7R2A8T8A9R3A10/APL7A11R7

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3E7 DML

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3 DMLE7

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

Trang 26

Lower Rank 1 TOP SIDE VRAM DDR3 chips

0 31 32 63 ODT

Rank1 Rank0

BA1

A11 A11 CKE CS1*

A8 A8

A12 A12 A0 A12 A12

A8

RAS*

A2 A2 A0

A14 A14 A13

RAS* RAS*

CAS*

A13 A13 A3 A3

CKE CS1* ODT ODT

A10 A10 A4

BA0 BA0 BA0 WE*

A9 A6 A9 A7

CMD22

A14

RST

CMD23 CMD25 CMD24

CMD30 CMD29 CMD28 CMD27 CMD26

Mode E Address

CMD15

32 63

CMD3 CMD2 CMD1 CMD0 0 31

CMD6 CMD5 CMD4

CMD10 CMD9 CMD8 CMD7

CMD17 CMD16

CMD20 CMD19 CMD18

CAS*

A11

A7 CMD21

BA1

A10 A2 A5

A1 A13

A2

WE*

BA2

A11 CS0*

BA2 A5

A4 A7

Default Pull-downCommand Bit

10kCKE

RSTNot Available

10kCS* No Termination

Group0Group3

ZQ3CMDA20

DQSA1

DQMA1

DQSA#1DQSA2

DQSA#2DQMA2

CMDA29CMDA6CMDA30

CLKA0CLKA0#

CMDA3

CMDA0CMDA11CMDA25

CMDA20

CMDA9CMDA24CMDA13CMDA22CMDA5CMDA23CMDA4CMDA14

CMDA29CMDA6CMDA30

CLKA0CLKA0#

CMDA3

CMDA0CMDA11CMDA25

DQSA0

DQMA3DQSA3

DQMA0

MDA1MDA2MDA3MDA0

MDA30MDA28MDA29MDA31

MDA9MDA12MDA14MDA8MDA15MDA13

MDA19

MDA22MDA23

MDA16

MDA17

DQSA#[7 0]

21,25,27,28DQSA[7 0]

21,25,27,28

CMDA[30 0]

21,25,27,28MDA[63 0]

21,25,27,28DQMA[7 0]

21,25,27,28

CLKA021,25CLKA0#

21,25

+MEM_VREFCA025

+MEM_VREFDQ025

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3E7 DML

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3 DMLE7

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

Trang 27

Upper Rank 0 BOT SIDE

ODT

Rank1 Rank0

BA1

A11 A11 CKE CS1*

A8 A8

A12 A12 A0 A12 A12

A8

RAS*

A2 A2 A0

A14 A14 A13

RAS* RAS*

CAS*

A13 A13 A3 A3

CKE CS1* ODT ODT

A10 A10 A4

BA0 BA0 BA0 WE*

A9 A6 A9 A7

CMD22

A14

RST

CMD23 CMD25 CMD24

Mode E Address

CMD15

32 63

CMD6 CMD5 CMD4

CMD17 CMD16

CMD20 CMD19 CMD18

CAS*

A11

A7 CMD21

BA1

A10 A2 A5

BA2

A3

BA1 CAS*

BA2 A5

A4 A7

10kCKE

RSTNot Available

Group5Group6

Group7Group4

DQSA6

DQMA6

DQSA#6

CMDA7CMDA24CMDA22CMDA6CMDA26CMDA5CMDA21CMDA8CMDA25CMDA9CMDA12

CMDA29CMDA27

CMDA19

CMDA15

CMDA20

CMDA16CMDA11

CMDA29CMDA27

CMDA19

CMDA15CMDA16CMDA11

+MEM_VREFDQ1+MEM_VREFCA1

MDA50

MDA53MDA55MDA52

MDA51MDA48MDA49

MDA54

MDA63MDA58MDA56

MDA60MDA57MDA59

MDA61MDA62

MDA37

MDA39MDA36

MDA38

DQSA[7 0]

21,25,26,28DQSA#[7 0]

21,25,26,28DQMA[7 0]

21,25,26,28MDA[63 0]

21,25,26,28CMDA[30 0]

21,25,26,28

CLKA121,28

96-BALLSDRAM DDR3U2008

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3 DMLE7

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3 DMLE7

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

VGA@

Trang 28

Upper Rank 1 TOP SIDE VRAM DDR3 chips

0 31 32 63 ODT

Rank1 Rank0

BA1

A11 A11 CKE CS1*

A8 A8

A12 A12 A0 A12 A12

A8

RAS*

A2 A2 A0

A14 A14 A13

RAS* RAS*

CAS*

A13 A13 A3 A3

CKE CS1* ODT ODT

A10 A10 A4

BA0 BA0 BA0 WE*

A9 A6 A9 A7

CMD22

A14

RST

CMD23 CMD25 CMD24

Mode E Address

CMD15

32 63

CMD6 CMD5 CMD4

CMD17 CMD16

CMD20 CMD19 CMD18

CAS*

A11

A7 CMD21

BA1

A10 A2 A5

A1 A13

A2

WE*

BA2

A11 CS0*

BA2 A5

A4 A7

10kCKE

RSTNot Available

Group5Group6

Group7Group4

CMDA29

CMDA10CMDA9

CMDA14CMDA5

CMDA7CMDA8

CMDA4

CMDA19

CMDA11CMDA16

CMDA15

CMDA20CMDA17

CMDA22CMDA24

CMDA23CMDA13

CMDA14CMDA5

CMDA7CMDA8

CMDA4

CMDA30CMDA6CMDA29

CMDA11CMDA16

CMDA15CMDA17

DQSA7

DQMA7

DQSA#7DQSA4

DQSA#4

DQMA4

DQMA5DQSA5

DQMA6

DQSA#6DQSA6

MDA48MDA51

MDA63MDA61MDA59

MDA60MDA57

MDA56MDA58

MDA42MDA43

MDA44MDA46MDA45

MDA38

MDA39MDA36

MDA37

DQSA#[7 0]

21,25,26,27DQSA[7 0]

21,25,26,27

CMDA[30 0]

21,25,26,27MDA[63 0]

21,25,26,27DQMA[7 0]

21,25,26,27

CLKA121,27CLKA1#

21,27

+MEM_VREFCA127

+MEM_VREFDQ127

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3 DMLE7

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

VGA@

96-BALLSDRAM DDR3U2010

X76@

DQSUB7

BA0M2BA1N8

ZQ/ZQ0L8RESETT2

DQSLF3

DMUD3 DMLE7

DQSLG3

ODT/ODT0K1

A0N3A1P7

A12N7

BA2M3

VREFDQH1

NCZQ1L9

Trang 29

LED PANEL Conn.

USB20_P7

SOC_BKL_PW MBKOFF#

EDP_HPD

USB20_N7_CAMERA

EDP_AUXN_CEDP_AUXP_CEDP_TXP0_CEDP_TXP1_C

TS_ENUSB20_P6USB20_N6I2C_0_SCLI2C_TS_INT#

I2C_TS_RST#

EDP_TXP2_C

EDP_TXN3_CEDP_TXP0_C

EDP_TXP1_CEDP_TXN2_CEDP_TXN3_C

EDP_AUXP_CEDP_AUXN_C

EDP_AUXN_CEDP_AUXP_C

USB20_N712USB20_P712

I2C_0_SDA11I2C_0_SCL11USB20_P612USB20_N612

I2C_TS_INT#

6I2C_TS_RST#

+INVPW R_B+

+19VB+LCDVDD

+3VS

+5VS

+TS_PW R+3VS

+3VS

Title

@

C3674.7U_0603_6.3V6K

1

2

C368.1U_0402_16V7K

@1

2

C3711 2 1U_0402_16V7K

C375.1U_0402_16V7K1

@1

@EMC@

1

2U8

SY6288C20AAC_SOT23-5

OUT 1

OC 3GND 2

12C3741 2 1U_0402_16V7K

L11HCB2012KF-221T30_0805EMC@

C3881 2 1U_0402_16V7K

L27DLW 21HN900HQ2L_4P

@EMC@

1 1

4 43

3

2

2R82 1 @ 2 0_0603_5%

C3871 2 1U_0402_16V7K

C528 1 2 220P_0402_50V7K@EMC@

JEDP1

E-T_0871K-F40N-00LCONN@

C3761 2 1U_0402_16V7KC3771 2 1U_0402_16V7K

R6142 @ 1 100K_0402_5%

R4271 @ 2 0_0402_5%

C3691 2 1U_0402_16V7K

Trang 30

Enable active DDC buffer;

Internal pull down at ~150KΩ , 3.3V I/O

L: default, passive DDC pass-through

H: active DDC buffer with internal pull

up2.36K resistor

M: active DDC buffer without internal pull

up resistor

Receiver equalization setting;

Internal pull down at ~150kΩ , 3.3V I/O.

L: programmable EQ for channel loss up to 5.3dB H: programmable EQ for channel loss up to 10dB

Output pre-emphasis setting;

Internal pull down at ~150kΩ , 3.3V I/O.

L: no pre-emphasis H: 1.6dB pre-emphasis

W=40mils

Intel Sugesstion HPD_SNK with Internal PD 150K

HDMI_R_D2-HDMI_SCLKHDMI_SDATA

HDMI_C_TX1-HDMI_C_TX0+

HDMI_C_TX0-HDMI_C_CLK+

HDMI_C_CLK-ALS_TX2+

ALS_TX2-ALS_TX1+

ALS_TX1-ALS_TX0+

ALS_TX0-ALS_CLK+

ALS_CLK-HDMI_ISETHDMI_HPD

SOC_DP2_CTRL_DATA

HDMI_BUF

HDMI_PRE

HDMI_EQHDMI_DCIN_EN

HDMI_DCIN_EN

HDMI_CFGHDMI_CFG

HDMI_PRE

HDMI_ISETHDMI_BUF

HDMI_EQ

SOC_DP2_CTRL_CLK

HDMI_HPD

HDMI_SDATAHDMI_SCLK

SOC_DP2_HPD

SOC_DP2_N06SOC_DP2_P06

SOC_DP2_HPD 6

SOC_DP2_CTRL_CLK 6SOC_DP2_CTRL_DATA 6

4

C378.1U_0402_16V7K1

2

R374 1 @ 20_0402_5%

R2554 1 @ 20_0603_5%

R10514.7K_0402_5%

@

R10504.7K_0402_5%

OUT_D1- 26OUT_D1+ 27

OUT_D0- 24OUT_D0+ 25

OUT_CLK- 21OUT_CLK+ 22

SCL_SRC 38SDA_SRC 39

SCL_SNK 32SDA_SNK 33

HPD_SRC 3

NC_1 12NC_2 15NC_3 34NC_4 37

GND 35EPAD 41

@

L56WCM2012F2S-900T04_0805

4

R10584.7K_0402_5%

JHDMI1

ACON_HMRB4-AK120CCONN@

GND 20GND 21GND 22GND 23

Tiêu đề	Acer Aspire E5 474G Compal LA C611P Rev 1 0 Schematic
Trường học	Compal Electronics, Inc.
Thể loại	Schematic Document
Năm xuất bản	2015
Thành phố	Taipei

Định dạng
Số trang	60
Dung lượng	2,22 MB