Acer aspire a515 51g compal LA e891p rev 1a схема

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Power SequenceCustom Title Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF

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2017.06.12 Rev: 1A LA-E891P

Compal Project Name : C5V01 / D7W01

File Name : LA-E891P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

Cover SheetCustom

Monday, June 12, 2017

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(KBL-RU_4+2) Intel Kabylake U

page 29

3.3V 24MHz

CMOS Camera

USB 3.0 conn x1

page 30

ENE KB9022

page 31 page 26

SATA3.0

SATA HDD Conn

port 7

LAN(GbE) Realtek 8411B

SPI

page 9

SPI ROM 64Mb

Quad Core + GT2

PCIE 3.0 x4 8GT/s Port 9-12

page 25

Int Speaker

on Sub/B UAJ

DDR4-ON BOARD 4G 8Gbx16

LS-E892 Hall Sensor/B

page 31

SATA CDROM Conn.

SATA3.0 port 8 (SATA1)

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BOM Structure Table

+1.2V_VDDQ

ON ON +VCC_CORE

Voltage Rails

+19V_VIN

+19VB

Adapter power supply

AC or battery power rail for power circuit.

Processor IA Cores Power Rail

Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.

S0

ON ON

N/A

S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

ON ON ON

ON

OFF OFF OFF

OFF OFF OFF OFF OFF

LOW LOW LOW HIGH

HIGH HIGH

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power State

Board ID Table for AD channel

431A72BOL01

BOM Structure

43 level BOM table

+5V Always power rail

ON

SMT MB AE891 C5V01 UMA I36006U HDMI

OFF OFF

OFFON

OFF OFF

OFF

N/A N/A

ONOFFON ON*1OFFON

ON*1OFF

PCB Revision 0.1(EVT) 1.0(DVT) 1A(PVT) 1A(MP)

EC Mode Select LPC@ / ESPI@

Acer BYOC BYOC@ / NBYOC@

SDP@ / DDP@

BOM Select X76@

X76TI@ / X76PAR@

SATA Redriver Select

LAN Mode Select SWR@ / LDO@

@RF@

RF requirement

MB Stage EVT@/DVT@/PVT@/MP@

BOM Option Table

CONN@

Connector

BOM Option Table

SMT MB AE891 C5V01 UMA I3 QLYK2.2 HDMI

SMT MB AE891 C5V01 UMA I3-7100 1.4 HDMI

SMT MB AE891 C5V01 UMA I5 QLYJ2.2 HDMI

SMT MB AE891 C5V01 UMA I7 QLYH2.2 HDMI

SMT MB AE891 C5V01 UMA I3-7100 U42 HDMI

SMT MB AE891 C5V01 UMA I5 QN5D U42 HDMI

SMT MB AE891 C5V01 UMA I7 QN5C U42 HDMI

D7W01(PVT) D7W01(MP)

SMT MB AE891 C5V01 UMA I7 QN5C U42 HDMI

SMT MB AE891 D7W01 UMA I3-6006 HDMI

SMT MB AE891 D7W01 UMA QNEF HDMI

SMT MB AE891 D7W01 UMA QNBF HDMI

Security Classification Compal Secret Data

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC

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+VCC_CORE NCP81151MNTBG

+VCC_SA NCP81253MNTBG

(PU9004)

+1.2VP RT8207KGQW

(PU402)

5V_EN

JUMP (PJ501) JUMP (PJ502)

+1.2V_VDDQ

+0.6VS_VTT

JUMP (JPC1,JPC2) +1.2V_VDDQ_CPU

R-Short (RC208) +1.2V_VDDQC R-Short

(RC141) +1.2V_VCCSFR_OC

JUMP

SY6288C20AAC (US21)

SY8288RAC (PU601)

R-Short

R-Short (RC172) +3VALW_1.8VALW_PGPPD R-Short

(RC167) +3VALW_PGPPE R-Short

SY6288C20AAC

WLAN_ON

EM5209VF (UQ1)

SUSP#

+3VS_OUT JUMP (JPQ1) +3VS

EM5209VF (UQ1)

SUSP#

+5VS_OUT

R-Short (RC178) +1.8VS_3VS_PGPPA

SY6288C20AAC (UX1)

SPOK

+1.8VALWP JUMP (PJ702) +1.8VALW_PRIM EM5209VF (UC5) +1.8VS R-Short (RA6) +1.8VS_VDDA

R-Short (RC148) +1.0VALW_APLL JUMP

(RC169) +1.0VALW_CLK6_24TBT R-Short

(RC164) +1.0VALW_VCCCLK2 R-Short

(RC190) +1.0VALW_CLK4_F100OC R-Short

(RC152) +1.0VALW_CLK5_F24NS

+1.0VALW_MPHYAON R-Short

(RC175) EM5209VF

AOZ1336 (UC8) +1.0VS_VCCSTG_IO R-Short (RC188) +1.0VS_VCCSTG

R-Short (RC143) +1.0V_VCCSFR

R-Short (RC209) +1.0VALW_MPHYGT R-Short

(RC149) +1.0VALW_AMPHYPLL R-Short

(RC176) +1.0VALW_SRAM R-Short

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Charger

2.2K 2.2K

79

80 SCL2

SDA2

7

6 77

78

CONN BATTERY

0x16

Address(7 bit)

I2C Address Table

SMBUS_Routing_TableCustom

Monday, June 12, 2017

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+1.8VALW_PG +1.8VALW_PRIM

VR_PWRGD

PLT_RST#

PCH_PWROK (SYS_PWROK) VR_ON

+VCCPRIM_CORE/+1.0VALW_PRIM

+1.0V_VCCSTU

+1.0VS_VCCSTG

+VCC_SA EC_VCCST_PG

+VCC_CORE / +VCC_GT H_CPUPWRGD

+RTCVCC SOC_RTCRST#

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns tCPU00 Min : 1 ms

tPLT05 Min : Platform dependent

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Power SequenceCustom

Title

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Rev_0.53

DDPB_CTRLDATA

DDPC_CTRLDATA

Display Port B/C Detected

NC =Port is not detected.

PU =Port is detected

Functional Strap Definitions

#543016 PDG2.0 P.873 PROC_POPIRCOMP/PCH_OPIRCOMP

PD 50ohm

#543016 PDG2.0 P.844

#544669 CRB1.1 P.52 EDRAM_OPIO_RCOMP/EOPIO_RCOMP

PD 50ohm

#545659 PCH EDS1.51 P.131 SCI capability is available on all GPIOs, while NMI and SMI capability is available on only select GPIOs.

Below are the PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23

‧ GPP_C 23 : 22

‧ GPP_ D 4 : 0

‧ GPP_E 8 : 0 , GPP_E 16 : 13

‧

#543016 PDG2.0 P.225

COMPENSATION PU for eDP

Trace width=5 mils,Spacing=25mil,Max length=600mils

#543016 PDG2.0 P.857

PU 1K to VCCST

EC_SCI# SOC internal PU

Reserved CATERR# for sight i ngs i ss ue c heck

For Intel debug, place to CPU side.

H_PECI

CPU_POPIRCOMPPCH_OPIRCOMPEDRAM_OPIO_RCOMPEOPIO_RCOMP

CPU_XDP_TCK0

SOC_XDP_TMSSOC_XDP_TRST#

SOC_XDP_TDISOC_XDP_TDO

CPU_XDP_TCK0SOC_XDP_TMSSOC_XDP_TRST#

PCH_JTAG_TCK1SOC_XDP_TDISOC_XDP_TDO

H_PROCHOT#_RH_THERMTRIP#

XDP_BPM#0H_THERMTRIP#

CPU_XDP_TCK0

SOC_XDP_TRST#

SOC_DP1_HPDSOC_DP1_CTRL_DATA

1ASKL-U(1/12)DDI,MSIC,XDP,EDPCustom

@

T194@T195@

CC531000P_0402_50V7KESD@

1 OF 20UC1A

EDP_TXP[0] C46EDP_TXP[1] C45EDP_TXP[2] B45EDP_TXP[3] B47

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#543016 PDG2.0 P.190 Trace width/Spacing >= 20mils Place componment near SODIMM

DDR_VTT_CNTL to DDR VTT supplied ramped

<35uS (tCPU18)

#543016 PDG2.0 P.139 W=12-15 Space= 20/25 L=500mil

2015MOW02, Can't install Cap on DRAMRST

Intel DOC: 549352

Change PN to SA00007WE00 01/11

DVTPre-MP Update DAZ / PCB PN 03/27

Skylake

PVT change to 121 ohm

U42D7W01 Pre-MP Update DAZ / PCB PN 06/12

+0.6V_B_VREFCADDR_PG_CTRL

DDR_A_D57DDR_A_D59

DDR_A_D48

DDR_A_D56DDR_A_D54DDR_A_D51DDR_A_D53DDR_A_D49

DDR_A_D61

DDR_A_D55DDR_A_D52

DDR_A_D60DDR_A_D62

DDR_A_D7

DDR_A_D13DDR_A_D8

DDR_A_D15DDR_A_D11

DDR_A_D23

DDR_A_D30

DDR_A_D24

DDR_A_D28DDR_A_D31DDR_A_D27

DDR_A_D18

DDR_A_D22

DDR_A_D29

DDR_A_D20DDR_A_D16

DDR_A_D25

DDR_A_D47DDR_A_D39

DDR_A_D33DDR_A_D35

DDR_A_D42

DDR_A_D38DDR_A_D40

DDR_A_D34DDR_A_D36

DDR_A_D43DDR_A_D37

DDR_A_D45DDR_A_D41

DDR_A_D46DDR_A_D44DDR_A_D32

DDR_A_ODT0DDR_A_MA5DDR_A_MA6

DDR_A_CLK0DDR_A_CLK#0

DDR_A_CLK1DDR_A_CLK#1

DDR_A_MA8

DDR_A_CKE1

DDR_A_CS#1

DDR_A_MA7DDR_A_MA12DDR_A_ACT#

DDR_A_BG1DDR_A_MA13DDR_A_MA14DDR_A_BA0DDR_A_MA2DDR_A_BA1DDR_A_MA10DDR_A_MA1DDR_A_MA3

DDR_A_DQS#0DDR_A_DQS0DDR_A_DQS#1DDR_A_DQS1DDR_A_DQS#2DDR_A_DQS2DDR_A_DQS#3DDR_A_DQS#4DDR_A_DQS3DDR_A_DQS4DDR_A_DQS#5DDR_A_DQS5DDR_A_DQS#6DDR_A_DQS6DDR_A_DQS#7DDR_A_DQS7

DDR_B_D3

DDR_B_D8

DDR_B_D13DDR_B_D4

DDR_B_D14

DDR_B_D7DDR_B_D10

DDR_B_D2DDR_B_D0

DDR_B_D15

DDR_B_D6DDR_B_D9

DDR_B_D12

DDR_B_D19

DDR_B_D29DDR_B_D20

DDR_B_D31

DDR_B_D17

DDR_B_D25

DDR_B_D28DDR_B_D30DDR_B_D27DDR_B_D22DDR_B_D18

DDR_B_D24DDR_B_D16

DDR_B_D32DDR_B_D34

DDR_B_D47

DDR_B_D35

DDR_B_D38DDR_B_D41DDR_B_D44

DDR_B_D56

DDR_B_D60

DDR_B_D54

DDR_B_D57DDR_B_D53

DDR_B_D62DDR_B_D51

DDR_B_D61DDR_B_D58

DDR_B_MA5DDR_B_MA6DDR_B_MA7DDR_B_MA12DDR_B_ACT#

DDR_B_BG1DDR_B_MA13DDR_B_MA14DDR_B_BA0DDR_B_MA2DDR_B_BA1DDR_B_MA10DDR_B_MA1DDR_B_MA3DDR_B_DQS#0DDR_B_DQS0DDR_B_DQS#1DDR_B_DQS1DDR_B_DQS#2DDR_B_DQS2DDR_B_DQS#3DDR_B_DQS#4DDR_B_DQS3DDR_B_DQS4DDR_B_DQS#5DDR_B_DQS5DDR_B_DQS#6DDR_B_DQS6DDR_B_DQS#7DDR_B_DQS7

DDR_B_CLK1DDR_B_CLK#1DDR_B_CLK0DDR_B_CKE0

DDR_DRAMRST#

DDR_A_ALERT#

DDR_B_PAR+0.6V_A_VREFCA

DDR_B_MA5 <20>DDR_B_MA9 <20>DDR_B_MA6 <20>DDR_B_MA8 <20>DDR_B_MA7 <20>DDR_B_MA12 <20>DDR_B_MA11 <20>DDR_B_ACT# <20>DDR_B_BG1 <20>

DDR_B_MA2 <20>DDR_B_MA10 <20>DDR_B_MA1 <20>DDR_B_MA0 <20>DDR_B_MA3 <20>DDR_B_DQS#0 <20>DDR_B_MA4 <20>DDR_B_DQS0 <20>DDR_B_DQS#1 <20>DDR_B_DQS1 <20>DDR_B_DQS#2 <20>DDR_B_DQS2 <20>DDR_B_DQS#3 <20>DDR_B_DQS3 <20>DDR_B_DQS#4 <20>DDR_B_DQS4 <20>DDR_B_DQS#5 <20>DDR_B_DQS5 <20>DDR_B_DQS#6 <20>DDR_B_DQS6 <20>DDR_B_DQS#7 <20>DDR_B_DQS7 <20>DDR_B_MA13 <20>

DDR_B_CLK#0 <20>DDR_B_CLK0 <20>DDR_B_CLK#1 <20>DDR_B_CLK1 <20>DDR_B_CKE0 <20>DDR_B_CKE1 <20>

DDR_B_CS#0 <20>DDR_B_CS#1 <20>DDR_A_ODT0 <19>

DDR_B_ODT0 <20>DDR_B_ODT1 <20>

SM_PG_CTRL <38>

DDR_A_ALERT# <19>

DDR_B_PAR <20>DDR_A_BG1 <19>

+0.6V_B_VREFCA

+1.2V_VDDQ+3VS+0.6V_A_VREFCA

Title

SA0000A37N0

UC1

KBL i7 U42QN5C@

SA0000AQZ10UC1

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AY55

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AU48

DDR0_CKE[0] BA56DDR0_CKE[1] BB56

DDR0_CKE[3] AY56

DDR0_CKN[0] AU53DDR0_CKN[1] AU55DDR0_CKP[0] AT53DDR0_CKP[1] AT55

DDR0_CS#[0] AU45DDR0_CS#[1] AU43

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AY50DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] BB50DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AT50

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA54DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AW54

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU46DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AY54DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# BA55

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AY51

DDR0_MA[3] BA50DDR0_MA[4] BB52

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BA51DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] BA52DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AW52DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AY52DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BB54

DDR0_ODT[0] AT45DDR0_ODT[1] AT43

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU50DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AT46

DDR0_DQSP[0] AM69DDR0_DQSP[1] AT70DDR0_DQSP[2]/DDR0_DQSP[4] AY64DDR0_DQSP[3]/DDR0_DQSP[5] BA60DDR0_DQSP[4]/DDR1_DQSP[0] AY38DDR0_DQSP[5]/DDR1_DQSP[1] BA34DDR0_DQSP[6]/DDR1_DQSP[4] AY30DDR0_DQSP[7]/DDR1_DQSP[5] BA26

ZZZ

HDMI LOGO45@

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AP52

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY43

DDR1_CKE[0] AN56DDR1_CKE[1] AP55DDR1_CKE[2] AN55DDR1_CKE[3] AP53

DDR1_CKN[0] AN45DDR1_CKN[1] AN46DDR1_CKP[0] AP45DDR1_CKP[1] AP46

DDR1_CS#[0] BB42DDR1_CS#[1] AY42

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BA46DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AY46DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AW46

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN48DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN50

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] BA43DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AN52DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN53

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AY47

DDR1_MA[3] BB46DDR1_MA[4] BA47

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AY48DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BA48DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP48DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] BB48DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AP50

DDR1_ODT[0] BA42

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] AW44DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AY44

DDR1_DQSP[0]/DDR0_DQSP[2] AH65DDR1_DQSP[1]/DDR0_DQSP[3] AG70DDR1_DQSP[2]/DDR0_DQSP[6] AR65DDR1_DQSP[3]/DDR0_DQSP[7] AR60DDR1_DQSP[4]/DDR1_DQSP[2] AR38DDR1_DQSP[5]/DDR1_DQSP[3] AR32DDR1_DQSP[6] AR27DDR1_DQSP[7] AR21

UC1

KBL i7-7500U HDCP2.2 MPI7750022@

SA0000A34L0

ZZZ1

PCB 20X LA-E891P REV1A MB 2PCB@

RC38121_0402_1%SDP@

@T242

SA0000AWC40

T243

@

RC381DDP@ 2 121_0402_1%RC391 2 80.6_0402_1%

RC161M_0402_5%

ZZZ

PCB D7W01 LA-E891P LS-E892P/E893PEA17DAZ@

DAZ24C00201

UC1

KBL i5 U42QN5D@

SA0000AR010

UC1

KBL i3-7100U HDCP2.2 MPI3710022@

SA0000A38M0

UC1

KBL i7-7500U HDCP2.2QLYH@

SA0000A34J0

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RPC5 and RC52 are close UC2

SPI ROM

SPI Touch

Strap Pin

2015MOW06 no need PU1K on SPI_IO2/IO3

Change RC144~RC147, RC45 to 15ohm when use ESPI

*

SML0ALERT# / GPP_C5 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# ) eSPI or LPC

0 = LPC is selected for EC > For KB9022/9032 Use

1 = eSPI is selected for EC > For KB9032 Only.

*

SMBALERT# / GPP_C2 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# ) TLS Conf i dent ial i ty

0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no conf i dent ial i ty).

1 = Enable Intel ME Crypto (TLS) (with conf i dent ial i ty) Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

SOC_SPI_IO2

SOC_SPI_IO2_0_R

SOC_SPI_CLKSOC_SPI_SISOC_SPI_SO

TPM_SERIRQ

SOC_SML1ALERT#

SOC_SML0CLKSOC_SML0DATASOC_SML1CLKSOC_SML1DATA

SOC_SMBCLKSOC_SMBDATASOC_SMBALERT#

SOC_SML0ALERT#

CLKOUT_LPC0LPC_FRAME#

LPC_AD2LPC_AD0LPC_AD3LPC_AD1

ESPI_RST#

SOC_SML0CLKSOC_SML0DATA

PM_CLKRUN#

SOC_SPI_IO3 SOC_SPI_IO3_0_RSOC_SPI_SI SOC_SPI_SI_0_RSOC_SPI_CLK SOC_SPI_CLK_0_RSOC_SPI_SO SOC_SPI_SO_0_R

TPM_SERIRQ

SOC_SPI_IO2SOC_SPI_IO3SOC_SPI_CLK_0_R

SOC_SMBCLK_1SOC_SMBDATA_1

SOC_SMBDATA_1SOC_SMBCLK

SOC_SMBDATA

SOC_SMBCLK_1

SOC_SPI_CS#0

SOC_SPI_SO_0_RSOC_SPI_SI_0_RSOC_SPI_CLK_0_RSOC_SPI_IO3_0_R

SOC_SML1CLKSOC_SMBCLKSOC_SML1DATASOC_SMBDATA

CLK_LPC_TPM_RPM_CLKRUN#

CC80.1U_0201_10V6K

RPC5

15_0804_8P4R_5%

18273645

UC2

W25Q64FVSSIQ_SO8 SA000039A40

GND

4

DI(IO0) 5DO(IO1)

RC112 1 2 10K_0402_5%

CC910P_0402_50V8J

@EMI@

SKL-USPI - FLASH

ACES_91960-0084N_8P-NPM

CS#

1

SO/SIO1 2WP#

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to GPIO funct i onali t y ( as i nput) If S DI O i nt erf ac e i s not used, the signals can be used as GPIOs instead

If the GPIO funct i onali t y i s al s o not us ed, t he si gnal s can be lef t as no- c onnect.

*

SPKR / GPP_B14 (Internal Pull Down):

(Sampled:Rising edge of PCH_PWROK)

TOP Swap Override

0 = Disable TOP Swap mode.

1 = Enable TOP Swap Mode.

HDA for AUDIO

Intel HD Audio link capabilit i es

> Two SDI signals to support two external codecs.

> Drivers variable requency (5MHz to 24MHz) BCLK to support:

SDO double pumped up to 48 Mb/s

SDI's single pumped up to 24 Mb/s

> Provides cadence for 44.1 kHz based sample rate output.

> Support 1.5V, 1.8V, and 3.3V modes.

HDA_SDO / I2S_TXD0 (Internal Pull Down):

(Sampled: Rising edge of PCH_PWROK )

Flash Descriptor Security Override

0 = Enable security measures def i ned i n t he Fl as h

Descriptor

1 = Disable Flash Descriptor Security (override) This

strap should only be asserted high using external

pull-up in manufacturing/debug environments ONLY

1 0 GPIO67

HDA_BIT_CLKHDA_SYNC

HDA_RST#

HDA_SDIN0HDA_SDOUT

EMMC_CMDEMMC_CLK

PCH_DMIC_CLKPCH_DMIC_DATA

DGPU_PRSNT#

HDA_SDOUTHDA_SYNCHDA_BIT_CLK

DMIC_DATA1DMIC_CLK1

SDIO/SDXC

7 OF 20UC1G

12

RC13310K_0402_5%

RC13410K_0402_5%

Trang 11

PROCPWRGD is used only for power sequence

debug and is not required to be connected to

anything on the plat f or m

WAKE# (DSX wake event)

10 KΩ pull- up t o Vcc DS W 3_3.

The pull-up is required even if PCIe* interface

is not used on the plat f or m

Change PN to SJ10000Q400

XCLK_BIASREF T:50ohm S:12/15 L:1000 Via:2

Follow 2014MOW48 Skylake U PU 2.7k ohm to 1V Cannonlake U PD 60.4 ohm

2014MOW48:

Skylake-U use 24M 50 ohm ESR Cannonlake U use 38.4M 30 ohm ESR

EC internal PU PCH internal PU

Note for VCCST_PWRGD

1 1.0V tolerance

2 PDG2.0 P.598 Figure43-5 note17: when failure events,

VCCST_PWRGD and PCH_PWROK de-assert at the same t i me

PVT Change to 1000P 02/20 PVT Change to 1000P 02/20

Pre-MP change to 33 ohm 03/28

EC_RSMRST# PCH_DPWROK

H_CPUPWRGDSYS_PWROKPCH_DPWROKSUSPWRDNACKSUSACK#

CLKREQ_PCIE#2CLK_PCIE_N2

CLKREQ_PCIE#5

SUSCLKSOC_XTAL24_INSOC_XTAL24_OUT

SOC_RTCX2SOC_SRTCRST#

SOC_RTCX1SOC_RTCX2CLKREQ_PCIE#3

PCH_PWROK_RSYS_PWROK

EC_RSMRST#

CLKREQ_PCIE#3CLKREQ_PCIE#5

CLK_PCIE_P3CLKREQ_PCIE#0

CLKREQ_PCIE#2CLKREQ_PCIE#0

SOC_XTAL24_OUT_R

SOC_XTAL24_IN_RSOC_XTAL24_IN

Title

JCMOS11 @ 2 0_0603_5%

CC166.8P_0402_50V8C

1

2

T95 @

YC232.768KHZ_9PF_X1A000141000200

RC125 0_0402_5%

@

12T92@

RC911 2 20K_0402_5%

CC130100P_0402_50V8J

11 OF 20UC1K

RC121 1 2 10K_0402_5%

T165@RC235 1U22@ 2 33_0402_1%

10K_0804_8P4R_5%

18273645CC10 1 2 1U_0402_6.3V6K

CC156.8P_0402_50V8C

1

2T185@

CC50 1000P_0402_50V7K

ESD@

12

27

36

45

Trang 12

1 1

Functional Strap Definitions

GSPI1_MOSI / GPP_B22 (Internal Pull Down):

(Rising edge of PCH_PWROK)

Boot BIOS Strap Bit

0 = SPI Mode > AAX05 Use

*

1 1

C5V01

Project_ID0 Project_ID1

Reserved D7W01

*

1 0 U22

U42

CPU_ID

Memory Down Strap

GSPI0_MOSI /GPP_B18 (Internal Pull Down):

(Rising edge of PCH_PWROK)

No Reboot

0 = Disable No Reboot mode > AAX05 Use

1 = Enable No Reboot Mode (PCH will disable the TCO

Timer system reboot feature) This function is useful

when running ITP/XDP.

Micron 4Gb

SA0000A1H20 (S IC D4 512M16 H5AN8G6NAFR-UHC FBGA ABO!) SA00009V220 (S IC D4 512M16 MT40A512M16JY-083E:B ABO!) SA00009U420 (S IC D4 512M16 K4A8G165WB-BCRC FBGA 96P ABO !)

RAM_ID2 RAM_ID3

*RAM_ID1 0

0 0 1

*RAM_ID0 0

0 0 1

PartNumber - Description

DVT

No on board memory

PVT identify U22 , U42 CPU 03/02

Add D7W01 Project ID setting

TS_ENGSPI0_MOSI

GSPI1_MOSI

UART_2_CTXD_DRXDUART_2_CRTS_DCTS

I2C_0_SCLI2C_0_SDA

I2C_1_SDAI2C_1_SCLI2C_2_SDAI2C_2_SCLI2C_3_SDAI2C_3_SCLI2C_4_SDAI2C_4_SCL

ISH_I2C0_SDAISH_I2C0_SCL

I2C_5_SDAI2C_5_SCL

ISH_I2C1_SCLISH_I2C1_SDA

ISH_I2C0_SDAISH_I2C0_SCL

PROJECT_ID1

PROJECT_ID0

I2C_0_SDAI2C_0_SCLI2C_1_SDAI2C_1_SCL

UART_2_CTXD_DRXDUART_2_CRXD_DTXD

UART_2_CRTS_DCTSUART_2_CCTS_DRTS

+1.8VS+3VS

SKL-U_BGA1356

@

GPP_A12/BM_BUSY#/ISH_GP6 AP13

GPP_A18/ISH_GP0 AY8GPP_A19/ISH_GP1 BA8GPP_A20/ISH_GP2 BB7GPP_A21/ISH_GP3 BA7GPP_A22/ISH_GP4 AY7

GPP_D15/ISH_UART0_RTS# U3

GPP_D5/ISH_I2C0_SDA M4GPP_D6/ISH_I2C0_SCL N3GPP_D7/ISH_I2C1_SDA N1GPP_D8/ISH_I2C1_SCL N2

GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD11GPP_F11/I2C5_SCL/ISH_I2C2_SCL AD12

X76@

RC20710K_0402_5%

X76@

RC21410K_0402_5%U42@

ZZZ Hynix4GBX76M01@ X76731BOL01

X76@

RC21510K_0402_5%U22@

X76@

RC21310K_0402_5%

D7W01@

SD028100280RC207 2 @ 1 10K_0402_5%

ZZZ Samsung4GBX76M02@ X76731BOL02

RC1780_0402_5%2 @ 1RC129 1 2 2.2K_0402_5%

RC22710K_0402_5%

X76@

RC1770_0402_5%2ESPI@ 1

Trang 13

NGFF WLAN+BT(Key E)

GLAN

2015MOW10, USB2_ID Connected to GND Directly

Unused OC pin need set to GPI.

M.2 SSD PCIE/SATA select pin

USB_OC1#

DEVSLP0

DEVSLP2 DEVSLP1

USB_OC2#

USB_OC3#

DEVICE CONTROL USB2 Port 1

NA NA

NA SATA_GP0 SATA_GP1 SATA_GP2 NA

NA NA

DEVSLP[2:0] Implementation DEVSLP is a host-controlled hardware signal which enables a SATA host and device to enter an ultra-low interface power state, including the possibility to completely power down host and device PHYs.

The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.

When hi gh, DEVSLP reWuests t he SATA devi ce t o ent er i nt o t he DEVSLP po wer st at e

‧ When l o w , DEVSLP reWuests t he SATA devi ce t o eWit f r o m t he DEVSLP po wer st at e

‧ and transition to active state

SATA General Purpose (SATAGP[2:0]) Signals The pr ocess or provi des t hree SATA general pur pose i nput si g nal s, SATAGP[ 2: 0] f or S KL U

‧ These signals can be configured as interlock switch inputs corresponding to a given SATA port When used as an i nt erl oc k s w it c h st at us i ndi cati on, t hi s si g nal s houl d be dri ven t o 0

‧

to indicate that the switch is closed and to a 1 to indicate that the switch is open

If mec hani cal presence s w it c hes w ill not be used on t he pl atf or m , SATAGP[ 2: 0]

‧ signals can be configured as GPP_E[2:0] GPIOs signals.

SSD_DET# (SATA_GP2) SATA Device 0 PCIE Device 1

PCIE_CTX_DRX_P5PCIE_CRX_DTX_P5

PCIE_CRX_DTX_N6

PCIE_CTX_DRX_P6

USB2_IDUSB2_VBUSSENSEUSB20_P8USB20_N4

+3VS

Title

RC119 1 2 113_0402_1%

CC60 1 2 1U_0402_16V7K

RH1610K_0402_5%

Trang 14

#543016 PDG2.0 P.750 +1.35V_VDDQ_CPU : 4x 10uF 0402 3x 22uF 0603

BSC Side PSC Side

PSC Side

BSC Side

#543016 PDG2.0 P.750 +1.35V_VDDQC : 1x 10uF

PSC Side

6.35A 2.73A

6A 0.09A 0.04A 0.04A 0.26A 0.12A

#543016 PDG2.0 P.750 +1.0V_VCCST : 1x 1uF

#543016 PDG2.0 P.750 +1.0V_VCCSFR : 1x 1uF

#543016 PDG2.0 P.750 +1.35V_VCCSFR_OC : 1x 1uF

#543016 PDG2.0 P.750 +1.0V_VCCSTG : 1x 1uF (Placeholder)

EN_1.8VSEN_1.0V_VCCSTU

+1.0VS_VCCSTG_IO

SUSP#_R1SUSP#

+1.2V_VDDQ_CPU

+1.2V_VDDQ

+1.0VS_VCCSTG

+1.0V_VCCST+1.0VS_VCCSTG+1.2V_VCCSFR_OC+1.0V_VCCSFR

+1.8VALW_VS

+1.0V_VCCSTU+1.0VALW_PRIM

+1.2V_VCCSFR_OC+1.2V_VDDQ_CPU

+1.2V_VDDQC+1.2V_VDDQ_CPU

+1.8VALW_PRIM

+1.0VS_VCCSTG

+VCCIO+1.0VALW_PRIM

+5VALW+1.0VALW_PRIM_JP

Title

CC951000P_0402_50V7K

CC1270.1U_0201_10V6K1

2RC168 1 2 49.9K_0402_1%

2

JPC8JUMP_43X39

2

T124@

SKL-UCPU POWER 3 OF 4

14 OF 20UC1N

@

CC104.1U_0402_16V7K1

2

JPC5JUMP_43X79

2

Trang 15

+CHGRTC BAT54C(VF) +RTCVCC

Power Rail Voltage

3.383V(MAX)

240 mV 3.143V Result : Pass

CC77,CC78 near AK17 (<3 mm)

CC86 near A10 (<3 mm) CC87 near K17 (<3 mm)

+1.0VALW_CLK6_24TBT+RTCVCC

+1.0VALW_APLL+1.0VALW_CLK4_F100OC

+1.0VALW_PRIM

+1.0VALW_MPHYAON

+1.0VALW_AMPHYPLL+1.0VALW_APLL

+1.0VALW_CLK5_F24NS

+1.0VALW_PRIM+3VALW_DSW

+3VALW_HDA+3VALW_SPI

+3VALW_PGPPC+3VALW_1.8VALW_PGPPD+3VALW_PGPPE+3VALW_PGPPG

+1.0VALW_SRAM

+3VALW_PRIM

+1.0VALW_PRIM+1.0VALW_APLLEBB

+3VALW_1.8VALW_PGPPA+3VALW_PGPPB

+1.0VALW_CLK6_24TBT+1.0VALW_PRIM

+1.0VALW_PRIM +3VALW_PRIM +1.8VALW_PRIM

+1.0VALW_MPHYPLL+1.0VALW_PRIM

+1.8VALW_PRIM+3VALW_1.8VALW_PGPPD +3VALW_PRIM

+RTCBATT

Title

12

CC831U_0402_6.3V6K @

12

RH1631K_0402_5%

2

CC840.1U_0201_10V6K1

2

RC2060_0402_5%1 @ 2

RC1520_0603_5%2 @ 1

CC761U_0402_6.3V6K

@12

CC681 2 1U_0402_6.3V6K

CC711 2 0.1U_0201_10V6K

RC1610_0402_5%2 @ 1

2

CC780.1U_0201_10V6K

12

DC1

CHN202UPT_SC70-3

123

12

RC1690_0402_5%2 @ 1

2

T138@

JRTC1

ACES_50271-0020N-001CONN@

12CC123

15 OF 20UC1O

SKL-U_BGA1356

@

GPP_B0/CORE_VID0 AN11GPP_B1/CORE_VID1 AN13

RC1710_0402_5%2 @ 1

RC1720_0402_5% 2 @ 1

T136@

CC12522U_0603_6.3V6M @

1

2 0_0603_5%2 @ 1 RC190

RC1670_0402_5%2 @ 1RC154 1 @ 2 0_0402_5%

RC176 1 @ 20_0603_5%

CC741U_0402_6.3V6K @

12

2

CC631U_0402_6.3V6K

@

CC861U_0402_6.3V6K @

12

RC1960_0402_5%2ESPI@ 1

RC1640_0603_5%2 @ 1

RC1620_0402_5%2 @ 1

CC721U_0402_6.3V6K

12

CC871U_0402_6.3V6K

@12

RC198 1 @ 2 0_0402_5%

RC149 1 @ 20_0603_5%

CC771U_0402_6.3V6K

12

RC175 1 @ 2 0_0402_5%

CC1031U_0402_6.3V6K

12

RC1870_0402_5%2 @ 1

CC731U_0402_6.3V6K @

12

CC61 1U_0402_6.3V6K

@

CC671U_0402_6.3V6K @

12

RC1630_0402_5%2 @ 1

CC1021U_0402_6.3V6K @

12

2RC148 1 @ 2 0_0603_5%

Trang 16

1 1

Trace Length < 25 mils

For CPU2+3e SKU

Trace Length < 25 mils

For CPU2+3e SKU

#544924 SKL EDS1.2 P.136 VCCGT U(15W)-dual core GT2 31A(MAX) 0.55-1.5V

#543016 PDG2.0 P.273

To VR

Place the PU resistors close to CPU

569110 U42/U22 common baord K52/AK52 NC

+VCC_GT_VCORE U22 > +VCC_GT U42 > +VCC_CORE

+VCC_GTX_VCORE U22 > NC U42 > +VCC_CORE

VCCGT_SENSEVSSGT_SENSE

VCCOPC_SENSEVSSOPC_SENSE

VCCEOPIO_SENSEVSSEOPIO_SENSE

SOC_SVID_CLKSOC_SVID_ALERT#

VCCGTX_SENSEVSSGTX_SENSE

@

RC17956_0402_5%

T155@

RC180220_0402_5%

T219@

SKL-UCPU POWER 1 OF 4

12 OF 20UC1L

13 OF 20UC1M

Trang 17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

17 OF 20UC1Q

16 OF 20UC1P

Trang 18

Display Port Presence Strap

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

1 : Disabled; No Physical Display Port

at t ac hed t o E mbedded Dis pl ay Port

For 2+3e Solut i on PM_ZVM#

Zero Voltage Mode: Control Signal to OPC

VR, when low OPC VR output is 0V.

PM_MSM#

Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solut i on f or OPC).

Rev_0.53

#544669 CRB1.1 P.54

#544924 SKL EDS1.2 P.125 PROC_SELECT#

This pin is for compat i bili t y w i t h f ut ur e plat f or ms It s houl d be unc onnect ed f or the processor.

CC79 near U11,U12 (<10 mm) 14MOW52, Connect U11, U12 to 1.8V for Cannonlake-U PCH compat i bili t y

568813_KBL_U42 Rev0.5

563377 Intel MOW 33

PVT 02/22

PVT 02/22 PVT 02/22

Pre-MP change to 33 ohm 03/28

Pre-MP change to 27pF 03/28

CFG16

CFG18

CFG0CFG2CFG4CFG6CFG8CFG10CFG12CFG14

SOC_XTAL24_IN_U42_RSOC_XTAL24_OUT_U42_RSOC_XTAL24_IN_U42

SOC_XTAL24_OUT_U42+1.0V_VCCST

+1.8VALW_PRIM

Title

@T171

@T169

@

T199@

T157@

RC570_0402_5%

@

SKL-URESERVED SIGNALS-1

19 OF 20UC1S

20 OF 20UC1T

@1

2T156@

RC234 1U42@ 2 33_0402_1%

RC1931K_0402_1%

12

2

T170

@

RC18549.9_0402_1%

12

T163@

T221@T215 @

T225@

Trang 19

VSSSDP DDPVSSNCBG1VSS

Follow MA51

4 as near each on board RAM device as possible

2 as near each on board RAM device as possible

RCOMP[0]

(SOC side) 200_1% 121_1%

DDR_A_BG1(RD78, Intel:549352)

1 Near SOC side

2 BO1+BO2+M small then other CMD 25mils

3 BO1+BO2 small then 800mils

RAM_ID2RAM_ID3

*RAM_ID1

0001

*RAM_ID0

0001

PartNumber - Description

No on board memory

MEMRST#

DDR_A_MA8DDR_A_MA5DDR_A_MA1

DDR_A_MA13DDR_A_MA10DDR_A_MA9DDR_A_MA11DDR_A_MA7DDR_A_MA4DDR_A_MA0

DDR_A_CLK#0DDR_A_CLK0DDR_A_CKE0DDR_A_MA14

DDR_A_DQS#1DDR_A_DQS1

DDR_A_D14DDR_A_D8DDR_A_D10DDR_A_D11

DDR_A_D13DDR_A_D9

DDR_A_D2DDR_A_D6

DDR_A_D15

DDR_A_D5

DDR_A_D7

DDR_A_ODT0DDR_A_CS#0

DDR_A_ALERT#

DDR_A_PARDDR_A_BG0DDR_A_ACT#

DDR_A_D20DDR_A_D16

DDR_A_D21

DDR_A_D27

DDR_A_D30DDR_A_D25

DDR_A_MA10DDR_A_MA13

DDR_A_MA0

DDR_A_MA4DDR_A_MA6

DDR_A_MA11DDR_A_MA9

DDR_A_MA14

DDR_A_D34DDR_A_D39

DDR_A_D36DDR_A_D35

DDR_A_MA0

DDR_A_MA4DDR_A_MA6

DDR_A_MA11DDR_A_MA9

DDR_A_MA14

DDR_A_D49DDR_A_D55

DDR_A_D48DDR_A_D54

MEMRST#

DDR_A_MA0

DDR_A_MA4DDR_A_MA6

DDR_A_MA11DDR_A_MA9

DDR_A_CKE0DDR_A_CLK0DDR_A_CLK#0

DDR_A_MA16DDR_A_ODT0DDR_A_CS#0

DDR_A_ALERT#

MEMRST#

DDR_A_DQS2DDR_A_DQS#2DDR_A_DQS#3

DDR_A_DQS#6DDR_A_DQS7DDR_A_DQS#7

DDR_A_BG1_RDDR_A_BG1

DDR_A_ALERT#

DDR_A_MA15

DDR_A_MA8

DDR_A_MA14DDR_A_CS#0

DDR_A_MA2

DDR_A_BG0DDR_A_BA1DDR_A_MA10

DDR_A_CKE0

DDR_A_MA6DDR_A_MA4

MEMRST#

DDR_DRAMRST#

DDR_A_D18

DDR_A_D22DDR_A_D19

DDR_A_D29DDR_A_D24

DDR_A_MA16DDR_A_ACT#

DDR_A_MA13DDR_A_MA11DDR_A_PAR

Title

Security Classification Compal Secret DataTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@1

K4A8G165WB-BCPB_FBGA96X76@

VSSQC9

VSSB2VSSE9VSSE1

ACT

L3

VDDB3VDDB9

VDDQ A1VDDQ A9VDDQ C1VDDQ D9

DQSU_c

A7

VDDQ G1

VSSQE8VSSQF1

VDDQ G9VDDQ J2

VSSK9VSSM9VSSN1VSST1

VDDQ F2VDDT9

VSSQ C9

VSSB2VSSE9VSSE1

ACT

L3

VDD B3VDD B9

DQSU_c

A7

VDDQ G1

VSSQ E8VSSQ F1

VDDQ G9VDDQ J2

VDDQ F2VDD T9

RD206240_0402_1%

12

VSSQC9

VSSB2VSSE9VSSE1

ACT

L3

VDDB3VDDB9

DQSU_c

A7

VDDQ G1

VSSQE8VSSQF1

VDDQ G9VDDQ J2

VDDQ F2VDDT9

SDP@

SD028000080

RD2090_0402_5%

DDP@

RD208240_0402_1%

RD210240_0402_1%

VSSQ C9

VSS B2VSS E9VSS E1

ACT

L3

VDD B3VDD B9

DQSU_c

A7

VDDQ G1

VSSQ E8VSSQ F1

VDDQ G9VDDQ J2

VSS K9VSS M9VSS N1VSS T1

VDDQ F2VDD T9

Trang 20

DDR_B_MA2

DDR_B_BG0DDR_B_BA0

DDR_B_MA3DDR_B_MA0

DDR_B_MA4DDR_B_MA6DDR_B_MA8DDR_B_MA10DDR_B_MA12DDR_B_MA14DDR_B_MA16

SOC_SMBDATA_1DDR_B_ACT#

SOC_SMBCLK_1

DDR_B_PARDDR_B_ALERT#

DDR_B_EVENT#

DDR_B_DQS8DDR_B_DQS#8

DDR_B_SA0DDR_B_SA2

DDR_B_D10DDR_B_D9DDR_B_D12DDR_B_D15DDR_B_D8DDR_B_DQS1DDR_B_DQS#1DDR_B_D1DDR_B_D7DDR_B_D5DDR_B_D3DDR_B_DQS0DDR_B_DQS#0DDR_B_D17DDR_B_D19DDR_B_D16DDR_B_D18DDR_B_DQS2DDR_B_DQS#2DDR_B_D25DDR_B_D31DDR_B_D24DDR_B_D30DDR_B_DQS3DDR_B_DQS#3DDR_B_D37DDR_B_D39DDR_B_D36DDR_B_D38DDR_B_DQS4DDR_B_DQS#4DDR_B_D41DDR_B_D46DDR_B_D40DDR_B_D43DDR_B_DQS5DDR_B_DQS#5DDR_B_D53DDR_B_D54DDR_B_D48DDR_B_D55DDR_B_DQS6DDR_B_DQS#6

DDR_B_D61DDR_B_D58DDR_B_D60DDR_B_D59DDR_B_DQS7DDR_B_DQS#7

DDR_B_BG1DDR_B_ACT#

DDR_B_ALERT#

DDR_B_PARDDR_B_BG0DDR_B_BA0

DDR_B_CKE0

DDR_B_CLK0DDR_B_CLK#0

DDR_B_CS#1DDR_B_CKE1

DDR_B_CLK1DDR_B_CLK#1DDR_B_BA1

DDR_B_ODT0DDR_B_CS#0

DDR_B_ODT1SOC_SMBCLK_1SOC_SMBDATA_1

DDR_B_SA0DDR_B_SA2

+1.2V_VDDQ

+2.5V+0.6VS_VTT+1.2V_VDDQ

+0.6VS_VTT

+1.2V_VDDQ+1.2V_VDDQ

1ADDR4_DIMMB

Custom

C5V01 M/B LA-E891P

Title

1ADDR4_DIMMB

Custom

C5V01 M/B LA-E891P

Title

1ADDR4_DIMMB

DQS2#(C) 53DQS2(T) 55

DQS3#(C) 74DQS3(T) 76

DQS4#(C) 177DQS4(T) 179

DQS5#(C) 198DQS5(T) 200

DQS6#(C)DQS6(T) 219

221

DQS7#(C) 240DQS7(T) 242

12

CD660.022U_0402_16V7K

1

2

Trang 21

Place closed to JEDP1

LED PANEL Conn.

EDP_AUXP_CEDP_AUXN_C

EDP_AUXN_CEDP_AUXP_C

EDP_HPD

EDP_TXN2_CEDP_TXN3_CEDP_TXP2_C

EDP_HPDBKOFF#

SOC_BKL_PW M

EDP_AUXP_CEDP_AUXN_C

EDP_TXN3_CEDP_TXN2_CEDP_TXP3_CEDP_TXN1_CEDP_TXP0_C

USB20_P7_CAMERA

DMIC_DATA_RDMIC_CLK_R

USB20_P6USB20_N6

TS_EN

DMIC_CLK_RDMIC_DATA_R

+3VS

+LCDVDD+3VS

+3VS

+INVPW R_B+

+LCDVDD

+3VS+TS_PW R

Title

@

JEDP1

ACES_50398-04041-001CONN@

@1

0.1U_0201_10V6K1

2

CX161 2 1U_0402_16V7KCX8 1 2 1U_0402_16V7K

@EMI@

RX3100K_0402_5% 1 @ 2

RX2 1 @ 2 10K_0402_5%

CX181 2 1U_0402_16V7KCX9 1 2 1U_0402_16V7K

CX7.1U_0402_16V7K

@1

2CX3

12

CX111 2 1U_0402_16V7K

CX191 2 1U_0402_16V7K

LX1HCB2012KF-221T30_08053S@

@

RX4100K_0402_5% 1 @ 2CX151 2 1U_0402_16V7K

Trang 22

HDMI_SCLKHDMI_SDATA

HDMI_C_TX0-

SOC_DP1_CTRL_CLKHDMI_SDATA

HDMI_C_CLK+

HDMI_C_CLK-HDMI_C_TX2+

HDMI_C_TX2-HDMI_C_TX0+

HDMI_C_TX0-HDMI_C_TX1+

HDMI_C_TX1-HDMI_R_D0+

HDMI_R_D0-HDMI_R_CK+

HDMI_R_CK-HDMI_R_D0+

HDMI_R_D0-HDMI_R_CK+

HDMI_R_CK-HDMI_R_D1+

HDMI_R_D1-HDMI_R_D2+

RPY2470_8P4R_5%

S

QY1A2N7002KDW _SOT363-62

RY61M_0402_5%

RPY1470_8P4R_5%

61

34

4

3

21

9 10DY2

TVW DF1004AD0ESD@

SC300002800

451

4

3

21

9 10DY3

TVW DF1004AD0ESD@

SC300002800

451

Trang 23

1 1

Using for Switch mode

Place near Pin 27

W=60mil W=60mil

The trace length from C to PIN34,35(VDDREG) must < 200mils.

reserve EC_PME# pull high 100K to +3VALW_EC

The trace length from and from C to Lx must

< 200mils.

+3V_LAN Rising time must >0.5ms and <100ms

Place near Pin 20 Place near Pin 3,8,33,46

Using for Switch mode

Current limit threshold 1.5~2.8A

Place near Pin 11,32,48

1.4A

300mA

close to pin17

800mA 1400mA

LAN-RTL8411B

PU at PCH side

DVT modify 12/04for WOL pull high to +3V_LAN

for disable PHYreserve 0 ohm

11/27: P/N change to SH00000RT00 ( S COIL 2.2UH +-20%

HPC252012NF-2R2M 1.3A)

Protect cotact

Open Card Uninsert

Card insert

Write protect (Lock)

Close

Write Enable (Unlock)

Card contact

Open Close

Place close to TCT pin

40mil 40mil

Card Reader Connector LAN Connector

LDO mode

LDO mode SWR mode

Close to JREAD1 for EMI

Close to Card Reader CONN

LAN_MIDI0-LAN_MIDI2+

LAN_MIDI1-LAN_MIDI3+

LAN_MIDI2-

LAN_MIDI3-XTLIXTLO

+REGOUTENSWREG

SD_D0_RSD_D0

SD_D1_RSD_D1

SD_CD#

+VDD33_18

GPO

XTLO_RGPO

SD_CLK_RSD_CMD_R

SD_WP#

SD_CD#

RJ45_MIDI0+

RJ45_MIDI0-RJ45_MIDI2+

RJ45_MIDI2-RJ45_MIDI3+

@EMI@

12

JPL1

@JUMP_43X118

CL2710P_0402_50V8J

2

RL162.49K_0402_1%

12

JSD1

TAITW_PSDATQ09GLBS1NN4H1CONN@

SP011611110

DAT1

109 DAT0VSS2

T262

@RL1 2LDO@ 1 0_0603_5%

RL1815K_0402_5%

@1

2CL19

10P_0402_50V8J1

JRJ45

SINGA_2RJ1660-000111FCONN@

SWR@

YL125MHZ_10PF_XRCGB25M000F2P34R0

@

T261

@

CL2510P_0402_50V8J12

SQL1L2N7002LT1G_SOT23-32

Tiêu đề	C5v01 M/B La-E891p
Trường học	Compal Electronics, Inc.
Thể loại	sơ đồ
Năm xuất bản	2017
Thành phố	taipei

Định dạng
Số trang	46
Dung lượng	1,43 MB