Apple macbook pro retina 15, a1398

BRANCH THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCEIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT Revision History 0

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TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

QTY

2 ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC

3 ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK APPD

1 2

4 5

6 7

8 B

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

D2_SEANVoltage & Load Side Current Sensing

45

D2_KEPLERSMBus Connections

44

D2_KEPLERLPC+SPI Debug Connector

43

D2_KEPLERSMC Support

42

D2_KEPLERSMC

41

D2_KEPLERUSB 3.0 CONNECTORS

40

D2_KEPLERSSD CONNECTOR

39

D2_KEPLERRIO CONNECTOR

38

D2_KEPLERThunderbolt Power Support

37

D2_KEPLERThunderbolt Host (2 of 2)

36

D2_KEPLERThunderbolt Host (1 of 2)

35

D2_KEPLERX29/ALS/CAMERA CONNECTOR

34

D2_KEPLERDDR3/FRAMEBUF VREF MARGINING

33

D2_KEPLERDDR3 Termination

32

D2_KEPLERDDR3 SDRAM Bank B (2 OF 2)

31

D2_KEPLERDDR3 SDRAM Bank B (1 OF 2)

30

D2_KEPLERDDR3 SDRAM Bank A (2 OF 2)

29

D2_KEPLERDDR3 SDRAM Bank A (1 OF 2)

28

D2_KEPLERCPU Memory S3 Support

27

D2_KEPLERUSB HUB & MUX

26

D2_KEPLERChipset Support

25

D2_KEPLERCPU & PCH XDP

24

D2_CLEANPCH DECOUPLING

23

D2_KEPLERPCH GROUNDS

22

D2_CLEANPCH POWER

21

D2_KEPLERPCH GPIO/MISC/NCTF

20

D2_KEPLERPCH PCI/USB/TP/RSVD

19

D2_KEPLERPCH DMI/FDI/PM/Graphics

18

D2_KEPLERPCH SATA/PCIe/CLK/LPC/SPI

17

D2_SEANCPU DECOUPLING-II

16

D2_SEANCPU DECOUPLING-I

15

D2_KEPLERCPU POWER AND GND

14

D2_KEPLERCPU POWER

13

D2_KEPLERCPU DDR3 INTERFACES

12

D2_KEPLERCPU CLOCK/MISC/JTAG

11

D2_KEPLERCPU DMI/PEG/FDI/RSVD

10

D2_KEPLERSignal Aliases

9

D2_KEPLERPower Aliases

8

D2_KEPLERFunctional / ICT Test

7

D2_KEPLERBOM Variants

6

D2_KEPLERBOM Configuration

5

D2_KEPLERRevision History

4

D2_KEPLERPower Block Diagram

3

D2_KEPLERSystem Block Diagram

2

01/13/2012 101

90

01/13/2012 100

89

01/13/2012 99

88

01/13/2012 98

87

01/13/2012 97

86

01/13/2012 96

85

01/13/2012 94

84

03/05/2012 92

83

03/05/2012 91

82

01/13/2012 90

81

03/05/2012 89

80

03/05/2012 88

79

03/05/2012 87

78

03/05/2012 86

77

03/05/2012 85

76

03/05/2012 84

75

03/05/2012 83

74

03/05/2012 82

73

03/05/2012 81

72

01/13/2012 80

71

01/13/2012 79

70

01/13/2012 78

69

01/13/2012 77

68

01/13/2012 76

67

03/05/2012 75

66

03/05/2012 74

65

01/13/2012 73

64

01/13/2012 72

63

01/13/2012 71

62

01/13/2012 70

61

01/13/2012 69

60

03/16/2012 68

59

03/16/2012 67

58

03/16/2012 66

57

03/16/2012 65

56

03/16/2012 64

55

03/16/2012 63

54

03/16/2012 62

53

01/13/2012 61

52

01/13/2012 59

51

01/13/2012 58

50

01/13/2012 57

49

01/13/2012 56

48

03/05/2012 55

03/05/2012 54

46

Sync Page

DateContents

Page

D2_KEPLERTable of Contents

1

SCHEM,MLB,KEPLER,2PHASE,D2 苹果笔记本维修交流群群号：３２５７４２６３４

苹果笔记本维修交流群群号：３２５７４２６３４

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BRANCH

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCEIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

PG 16

DDR3-1067/1333MHZ

2 DIMMS

RTCDMI

PG 17

PG 44

PG 51

PG 44 POWER SENSE

FAN CONN AND CONTROLJ5650,5660

Fan

CONNECTION SMBUS

PG 33

HUB 1USB

PG 34 U3700

LPC + SPI CONN Port80,serial

PG 57

J6700,J6750

LINE TINFILTER

CONNSATAJ4501ODD

PG 41

SATACONN

J4500HDD

PG 83

DP MUXXP25-5G

PG 83DDC MUX

PG 86GMUX

System Block Diagram

051-9589 4.18.0

2 OF 132

2 OF 99 苹果笔记本维修交流群群号：３２５７４２６３４

苹果笔记本维修交流群群号：３２５７４２６３４

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC

1 2

4 5

7 8

REVISION

BRANCH

D2 POWER SYSTEM ARCHITECTURE

CPUVTTS0_PGOOD

VOUT

REF3333(PAGE 45)

SMC PWRGDNCP303LSN

VIN

ENPP5V_S0_CPUVTTS0

(PAGE 45)U5000

U6990

VOUT

PGOODU8900

VIN

ISL6263CGPU VCORE

Q5315V

VDD

VR_ON SMC_PBUS_VSENSE

GPUVCORE_EN

PP5V_S3_GFXIMVP6_VDDPPBUS_G3H

MAX88404.5V

PP1V5_S3

ENPP3V3_S0

PP3V3_S0_PWRCTL

ISL88042IRTJJZ

S0PGOOD_PWROK

VCCPP3V3_S0PP1V8_GPUIFPX

PP1V05_S0

SMC_CPU_ISENSEA

PP1V2_S0

P1V2S0_EN

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_ENPP1V8_S0

TPS51116

Q7801

P1V5S0FET_GATE

U7300(PAGE 66)

SMC_CPU_HI_ISENSE

S5S3

PP3V3_S5

PP1V5_S3

GU7801

VIN

PP3V3_S5PP5V_S3

DDRREG_EN

DDRVTT_EN

SLG5AP020ON

VOUT2 VOUT1

VREG5

P1V5CPU_EN

(L/H)

(R/H)3.3V5VVIN

GU7880SLG5AP020

VIN

Q7922ON

PP1V8_S0

P1V8S0_PGOOD

P1V2ENET_PGOODPP1V2_ENET

PGOOD VOUT

(PAGE 70)

U7720

ISL8014AVIN

VINISL8014AVOUT PGOOD(PAGE 70)

U7760EN PP3V3_S0GPU

P1V2ENET_EN

P3V3S3_EN

EN

P3V3S0_EN PP3V3_S0_FET

PP3V3_S3Q7810Q7870

Q7830U7201

P1V8_S0_EN

D6990

PPBUS_G3H

PGOOD(PAGE 65)PP1V0_S0GPU_REG

PPVOUT_S0_LCDBKLTP5V3V3_PGOOD

P1V0GPU_PGOODP1V5FB_PGOOD

SMC_BATT_ISENSEVOUT

R6990

ISL6259HRTZU7000

SMC_RESET_L

SMC_DCIN_ISENSE

F69056A FUSE

POK1 VOUT2

EN1

EN2

POK2 1.003V(L/H)

P3V3S5_EN

(PAGE 85) 1.503V(R/H)

P5VS3_EN

VIN EN1

ISL6236 EN2

Q9806

U9500

P1V0GPU_ENPPVBAT_G3H_CHGR_R

P1V5FB_EN

Q7055

GPUVCORE_ENP3V3GPU_ENP1V1GPU_EN

P3V3S5_EN

VOUT

VINLP8550

PFWBOOST

U9701

(PAGE 87)ENA

BKLT_EN

Q4260

LCD_BKLT_NOBKLT_PLT_RST_L

P5VS3_EN

DDRREG_EN

P3V3S3_ENPM_ALL_GPU_PGOOD

PM_SLP_S4_LPM_SLP_S5_L

PM_SLP_S3_L

PPVBATT_G3H_CONN

EG_RAIL1_EN

EG_RAIL3_ENEG_RAIL2_EN

J6950

PB16B

PB17B PB17AU9600

GMUX

XP25-5

DELAYRC

P1V5CPU_ENCPUVTTS0_EN

RC

DELAY RC DELAY

RC

RC DELAY

PM_PWRBTN_L

PM_MEM_PWRGDCPU_PWRGDPLT_RERST_L

SMC_ADAPTER_EN

PM_PWRBTN_LPM_SYSRST_LCPUIMVP_VR_ONPM_RSMRST_L

SMC_RESET_LRSMRST_OUT(P15)

DRAMPWROK PROCPWRGD

AR7640

CPUVTTS0_PGOOD

VOUT

REF3333(PAGE 45)

H8S2117SLP_S5_L(P95)

U4900SLP_S3_L(P93) SLP_S4_L(P94)

U6200VIN

CHGR_BGATE

ADAPTER

AC

P5V3V3_PGOODP1V8S0_PGOODPP3V3_S0_PWRCTL

(PAGE 82)

DDRREG_PGOOD

P3V3GPU_EN

ACPRESENT RSMRST#

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BRANCH

Revision History

051-9589 4.18.0

4 OF 132

4 OF 99

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TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

BOM OPTIONS BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

QTY

TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PART NUMBERALTERNATE FOR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS BOM GROUP

TABLE_BOMGROUP_HEAD

4 5

7 8

REVISION

BRANCH

PD Parts

Alternate Parts BOM Variants (continued on CSA 6)

353S3526 353S3528

Diodes alt to Toshiba

376S0855376S0855 376S0613 VREFDQ:M1_M3 ALL Diodes alt to Toshiba

ALL376S0796

ALL Diodes alt to On Semi376S1076

197S0181197S0452

NDK Alt to TXCALL

197S0453 197S0181

D2,MLB,KEPLER,FSB DEVD2,MLB,KEPLER,DEV

D2,MLB,KEPLER_2PHASE,COMMON607-9546

338S1113

32

32 333S0623

685-0017

PBUS_CAP:KEMET

IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP

IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HTPCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4

PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44

PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D

PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C

PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3YPCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V

CRITICAL

CRITICAL CRITICAL U1000

DDS alt to STALL

333S0631

PBUS_CAP:SANYO

CRITICAL

PBUS_CAP:KEMET128S0257

CRITICAL CRITICAL

TBTRTR:PRQ

2G_SAMSUNG_1600

PBUS_CAP:SANYO

FB_2G_HYNIX_A_DIE 4G_ELPIDA_1600 4G_SAMSUNG_1600 4G_HYNIX_1600 2G_ELPIDA_1600

CRITICAL CRITICAL CRITICAL CRITICAL

XDP_CONN,XDP_PCH ALTERNATE,IVB_PPT_XDP SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG

VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO

ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB

PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HMPCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600

PBUS_CAP:SANYO BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600

D2_COMMON,POSCAP_MYLAR_PAIR

[EEEE:DY3V] CRITICAL825-7563 1 LABEL,MLB/LIO,MBA EEEE:DY3V

[EEEE:DY43] EEEE:DY431

825-7563 LABEL,MLB/LIO,MBA CRITICAL

825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY45] CRITICAL

1825-7563

825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY4C] CRITICAL

1 [EEEE:DRF1] CRITICAL825-7563 LABEL,MLB/LIO,MBA

[EEEE:DRF4] CRITICAL1

825-7563 LABEL,MLB/LIO,MBA

EEEE:DRDNCRITICAL

1825-7563 LABEL,MLB/LIO,MBA [EEEE:DRDN]

1 [EEEE:DRDW] CRITICAL825-7563 LABEL,MLB/LIO,MBA

825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9G] CRITICAL

IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2

VREFDQ:M1_M3,VREFCA:LDO VREFDQ:M1_M3,VREFCA:LDO_DAC VREF:ENG_M3

VREFDQ:M1_DAC,VREFCA:LDO_DAC VREF:ENG_LDO

685-0016 PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 POSCAP_MYLAR POSCAP_MYLAR_PAIR

085-4776 D2 MLB KEPLER FSB DEVEL BOM DEVEL_FSB DEVEL_FSB_BOM

1085-3726

EEEE:DY45EEEE:DY4CEEEE:DRF1

EEEE:DRDWEEEE:DT9H

EEEE:DT9FEEEE:DT9G

On Semi alt to Semtech377S0147

PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1

PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN

PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H

PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9GPCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HNPCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR

PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY

CAN_COVER1,CAN_COVER2

PCH_INSULATORGPU_INSULATOR

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LFCAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

REAR_INSULATORCPU_INSULATOR

3030

C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821 C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821

051-9589 4.18.0

5 OF 132

5 OF 99

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REVISION

BRANCH

TABLE_BOMGROUP_ITEM

BOM OPTIONS BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

QTY

Keeping for PRQ Elipda DQ’d

1 [EEEE:F0J4] CRITICAL EEEE:F0J4825-7563 LABEL,MLB/LIO,MBA

CRITICAL

1 [EEEE:F0JD] EEEE:F0JD825-7563 LABEL,MLB/LIO,MBA

1 [EEEE:F0J3] CRITICAL EEEE:F0J3825-7563 LABEL,MLB/LIO,MBA

CRITICAL

1 [EEEE:F0JC] EEEE:F0JC825-7563 LABEL,MLB/LIO,MBA

639-3631

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600

051-9589 4.18.0

6 OF 132

6 OF 99

Trang 7

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

II NOT TO REPRODUCE OR COPY ITPLACEABLE BEAD-PROBES FOR TBT

CPU NO_TESTsNO_TEST

NO_TEST

ICT Test Points

GPU NO_TESTsNO_TEST

NO_TESTThunderbolt NO_TESTs

3X P5V_S0

2X2X

FUNC_TEST

2X GND4X GND

4XFUNC_TEST

4X

3X16X GND

2X GND

8X

2X GND2X

POWER RAILS

8X GNDFUNC_TEST

J9000 - eDP J6701 - audio flex

I1657 I1658 I1659

I1660 I1661

I1662 I1663 I1664

I1665 I1666

I1667 I1668 I1669

I1670 I1671

I1672 I1673 I1674

I1675 I1676

I1677 I1678 I1679

I1688 I1689

I1690 I1691

I1692

I1693 I1694

I1695

I1696 I1697

I1698 I1699 I1700

I1701 I1702

I1703 I1704 I1705

I1706 I1707

I1708 I1709 I1710

I1711 I1712

I1713

I1714 I1715

I1716 I1717

I1718

I1719 I1720

I1721 I1722

I1734 I1735

I1736

I1737 I1738

I1739 I1740

I1741

I1742 I1743

I1744 I1745

I1746

I1747 I1748

I1749 I1750

I1751

I1752 I1753

I1754 I1755

I1756

I1757 I1758

I1759 I1760 I1761

I1762 I1763

I1764

I1765 I1766

I1767 I1768

I1769 I1770 I1771

I1772 I1773

I1774 I1775 I1776 I1777

I1778 I1779

I1780 I1781 I1782

I1785

I1793

I1795

I1797 I1798

I1799 I1800

I1802 I1803

I1817 I1818

TP_GPU_MIOA_DETP_GPU_MIOA_D<9 0>

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE TRUE NC_HDA_SDIN3

TRUE NC_PCIE_5_D2RP

MAKE_BASE=TRUE TRUE NC_PCIE_8_R2D_CN

TRUE MAKE_BASE=TRUE

NC_PCIE_8_D2RN

MAKE_BASE=TRUE TRUE NC_PCIE_5_D2RN

NC_LVDS_IG_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE TRUE

NC_CRT_IG_DDC_DATA

TRUE MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE NC_TP_CPU_RSVD<43 32>

TRUE MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27 26>

MAKE_BASE=TRUE TRUE NC_TP_CPU_RSVD_NCTF<8 5>

TRUE NC_PCIE_PE8_R2D_CP

MAKE_BASE=TRUE TRUE NC_PCIE_PE8_R2D_CN

MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE NC_PCIE_PE8_D2RN

TRUE NC_PCIE_PE8_D2RP

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCIE_PE7_D2RP

TRUE MAKE_BASE=TRUE

NC_PCIE_PE5_D2RP

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

MAKE_BASE=TRUE TRUE NC_PCIE_PE5_D2RN

NC_PCH_LVDS_VBG

TRUE

NC_LVDS_IG_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_LPC_DREQ0_L

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

MAKE_BASE=TRUE TRUE NC_PCI_AD<31 0>

TRUE MAKE_BASE=TRUE

NC_PCI_GNT3_L

MAKE_BASE=TRUE TRUE NC_PCI_GNT1_L

NC_PCI_CLK33M_OUT3

TRUE MAKE_BASE=TRUE

NC_PCH_NV_RCOMP

MAKE_BASE=TRUE TRUE

NC_NV_DQ<15 0>

MAKE_BASE=TRUE TRUE

NC_NV_DQS<1 0>

TRUE MAKE_BASE=TRUE

NC_NV_ALE

MAKE_BASE=TRUE TRUE

NC_NV_CLE

MAKE_BASE=TRUE TRUE

NC_NV_WR_RE_L<1 0>

MAKE_BASE=TRUE TRUE

NC_NV_WE_CK_L<1 0>

MAKE_BASE=TRUE TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE TRUE NC_PSOC_P1_3

TRUE MAKE_BASE=TRUE

NC_SATA_B_D2RN

MAKE_BASE=TRUE TRUE NC_SATA_B_D2RP

TRUE MAKE_BASE=TRUE

NC_SATA_B_R2D_CN

TRUE MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE TRUE NC_SATA_D_D2RN

NC_SATA_D_D2RP

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE NC_SATA_D_R2D_CN

TRUE MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

MAKE_BASE=TRUE TRUE NC_SATA_E_D2RN

MAKE_BASE=TRUE TRUE NC_SATA_E_D2RP

MAKE_BASE=TRUE TRUE NC_SATA_E_R2D_CN

MAKE_BASE=TRUE TRUE NC_SATA_E_R2D_CP

MAKE_BASE=TRUE TRUE NC_SATA_F_D2RN

MAKE_BASE=TRUE TRUE NC_SATA_F_R2D_CN

TRUE MAKE_BASE=TRUE

NC_SATA_F_D2RP

MAKE_BASE=TRUE TRUE NC_SATA_F_R2D_CP

TRUE

MAKE_BASE=TRUE TRUE NC_DVPDATA<21 4>

MAKE_BASE=TRUE TRUE NC_DVPCNTL_M<1 0>

MAKE_BASE=TRUE TRUE NC_PCIE_7_R2D_CP

TRUE NC_PCIE_6_R2D_CP

MAKE_BASE=TRUE

MAKE_BASE=TRUE TRUE NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE TRUE NC_PCIE_CLK100M_PE4N

TRUE NC_HDA_SDIN2

MAKE_BASE=TRUE

NC_PCI_GNT2_L

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE TRUE NC_PCI_PME_L

TRUE NC_NV_RB_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE TRUE NC_PCI_GNT0_L

TRUE TBT_B_D2R_P<1 0>

TRUE TBT_B_D2R_C_N<1 0>

TBT_B_D2R_C_P<1 0>

TRUE TRUE TBT_A_R2D_N<1 0>

TRUE TBT_B_R2D_P<1 0>

TRUE TBT_B_R2D_N<1 0>

TBT_B_R2D_C_P<1 0>

TRUE TRUE TBT_B_R2D_C_N<1 0>

NC_CRT_IG_DDC_CLKNC_CRT_IG_RED

MAKE_BASE=TRUE TRUE

NC_CRT_IG_GREEN

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_HPDNC_DP_IG_C_CTRL_DATA

TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

TRUE

NC_DP_IG_C_MLP<3 0>

MAKE_BASE=TRUE TRUE

NC_DP_IG_C_MLN<3 0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3 0>

TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE NC_DP_IG_D_MLN<3 0>

NC_SDVO_INTP

TRUE MAKE_BASE=TRUE

NC_GPU_BUFRST_L

MAKE_BASE=TRUE TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE NC_GPU_MIOA_D<9 0>

NC_GPU_MIOA_DE

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWM

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE NC_PCIE_8_R2D_CP

MAKE_BASE=TRUE TRUE NC_PCIE_6_D2RP

MAKE_BASE=TRUE TRUE NC_PCIE_6_R2D_CN

MAKE_BASE=TRUE TRUE NC_PCIE_7_D2RN

MAKE_BASE=TRUE TRUE NC_PCIE_7_D2RP

TRUE TRUE WS_KBD8

TRUE WS_LEFT_OPTION_KBD

TRUE WS_LEFT_SHIFT_KBD

AUD_HP_PORT_R

TRUE TRUE AUD_HP_PORT_L

TRUE AUD_SPDIF_OUT_JACK

TRUE AUD_TYPEDETAUD_TIPDET_INV

TRUE PP3V3_S5TRUE PP3V3_S3

NC_TP_CPU_RSVD<65 62>

TRUE WS_KBD6

TRUE TP_SMC_MD1TP_SMC_TRST_L

TRUE PM_CLKRUN_L

TRUE Z2_DEBUG3Z2_CS_L

TP_PCIE_5_R2D_CPTP_PCIE_5_D2RP

TP_PCI_GNT1_LTP_PCI_GNT0_L

TP_NV_DQ<15 0>

TP_PCH_NV_RCOMPTP_PCI_PME_L

LVDS_IG_BKL_PWMSMC_BS_ALRT_LLVDS_IG_B_CLK_P

TP_GPU_GSTATE<0>

TP_GPU_GSTATE<1>

TP_GPU_BUFRST_LTP_SDVO_INTP

TP_SDVO_STALLPTP_SDVO_INTN

TP_SDVO_TVCLKINPTP_SDVO_STALLN

TP_DP_IG_D_AUXNTP_SDVO_TVCLKINNTP_DP_IG_D_AUXPTP_DP_IG_D_MLN<3 0>

TP_DP_IG_D_MLP<3 0>

TP_DP_IG_D_CTRL_DATATP_DP_IG_D_CTRL_CLKTP_DP_IG_D_HPDTP_DP_IG_C_AUXNTP_DP_IG_C_AUXPTP_DP_IG_C_MLN<3 0>

TP_DP_IG_C_MLP<3 0>

TP_DP_IG_C_CTRL_CLKTP_DP_IG_C_CTRL_DATATP_PCI_AD<31 0>

TP_PCIE_CLK100M_PE5P

TP_PSOC_P1_3

TP_PCIE_CLK100M_PE6PTP_PCIE_CLK100M_PE7P

TP_SATA_B_R2D_CN

TP_PCI_GNT2_L

TP_NV_CE_L<3 0>

TP_PCI_PARTP_PCI_RESET_LTP_PCI_CLK33M_OUT3TP_HDA_SDIN2

TP_SATA_B_D2RN

TP_PCIE_6_D2RNTP_PCIE_6_D2RP

TP_TBT_XTAL25OUTTP_TBT_PCIE_RESET0_LTP_TBT_PCIE_RESET1_LTP_TBT_PCIE_RESET3_LTP_DP_TBTSRC_ML_CN<3 0>

TP_DP_TBTSRC_AUXCH_CNTP_DP_TBTSRC_ML_CP<3 0>

TP_PCI_GNT3_L

TP_CRT_IG_BLUE

TP_CRT_IG_VSYNCTP_LVDS_IG_CTRL_CLKTP_CRT_IG_HSYNC

TP_LVDS_IG_CTRL_DATA

TP_HDA_SDIN1TP_HDA_SDIN3

TP_PCIE_CLK100M_PEBP

TP_PCIE_PE5_D2RN

TP_PCIE_PE5_R2D_CPTP_PCIE_PE6_D2RN

TP_PCIE_PE5_D2RPTP_PCIE_PE5_R2D_CN

TP_PCIE_PE6_R2D_CPTP_PCIE_PE6_R2D_CN

TP_PCIE_PE7_D2RNTP_PCIE_PE7_D2RPTP_PCIE_PE6_D2RP

TP_PCIE_PE7_R2D_CN

TP_PCIE_PE8_D2RPTP_PCIE_PE8_D2RNTP_PCIE_PE8_R2D_CNTP_PCIE_PE8_R2D_CP

TP_PCIE_7_D2RNTP_PCIE_7_D2RPTP_PCIE_6_R2D_CPTP_PCIE_6_R2D_CN

TP_PCIE_5_R2D_CNTP_PCIE_5_D2RN

TP_PCH_LVDS_VBGTP_CPU_RSVD_NCTF<8 5>

TP_NV_WR_RE_L<1 0>

TP_NV_CLETP_NV_ALE

BP07341

051-9589 4.18.0

Trang 8

BRANCH

PP5V_S3

VOLTAGE=5V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H_ISOL

VOLTAGE=18.5V MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V

PPDCIN_G3H

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm

PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=12.8V MIN_NECK_WIDTH=0.25 mm

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_NECK_WIDTH=0.1 MM

VOLTAGE=12.8V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_GPU_ISNSMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE VOLTAGE=12.8V MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPVIN_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE VOLTAGE=12.8V MIN_LINE_WIDTH=0.6 mm

PPVCORE_GPU

MAKE_BASE=TRUE VOLTAGE=1.0V

MIN_NECK_WIDTH=0.17 mm

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP15V_TBT

VOLTAGE=15V MIN_LINE_WIDTH=0.4 MM

PPVCORE_S0_AXG

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM

PPVRTC_G3H

VOLTAGE=3.42V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE VOLTAGE=1.5V

PP1V5_S3_CPU_VCCDQ

VOLTAGE=1.5V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

VOLTAGE=1.05V MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPVCCSA_S0_REG

MIN_LINE_WIDTH=0.6 MM VOLTAGE=0.9V MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0_CPUDDR

PPVCORE_S0_CPU

VOLTAGE=1.25V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.075 mm MIN_LINE_WIDTH=0.5 MM

PP3V3_S0

VOLTAGE=3.3V MAKE_BASE=TRUE

PP1V05_S0_P1V05TBTFET

VOLTAGE=12.8V

PPVIN_SW_TBTBST

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_TBTLC

VOLTAGE=3.3V

PP3V3_TBTLC

MAKE_BASE=TRUE MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.4 MM

PP1V05_TBTCIO

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM

PP3V3_S5

MAKE_BASE=TRUE

PP3V3_S0GPU_MISC

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_NECK_WIDTH=0.10MM

PP1V05_S0

PP1V05_PCHVCCIO_S0MIN_LINE_WIDTH=0.6 MMVOLTAGE=1.05VMAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_GPU_PGOOD2

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=2 mm

PP0V75_S0_DDRVTT

MAKE_BASE=TRUE VOLTAGE=0.75V MIN_NECK_WIDTH=0.2 MM

PPVTTDDR_S3

MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.6 MM

PP5V_S0

MAKE_BASE=TRUE VOLTAGE=5V

VOLTAGE=5V MAKE_BASE=TRUE

NC_SMC_T25_EN_L

MAKE_BASE=TRUE

PP3V3_SUS

MAKE_BASE=TRUE

051-9589 4.18.0

Trang 9

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

T29 / GMUX JTAG Signals

GMUX ALIASES

Unused PEG signals

T29 Signals Through PEGCPU signals

1/8W MF-LF0

TBTBST:N

STDOFF-4.5OD1.8H-SMSTDOFF-4.5OD2.15H-SM

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD2.15H-SMSTDOFF-4.5OD2.15H-SM

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.9H-SM

2.8R2.3

1K5%

201MF1/20W

RAMCFG0:L

1/20W

RAMCFG1:L

2011KMF5%

RAMCFG3:L

1/20WMF5%

2011K

201MF1/20W

RAMCFG2:L

1K5%

I1191I1192

SL-1.1X0.45-1.4x0.75TH-NSP

TH-NSP

SL-1.1X0.45-1.4x0.75SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75TH-NSP

MAKE_BASE=TRUE

GND

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P<2 0>

NC_LVDS_IG_A_DATAN<3>

TP_PCH_GPIO65_CLKOUTFLEX1

GND_CHASSIS_MLBCAN6GND_CHASSIS_MLBCAN5

GND_CHASSIS_MLBCAN4

GND_CHASSIS_FAN

GND_CHASSIS_MLBCAN3GND_CHASSIS_MLBCAN2GND_CHASSIS_MLBCAN1

NC_PCIE_CLK100M_EXCARD_P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_N

TRUE MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_P

TRUE MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_N

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE DPLL_REF_CLKN

TRUE MAKE_BASE=TRUE

PP5V_S0_AUDIO_AMP_R

MAKE_BASE=TRUE

NC_CPU_FDI_LSYNC<1 0>

NC_LVDS_IG_A_DATA_N<2 0>

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

NC_PCIE_FW_R2D_CN

NC_PCIE_FW_D2RP

NC_PCIE_FW_D2RN

TBT_LSEO_LSOE2

TBT_LSEO_LSOE3

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15 14>

USB3_EXTD_TX_N

USB_EXTC_PUSB_EXTC_N

USB_EXTD_EHCI_PUSB_EXTD_EHCI_N

TBT_LSEO<3>

TBT_LSEO<2>

GPU_RESET_L

IG_LCD_PWR_ENIG_BKLT_EN

EG_CLKREQ_OUT_LEG_CLKREQ_IN_L

=PPVIN_SW_TBTBST

=PEG_R2D_C_P<13 12>

=PEG_R2D_C_N<13 12>

PCIE_CLK100M_FW_NPCIE_CLK100M_FW_P

USBHUB_DN4_NUSBHUB_DN4_PUSBHUB_DN3_N

ENET_LOW_PWRENET_LOW_PWR_PCH

FW_PWR_EN

DPA_IG_HPDDPB_IG_HPD

=PP5V_S0_AUDIO_XWMLB_RAMCFG3

MLB_RAMCFG2MLB_RAMCFG1

PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_NPCIE_EXCARD_R2D_C_P

TP_PCH_GPIO67_CLKOUTFLEX3 TP_PCH_GPIO66_CLKOUTFLEX2

TBT_LSOE<3>

PCIE_EXCARD_D2R_NPCIE_EXCARD_D2R_PPCIE_EXCARD_R2D_C_N

TP_PCH_GPIO64_CLKOUTFLEX0 TP_PCH_CLKOUT_DPP

R0950

SH09251SH0926

1SH0927

1

SH09281SH0929

1

SH09301

SH09241

SH09231

SH0931

1

ZT09701

ZT09721

Trang 10

INININ

OUTOUT

OUT

IN

INININININININININININININININ

IN

ININININ

ININININININ

INININININ

OUT

OUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUTOUTOUTOUT

OUTOUTOUTOUTOUT

OUTOUTOUTOUTOUTOUT

OUT

OUTOUTOUTOUT

OUT

OUTOUT

OUT

OUTOUTOUTOUT

OUT

OUTOUT

OUT

ININ

IN

ININ

NCNCNCNCNC

NC

NCNC

NC

NCNC

NC

NCNCNCNCNC

NCNCNCNC

NC

NCNCNCNC

NC

NCNC

NC

OUTOUT

BIBI

IN

(1 OF 11)

FDI0_FSYNCFDI1_FSYNC

FDI0_LSYNCEDP_TX0*

EDP_TX2*

PEG_TX8EDP_TX3*

FDI1_TX3

FDI_INTFDI1_LSYNC

EDP_TX1*

EDP_TX0EDP_TX1EDP_TX2EDP_TX3

FDI0_TX2

FDI1_TX0FDI1_TX2

PEG_TX10PEG_TX9PEG_TX7PEG_TX6

PEG_TX14*

PEG_TX15*

PEG_TX13PEG_TX12EDP_AUX*

DMI_RX1DMI_RX2

DMI_TX3FDI0_TX0*

FDI0_TX1*

FDI1_TX1*

FDI0_TX0FDI0_TX1FDI0_TX3

FDI1_TX1

EDP_AUX

EDP_ICOMPOEDP_COMPIOEDP_HPD*

PEG_ICOMPIPEG_ICOMPOPEG_RCOMPOPEG_RX0*

PEG_TX11

PEG_TX14PEG_TX15

DMI_RX0DMI_RX3*

NCNC

NCNCNC

NCNC

NCNCNC

NCNCNCNC

NCNC

NCNCNC

NCNC

NCNCNC

NCNCNCNCNCNC

NC

NCNCNCNC

NC

NCNCNCNC

NC

SD

REVISION

BRANCH

QTY

Intel is investigating processor driven VREF_DQ generation

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

(THERMDC) (THERMDA)

These can be Placed close to J2500 and Only for debug access

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(IPU)

(IPU) (IPU) (IPU)

(IPU)

(IPU) (IPU) (IPU)

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSEDCFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOSCPU_CFG<4> should be pulled down to enable EDP

This connection is to support the same.

1/16W 5%

402

1K

NOSTUFF

1/16W 5%

402 MF-LF

1K

402

1K

MF-LF 5%

NOSTUFF

402 5%

MF-LF

1K

1/16W 5%

402

NOSTUFF

1K

1/16W 5%

402

1K

NOSTUFF

1/16W 5%

402

1K

NOSTUFF

1/16W 402

1K

NOSTUFF

MF-LF 5%

1K

5%

1/16WOMIT_TABLE

82

OMIT_TABLEIVY-BRIDGEBGA

OMIT_TABLE

IVY-BRIDGEBGA

2N7002TXGEDP:YES SOT-523-3

BEAD-PROBE SM

116S0090 1 RES,MTL FILM,1/16W,10K,0402,SMD,LF R1031 EDP:NO

R1031 EDP:YES

1 RES,MTL FILM,1/16W,1K,0402,SMD,LF116S0066

PPCPU_MEM_VREFDQ_A

PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mmVOLTAGE=0.75V

T9 R10

R6 R8

U8 U10

N2 N4

R2 R4

P3 P1

T5 U6

AE4 AE2

AC2

AE8 AB1

AG4 AG2

AF3 AF1

AF7 AE6

AG8 AG6

AC8

AB7

W6 V7

W10 W8

Y9 AA8

AA10 AC10

AA2

AB3 U2 U4

W4 W2

V3 V1

AA6 Y5

AD9

G2 H1 F3

G22 F23

K23 H23

F11 H11

K11 J12

F9 E8

H9 G10

H7 J8

G6

F7

K21 H21

F19 H19

K19 J20

H17 G18

K15 K17

G14 F15

J16 H15

K13 H13

C22 A22

D23 B23

B13 D13

C10 A10

D11 B11

B9 D9

D7 B7

F13

E12

A18 C18

B21 D21

D19 B19

F21 E20

C14 A14

B17 D17

D15 B15

F17 E16

U1000

B57 D57

F55 K55 F57 E58 H57 H55 D53 K57

B55 A54 A58 D55 C56 E54 J54 G56

G64 BJ42

BG62 BG34 BG26 BG22 BG4 BF63 BF43 BF41 BF35 BF25 BJ34

BF23 BF21 BF19 BF3 BE32 BE16 BE6 BD33 BD29 BD19 BJ22

BD15 BD13 BC42 BC30 BC14

BB57 BB43 BB25 BB17 BB15

BH43

BB13 BA48 BA16 AY45 AY41 AY17 AY15 AY13 AW50 AW46

BH35

AW42 AW14 AJ10 AJ6 AH5 AD5 AC6 AC4 AA4 P7

M9 M5 L10 L6 L4 L2 K49 K47 K9 BH23

K7 K5 J50 J4 J2 H49 H47 H5 G52 G48 BH21

G4 F5 D49 D25 D3 C52 C24 C4 B53 B25 BH19

Q10313

1

2

BP10041

BP10111

BP10121

051-9589 4.18.0

Trang 11

IN

OUT

ININOUT

OUTBI

NC

OUTBI

THERMTRIP*

RESET*

PM_SYNCUNCOREPWRGOODSM_DRAMPWROKSM_DRAMRST*

SM_VREFSM_RCOMP0SM_RCOMP1SM_RCOMP2

DPLL_REF_CLKDPLL_REF_CLK*

BCLK_ITPBCLK_ITP*

BCLKBCLK*

PRDY*

PREQ*

TCKTMSTRST*

TDITDODBR*

INOUT

ININ

INOUTIN

ININ

OUT

BIBIBI

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

R1120 and R1121 are Intel recommended values

(IPU) (IPU) (IPU) (IPU)

PLACE_NEAR=U1000.BG46:12.7mm

25.5

1%

1/16W 402

PLACE_NEAR=U1000.BJ46:12.7mm

1%

140

MF-LF 402

0.1UF

10%

MF-LF 5%

9 89

MF-LF1%

1K402PLACE_NEAR=U1000.BJ44:2.54mm

MF-LF1%

1K402

NOSTUFF

1K

5%

1/20W MF 201

MF-LF PLACE_NEAR=R1121.2:1mm

402

1301%

MF-LF PLACE_NEAR=U1000.AY25:51.562mm

402

43.2

1/16W 1%

MF-LF 402

=PP1V05_S0_CPU_VCCIO

DPLL_REF_CLKN

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

CPU_SM_RCOMP<0>

PM_THRMTRIP_L CPU_PROCHOT_R_L CPU_PECI CPU_PROC_SEL_L

R11041

2

R11251 2

R1102

1

2

R11111

2

R11261

2

R11141

2

R11131

2

R11121

2

R11031 2

U1000

D5 C6

K63 K65

C62 D61 E62 F63 D59 F61 F59 G60

H53

H61

AJ4 AJ2

F53

K53

J62 H65

J58

K61 K59

F51

H59 H63

Trang 12

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

BIBIBIBIBIBI

BIBI

OUT

OUTOUT

OUT

BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBI

OUTOUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

BIBIBIBIBIBIBIBI

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

BIBIBIBIBIBIBIBI

OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT

SA_CLK0

SA_CLK1*

SA_DQ30

SA_DQ0SA_DQ1SA_DQ2

SA_DQ9SA_DQ11SA_DQ12SA_DQ13SA_DQ14SA_DQ15SA_DQ16SA_DQ17SA_DQ18SA_DQ19SA_DQ20SA_DQ21SA_DQ22SA_DQ23SA_DQ24SA_DQ25SA_DQ26SA_DQ27SA_DQ28SA_DQ29SA_DQ31SA_DQ32SA_DQ33SA_DQ34SA_DQ35SA_DQ36SA_DQ37SA_DQ38SA_DQ39SA_DQ40SA_DQ41SA_DQ42SA_DQ43SA_DQ44

SA_DQ48SA_DQ49SA_DQ50SA_DQ51SA_DQ52SA_DQ53SA_DQ54SA_DQ55SA_DQ56SA_DQ57SA_DQ58SA_DQ59SA_DQ60SA_DQ61SA_DQ62SA_DQ63SA_BS0SA_BS1SA_BS2

SA_DQ4SA_DQ3

SA_DQ10SA_DQ8SA_DQ7

SA_DQ5SA_DQ6

SA_CAS*

SA_DQ47SA_DQ46SA_DQ45

SA_CKE1

SA_CLK0*

SA_CKE0SA_CLK1(3 OF 11)

SB_MA15SB_MA14

SB_BS0

SB_DQ51SB_DQ52SB_DQ53SB_DQ54SB_DQ55SB_DQ56SB_DQ57

SB_DQ18SB_DQ19SB_DQ20SB_DQ21SB_DQ22SB_DQ23SB_DQ24SB_DQ14

SB_DQ2

SB_DQ5SB_DQ7SB_DQ8SB_DQ6

SB_DQ10SB_DQ9

SB_DQS0

SB_DQS4SB_DQS5SB_DQS6SB_DQS7

SB_MA1SB_MA2

SB_DQ0

SB_DQ12SB_DQ11SB_DQ13SB_DQ15SB_DQ16SB_DQ17

SB_MA13SB_MA12SB_MA11SB_MA10SB_MA9SB_MA8SB_MA7SB_MA6SB_MA5SB_MA4SB_MA3SB_MA0

SB_DQS3SB_DQS2SB_DQS1

SB_DQ50SB_DQ49SB_DQ48SB_DQ47SB_DQ46SB_DQ45SB_DQ44SB_DQ43SB_DQ42SB_DQ41SB_DQ40SB_DQ39SB_DQ38SB_DQ37SB_DQ36SB_DQ35SB_DQ34SB_DQ33SB_DQ32SB_DQ31SB_DQ30SB_DQ29SB_DQ28SB_DQ27SB_DQ26SB_DQ25

SB_DQ1

SB_DQ4

SB_CLK1(4 OF 11)

REVISION

BRANCH

OMIT_TABLE

BGAIVY-BRIDGE

BE44

BC18

BD17

BB31 BA32

AW34 AY33

BD41 BD45

AL6 AL8

AV7 AY5 AT5 AR6 AW6 AT9 BA6 BA8 BG6 AY9 AP7

AW8 BB7 BC8 BE4 AW12 AV11 BB11 BA12 BE8 BA10 AM5

BD11 BE12 BB49 AY49 BE52 BD51 BD49 BE48 BA52 AY51 AK7

BC54 AY53 AW54 AY55 BD53 BB53 BE56 BA56 BD57 BF61 AL10

BA60 BB61 BE60 BD63 BB59 BC58 AW58 AY59 AL60 AP61 AN10

AW60 AY57 AN60 AR60

AM9 AR10 AR8

AN6 AN8

AU8 AU6

BD5 BC6

BC10 BD9

BB51 BC50

BD55 BB55

BD61 BD59

AV61 AU60

BD27 BA28

AW38 AW22 BA20 BB45 BE20 AW18

BB27 AW26 BB23 BA24 AY21 BD21 BC22 BB21

BB41 BC46

BE36 BA44

U1000

BJ38 BD37 AY29

BH39

BD25

BJ26

BF33 BH33

BF37 BH37

BE40 BH41

AL4 AK3

BA4 BB1 AV1 AU2 BA2 BB3 BC2 BF7 BF11 BJ10 AP3

BC4 BH7 BH11 BG10 BJ14 BG14 BF17 BJ18 BF13 BH13 AR2

BH17 BG18 BH49 BF47 BH53 BG50 BF49 BH47 BF53 BJ50 AL2

BF55 BH55 BJ58 BH59 BJ54 BG54 BG58 BF59 BA64 BC62 AK1

AU62 AW64 BA62 BC64 AU64 AW62 AR64 AT65 AL64 AM65 AP1

AR62 AT63 AL62 AM63

AR4 AV3 AU4

AN2 AN4

AW4 AW2

BF9 BH9

BH15 BF15

BH51 BF51

BF57 BH57

AY65 AY63

AN64 AN62

BF31 BH31

AY37 BJ30 AW30 BA40 BB29 BE28

BB37 BC34 BF27 BB33 BH27 BG30 BH29 BF29

BG42 BH45

BG38 BF39

051-9589 4.18.0

12 OF 132

12 OF 99

Trang 13

OUTOUT

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

II NOT TO REPRODUCE OR COPY IT HR_PPDG sections 6.2.1 and 6.3.1.

For Future Compatibility

NOTE: Intel validation sense lines per doc 439028 rev1.0

MF-LF 5%

0

1/16W 402

65

1%

402 1/16W

MF-LF

PLACE_SIDE=BOTTOM

NOSTUFF

1/16W 402

1/20W

PLACE_SIDE=BOTTOM

MF 1%

201

NOSTUFF

201 1/20W MF

49.9 PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

NOSTUFF

MF 1%

49.9

201 1/20W

MF 201 1/20W 1%

49.9 NOSTUFF PLACE_SIDE=BOTTOM

100

MF-LF 402 5%

402 MF-LF 1%

1/16W

100

1/16W 1%

MF-LF 402

OMIT_TABLE

BGA

OMIT_TABLEIVY-BRIDGE

TP_CPU_VDDQSENSEN TP_CPU_VDDQSENSEP

=PPVCORE_S0_CPU

TP_DC_TEST_D65 TP_DC_TEST_D1

TP_DC_TEST_BJ62 TP_DC_TEST_BJ4

DC_TEST_BH3_BJ2 DC_TEST_BG64_BH65 DC_TEST_BH1_BG2 TP_DC_TEST_BF65 TP_DC_TEST_BF1 DC_TEST_B3_C2 DC_TEST_B63_A64 TP_DC_TEST_A62 TP_DC_TEST_A4

=PP1V8_S0_CPU_VCCPLL_R

=PP1V5_S3_CPU_VCCDQ CPU_VCCIO_SEL

CPU_AXG_VALSENSE_N CPU_AXG_VALSENSE_P

CPU_AXG_SENSE_N

CPU_VCCSENSE_N CPU_VCCSENSE_P CPU_VCCSA_VID<1>

CPU_VCCSA_VID<0>

CPU_VIDALERT_L_R CPU_VIDSCLK_R CPU_VIDSOUT_R

2

R13621

2

R13701

2

R13711

2

R13671

2

R13681

2

U1000

R46 R42

N43

B29 A44 A40 A38 A34 A32 A28 A26

N39 N37 N33 N30 N26 N24 N20 M46 M42 R40

M40 M36 M34 M29 M27 M23 M21 L44 L40 L38 R36

L34 L32 L28 L26 L22 K45 K43 K41 K37 K35 R34

K31 K29 K25 J44 J40 J38 J34 J32 J28 J26 R29

H45 H43 H41 H37

H35 H31 H29 H25 G44 G40

G34 G32 G28 G26 F45 F43 F41 F37 F35 R23

F31 F29 F25 E44 E40 E38 E34 E32 E28 E26 R21

D45 D43 D41 D37 D35 D31 D29 C44 C40 C38 N45

C34 C32 C28 C26 B45 B43 B41 B37 B35 B31

U1000

A4 A62 A64 B3 B63 B65 BF1 BF65 BG2 BG64 BH1 BH3 BH63 BH65 BJ2 BJ4 BJ62 BJ64 C2 C64 D1 D65

F49

B49 F47 B47

D47

AV23 AT23 AP23 AL23 AJ8

AW10

AK65 AK63 AK61

AV21 AT21 AP21 AL21

W17 W15

N16 N14 M17 M15 M12 M11 L18 L14

W12 U17 U15 U12 T16 T14 T11 N18

K3

AE10 AG10

AY19

B51 D51 A50

BJ60 BJ6

E64 E2 B61 B5 A60 A6

BH61 BH5 BE64 BE2 BD65 BD1 F65 F1

A46

AU10

AW20

C48 E50

A48

051-9589 4.18.0

Trang 14

(7 OF11)

VDDQVAXG

(8 OF 11)

VSSVSS

(11 OF 11)

VSSVSS

REVISION

BRANCH

OMIT_TABLE

IVY-BRIDGEBGA

OMIT_TABLE BGAIVY-BRIDGE

OMIT_TABLE

IVY-BRIDGEBGA

OMIT_TABLE BGAIVY-BRIDGE

CPU POWER AND GND

U1000

AV55 AV53

AU20 AU18 AT55 AT53 AT48 AT17 AT15 AT12 AR58 AR56 AV48

AR52 AR49 AR20 AR18 AR16 AR14 AP55 AP53 AP48 AN58 AV17

AN56 AN52 AN49

AN20 AN18 AN16 AN14 AM11 AL55 AL53 AV15

AL48 AL17 AL15 AL12 AK58 AK56 AJ17 AJ15 AJ12 AH16 AV12

AH14 AH11 AF16 AF14 AE17 AE15 AE12 AD11 AC17 AC15 AU58

AC12 AB16 AB14 Y16 Y14 Y11

AU56 AU52 AU49

U1000

AH65 AH63

AE64 AE62 AE60 AD65 AD63 AD61 AD58 AD56 AB65 AB63 AH61

AB61 AB58 AB56 AA64 AA62 AA60 Y58 Y56 W64 W62 AH58

W60 V65 V63 V61 V58 V56 T65 T63 T61 T58 AH56

T56 R64 R62 R60 R55 R53 R48 N64 N62 N60 AG64

N58 N56 N52 N49 M65 M63 M61 M59 M55 M53 AG62

M48 L56 L52 L48

AG60 AF58 AF56

BJ36 BJ28

AY47 AY43 AY39 AY35 AY31 AY27 AY23 AV46 AV42 AV40 BG40

AV36 AV34 AV29 AV27 AU45 AU43 AU39 AU37 AU33 AU30 BG32

AU26 AU24 AT46 AT42 AT40 AT36 AT34 AT29 AT27 AR45 BD47

AR43 AR39 AR37 AR33 AR30 AR26 AR24 AP46 AP42 AP40 BD43

AP36 AP34 AP29 AP27 AN45 AN43 AN39 AN37 AN33 AN30 BD39

AN26 AN24 AL46 AL42 AL40 AL36 AL34 AL29 AL27

BD31 BD23 BB35

U1000

AG12 AF65 AF63 AF61 AF11 AF9 AF5 AE57 AD16 AD14 AD7 AD3 AD1 AC64 AC62 AC60 AC57 AB11 AB9 AB5 AA57 AA17 AA15 AA12 Y65 Y63 Y61 Y7 Y3 Y1 W57 V16 V14 V11 V9 V5 U64 U62 U60 U57 T7 T3 T1 R57 R50 R44 R38 R31 R25 R19 R17 R15 R12 P65 P63 P61 P11 P9 P5 N54 N47 N41 N35 N28 N22 M57 M50 M44 M38 M31 M25 M19 M7 M3 M1 L64 L62 L60 L58 L54 L50 L46 L42 L36 L30 L24

L20 L16 L12 L8 K39 K33 K27 K1 J64 J60 J56 J52 J48 J46 J42 J36 J30 J24 J22 J18 J14 J10 J6 H39 H33 H27 H3 G62 G58 G54 G50 G46 G42 G36 G30 G24 G20 G16 G12 G8 F39 F33 F27 E60 E56 E52 E48 E46 E42 E36 E30 E24 E22 E18 E14 E10 E6 E4 D63 D39 D33 D27 C58 C54 C50 C46 C42 C36 C30 C20 C16 C12 C8 B39 B33 B27 A56 A52 A42 A36 A30 A24 A20 A16 A12 A8

AT44 AT38 AT31 AT25 AT19 AT11 AT7 AT3 AT1 AR54 BG52

AR47 AR41 AR35 AR28 AR22 AP65 AP63 AP57 AP50 AP44 BG48

AP38 AP31 AP25 AP19 AP17 AP15 AP12 AP11 AP9 AP5 BG44

AN54 AN47 AN41 AN35 AN28 AN22 AM61 AM7 AM3 AM1 BG36

AL57 AL50 AL44 AL38 AL31 AL25 AL19 AK16 AK14 AK11 BG28

AK9 AK5 AJ64 AJ62 AJ60 AJ57 AH7 AH3 AH1 AG57 BG24

AG17 AG15

BJ8

AV57 AV50 AV44 AV38 AV31 AV25 AV19 AV9 AV5 AU54

051-9589 4.18.0

Trang 15

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

CPU VCCPLL DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1600-C16C7):

PLACEMENT_NOTE (C1620-C1623):

CPU VCCIO/VCCPQ DECOUPLING

Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402 PLACEMENT_NOTE (C1646-C1671):

CPU VCORE DECOUPLING

(Z = 1.2mm, place on short side behind CPU)

PLACEMENT_NOTE (C1624-C16D5):

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

Apple Implementation: 8x 270uF 6mOhm, 0x 470uF 4mOhm , 16x 22uF 0402, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0402 (NOSTUFF)Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

20%

0201 CERM-X6S 4V NOSTUFF

1UF

20%

1UF

10V X6S-CERM 0402

1UF

10%

20%

1UF

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

20%

1UF

20%

1UF

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

Place on bottom side of U1000

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

20%

1UF

20%

1UF

20%

Place near U1000 on bottom side

10UF4V 0402

20%

10UF4V 0402

20%

10UF4V 0402

20%

10UF4V 0402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

10V X6S-CERM 0402

1UF

10%

MF-LF 5%

0

402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

X6S-CERM 060310UF4V 0603

20%

X6S-CERM10UF4V 0603

20%

X6S-CERM10UF

X6S-CERM 060310UF4V 20%

X6S-CERM 060310UF4V 0603

20%

X6S-CERM10UF4V 20%

X6S-CERM 060310UF

X6S-CERM 060310UF4V 20%

X6S-CERM 060310UF4V

0603

0.0101%

1/4W MF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

1UF

20%

PLACE_NEAR=U1000.AK61:5MM

20%

270UF

TANT2V

CRITICAL

CASE-B2-SM

20%

CRITICAL270UF

2VTANTCASE-B2-SM

20%

270UF

CASE-B2-SMTANT2V

CRITICAL

20%

270UF

CASE-B2-SMTANT2V

CRITICAL

20%

270UF

CASE-B2-SMTANT2V

CRITICAL

20%

270UF

CASE-B2-SMTANT2V

CRITICAL

20%

270UF

CASE-B2-SMTANT2V

CRITICAL

20%

270UF

CASE-B2-SMTANT2V

CRITICAL

POLY-TANT2.0V20%

2.0VPOLY-TANT

2V X6T-CERM 0402

20UF

20%

CRITICALPlace near inductors on bottom side

2V X6T-CERM 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

CRITICAL

2V X6T-CERM 0402

20UF

20%

NOSTUFFPlace near inductors on bottom side

CRITICAL

2V X6T-CERM 0402

20UF

20%

NOSTUFFCRITICALPlace near inductors on bottom side

2V X6T-CERM 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

X6T-CERM

2V 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

NOSTUFF

2V X6T-CERM 0402

20UF

20%

NOSTUFF

2V X6T-CERM 0402

20UF

20%

NOSTUFFCRITICAL

2V X6T-CERM 0402

20UF

20%

NOSTUFFCRITICAL

2V X6T-CERM 0402

20UF

20%

Place near inductors on bottom side

2V X6T-CERM

2V X6T-CERM 0402

20UF

20%

2V X6T-CERM 0402

20UF

20%

CRITICALNOSTUFFPlace near inductors on bottom side

2V X6T-CERM 0402

20UF

20%

NOSTUFFPlace near inductors on bottom side

CRITICAL

2V X6T-CERM 0402

20UF

C16121

2

C16111

2

C16101

2

C16A41

2C16A31

2

C16091

2

C16A21

2

C16081

2

C16071

2

C16A11

2C16A01

2

C16311

2

C16061

2

C16191

2

C16051

2

C16181

2

C16041

2

C16171

2

C16031

2

C16021

2

C16161

2

C16151

2

C16011

2

C16141

2

C16001

2

C16131

2

C16301

2C16291

2C1627

1

2C16261

2

C16A61

2C16A51

2

C16201

2

C16211

2

C16221

2

C16231

2

C16251

2C16241

2

C16281

2

C16321

2

C16331

2

C16391

2C16381

2C16371

2C16361

2C16351

2C16341

2C16571

2C16561

2C16551

2C16541

2C16531

2C16521

2C16511

2C16501

2C16491

2C16481

2C16471

2C16461

2

C16641

2

C16631

2

C16621

2

C16611

2

C16601

2

C16591

2

C16711

2

C16701

2

C16691

2

C16681

2

C16671

2

C16661

2

C16651

2

C16751

2C16741

2C16731

2C16721

2

C16791

2C16781

2C16771

2C16761

2

C16811

2C16801

2

R1601

C16A71

2

C16A81

2

C16A91

2

C16B01

2

C16B11

2

C16B21

2

C16B31

2

C16B41

2

C16B51

2

C16B61

2

C16B71

2

C16B81

2

C16B91

2

C16C01

2

C16C71

2C16C61

2C16C51

2C16C41

2C16C31

2C16C1

1

2

C16C21

2

C16D31

2C16D21

2C16D11

2C16D01

2

C16D41

2

C16D51

2C1698

1

2

C16961

2C16951

2C16941

2C16931

2C1691

1

2C16901

2

C1682

1

23

C1683

1

23

051-9589 4.18.0

Trang 16

BRANCH

Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

CPU VCCSA DECOUPLING VAXG DECOUPLING

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

NOSTUFF

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

0402

Place close to U1000 on bottom side

NOSTUFF

4V X6S10UF20%

0402

NOSTUFF

4V X6S 0603

22UF

20%

10V X6S-CERM 0402

1UF

10%

4V X6S10UF20%

0402

10V X6S-CERM 0402

1UF

10%

4V X6S10UF20%

0402

10V X6S-CERM 0402

1UF

10%

4V X6S10UF20%

0402

4V X6S 0603

22UF

20%

4V X6S 0603

22UF

20%

4V X6S 0603

22UF

20%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

4V X6S10UF20%

0402

4V X6S10UF20%

0402

10V X6S-CERM 0402

1UF

10%

4V X6S10UF20%

0402

4V X6S 0603

22UF

20%

4V X6S 0603

22UF

20%

4V X6S 0603

22UF

20%

10V X6S-CERM 0402

1UF

10%

X6S-CERM 0402 10V

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

10V 0402

1UF

10%

X6S-CERM 10V

X6S-CERM 0402

1UF

10%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

X6S-CERM10UF

0603 20%

4V10UF

4V X6S-CERM 0603 20%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

10V X6S-CERM 0402

1UF

10%

10V X6S-CERM 0402

1UF

10%

4V X6S-CERM10UF

0603 20%

4V X6S-CERM10UF

0603 20%

10V X6S-CERM 0402

1UF

10%

4V X6S-CERM10UF

0603 20%

MF 1/4W 1%

0.010

0603

330UF-0.006OHM

POLY 2V CASE-D2-SM

20%

330UF-6MOHM2.0V

CRITICAL

POLY-TANTD15T20%

330UF-6MOHM2.0V

POLY-TANTD15T

CRITICAL

20%

330UF-6MOHM2.0V

POLY-TANT

CRITICAL

D15T20%

CRITICAL

D15T-ECGLT-COMBO

330UF-6MOHM20%

2.0VPOLY-TANT

2

C17161

2

C17151

2

C17141

2

C17131

2

C17121

2

C17111

2

C17101

2

C17091

2

C17081

2

C17071

2

C17061

2

C17251

2

C17241

2

C17331

2C17321

2

C17051

2

C17231

2

C17041

2

C17221

2

C17031

2

C17211

2

C17311

2C17301

2C17291

2

C17021

2

C17011

2

C17201

2

C17191

2

C17001

2

C17181

2

C17281

2C17271

2C17261

2C17461

2C17451

2C17441

2C17431

2C17421

2C17411

2C17401

2C17391

2C17381

2

C17551

2

C17541

2

C17531

2

C17521

2

C17511

2

C17501

2

C17491

2

C17481

2

C17621

2C17611

2

C17671

2C17661

2

C17601

2C17591

2

C17651

2C17641

2

C17581

2

C17631

2

R1700

C17561

2

C1735

1

23

C1737

1

23

C1734

1

23

C1768

1

23

051-9589 4.18.0

Trang 17

ININ

OUTOUT

OUTBI

ININOUTOUT

OUTBI

OUT

SATA3COMPISATA3RCOMPO

SATA0GP/GPIO21SATA1GP/GPIO19SATALED*

SATA3RBIASSATAICOMPO

SATA1RXNSATA0TXPSATA0TXN

SATA2RXNSATA2RXP

HDA_RST*

SPKR

HDA_SDIN0HDA_SDIN1HDA_SDIN3HDA_SDIN2

HDA_SDOHDA_DOCK_EN*/GPIO33HDA_DOCK_RST*/GPIO13

JTAG_TCKJTAG_TMSJTAG_TDIJTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSISPI_MISO

FWH0/LAD0RTCX1

RTCX2

SATA1TXP

SATA0RXNSERIRQLDRQ1*/GPIO23

FWH1/LAD1FWH2/LAD2FWH3/LAD3FWH4/LFRAME*

SATA1RXPSATA1TXN

SATA2TXNSATA2TXPSATA3RXNSATA3RXPSATA3TXNSATA3TXPSATA4RXNSATA4RXPSATA4TXNSATA4TXPSATA5RXNSATA5TXNSATA5TXP

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4PCLKOUT_PCIE4N

CLKOUT_PCIE3PCLKOUT_PCIE3N

PCIECLKRQ1*/GPIO18

PCIECLKRQ2*/GPIO20CLKOUT_PCIE2PCLKOUT_PCIE2N

PCIECLKRQ0*/GPIO73CLKOUT_PCIE1NCLKOUT_PCIE1P

CLKOUT_PCIE0NCLKOUT_PCIE0P

PERN3PETP2PETN2

PERP1PETN1PERN1

SMBCLKSMBALERT*/GPIO11

PETP8

PERP8PETN8

PETP7PERN8PETN7PERP7PERN7

PETN6PETP6PERP6PERN6PETP5PETN5PERP5

PETP4PERN5PETN4PERP4

PETP3PERN4PETN3PERP3

PERN2PERP2PETP1 SMBDATA

PCIECLKRQ5*/GPIO44CLKOUT_PCIE5PCLKOUT_PCIE5N

CLKOUT_PEG_B_P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE6NCLKOUT_PCIE6P

CLKOUT_PCIE7NCLKOUT_PCIE7PPCIECLKRQ7*/GPIO46

CLKOUT_ITPXDP_PCLKOUT_ITPXDP_N

CLKOUTFLEX0/GPIO64CLKOUTFLEX1/GPIO65CLKOUTFLEX2/GPIO66CLKOUTFLEX3/GPIO67

CLKOUT_DMI_NCLKOUT_DMI_P

CLKOUT_DP_PCLKOUT_DP_N

CLKIN_DMI_NCLKIN_DMI_P

CLKIN_GND1_NCLKIN_GND1_P

CLKIN_DOT_96NCLKIN_DOT_96P

CLKIN_SATA_PCLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUTXTAL25_IN

XCLK_RCOMP

CLKOUT_PEG_A_NPEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_P

SML0ALERT*/GPIO60SML0CLKSML0DATA

SML1CLK/GPIO58SML1ALERT*/PCHHOT*/GPIO74

SML1DATA/GPIO75

CL_CLK1CL_DATA1CL_RST1*

OUTOUT

OUTIN

IN

OUT

OUTBI

OUTOUT

ININ

IN

ININOUTOUT

IN

OUTOUT

OUTOUTIN

OUT

OUTOUTOUTOUT

BIBI

OUTBIBI

OUTOUT

NC

OUTOUT

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

II NOT TO REPRODUCE OR COPY ITConnect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

VSel strap not functional (VCCVRM = 1.8V)

Unused clock terminations for FCIM Mode

1.8V -> 1.1V

(IPD-PWROK)

If HDA = S0, must also ensure that signal cannot be high in S3.

(IPD-BOOT)(IPD)

(IPU)(IPD-PLTRST#)

(IPD-PWROK)(IPU-RSMRST#)

(IPD)

(IPU-RSMRST#)

(IPU)(IPU)

(IPD-PWROK)

(IPU)

(IPD-BOOT)(IPU)

(IPU)

Controlled by PCIECLKRQ5#

(IPD)(IPD)(IPD)

201 MF

1/20W 5%

201 MF

20K

1/20W 5%

201 MF

20K

10V

1UF

402 10V

402

1UF

1/20W 1%

201 MF

37.4PLACE_NEAR=U1800.Y11:2.54mm

1/20W 5%

201 MF

10K

PLACE_NEAR=U1800.Y47:2.54mm

90.9

1/20W 1%

201 MF

PANTHERPOINTOMIT_TABLE

201 MF

0

NO STUFF

1/20W 5%

201 MF

0

MF-LF 1%

402

604

1/20W 1%

201 MF

1K

25

1/20W 1%

201 MF

750PLACE_NEAR=U1800.AH1:2.54mm

33

PLACE_NEAR=U1800.N34:1.27mm 5% 1/20W MF 201

33PLACE_NEAR=U1800.L34:1.27mm 5% 1/20W MF 201

33

201 MF 1/20W

33

1/20W 5%

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_DATE=01/13/2012SYNC_MASTER=D2_KEPLER

PCIE_CLK100M_PCH_N

TP_PCIE_CLK100M_PEBN

TP_PCH_GPIO64_CLKOUTFLEX0SYSCLK_CLK25M_SB_R

ENET_CLKREQ_L

HDA_BIT_CLKXDP_DC3_PCH_GPIO19_SATARDRVR_EN

RTC_RESET_L

HDA_SYNC_R

SMBUS_PCH_ALERT_L

LPC_FRAME_R_LTP_LPC_DREQ0_L

PCIE_AP_R2D_C_N

FW_CLKREQ_LSSD_CLKREQ_L

PCIE_CLK100M_SSD_P

PCH_SATA3RBIASPCH_SATA3COMP

SMBUS_PCH_ALERT_LSMBUS_PCH_CLK

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCIE_7_R2D_CNTP_PCIE_6_R2D_CPTBT_PWR_EN_PCH

PCH_SATALED_LPCH_INTRUDER_L

TP_PCIE_8_D2RN

TP_PCIE_5_R2D_CNTP_PCIE_5_R2D_CPTP_PCIE_6_D2RNTP_PCIE_6_D2RPTP_PCIE_6_R2D_CNTP_PCIE_7_D2RNTP_PCIE_7_D2RP

TP_PCIE_8_D2RPTP_PCIE_8_R2D_CP

TP_PCIE_7_R2D_CP

TP_PCIE_8_R2D_CN

TP_PCIE_5_D2RNTP_PCIE_5_D2RPPCIE_EXCARD_R2D_C_P

PCIE_CLK100M_ENET_PPCIE_CLK100M_ENET_N

PCIE_FW_R2D_C_N

PCIE_ENET_R2D_C_PPCIE_AP_D2R_NPCIE_AP_D2R_P

LPC_SERIRQSATA_HDD_D2R_N

SATA_ODD_D2R_NSATA_ODD_D2R_PSATA_ODD_R2D_C_NSATA_ODD_R2D_C_P

TP_SATA_C_R2D_CNTP_SATA_C_R2D_CP

TP_SATA_D_D2RPTP_SATA_D_R2D_CNTP_SATA_D_R2D_CPTP_SATA_E_D2RNTP_SATA_E_D2RP

USB_EXTB_SEL_XHCI

=PP1V05_S0_PCH_VCCIO_SATA

ENET_CLKREQ_L

PCIE_FW_D2R_NPCIE_FW_D2R_PLPC_AD_R<1>

TP_SATA_E_R2D_CPTP_SATA_E_R2D_CN

TP_SATA_F_D2RN

PCH_CLK100M_SATA_NPCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLKPCH_CLKIN_GNDP1PCH_CLKIN_GNDN1

JTAG_DPMUXUC_TRST_L

ENET_MEDIA_SENSE_RDIVUSB_EXTD_SEL_XHCIUSB_EXTB_SEL_XHCI

PEG_CLKREQ_LEXCARD_CLKREQ_L

DP_AUXCH_ISOLPCH_SPKR

HDA_SDOUT_R

=PP1V05_S0_PCH_VCCDIFFCLK

SML_PCH_1_CLKSML_PCH_1_DATA

ITPCPU_CLK100M_P

ENET_MEDIA_SENSE_RDIV

XDP_PCH_TMS

TP_SATA_C_D2RPLPC_AD_R<3>

LPC_AD_R<1>

TP_SATA_C_D2RNTP_HDA_SDIN2

TP_CLINK_CLKTP_CLINK_DATATP_CLINK_RESET_L

SMBUS_PCH_DATA

SML_PCH_0_CLKSML_PCH_0_DATA

USB_EXTD_SEL_XHCI

DMI_CLK100M_CPU_NDMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPNTP_PCH_CLKOUT_DPP

TP_SATA_F_D2RPTP_SATA_F_R2D_CP

PCIE_CLK100M_PCH_N

HDA_SYNC_RLPC_AD_R<2>

PCH_SATALED_L

SATA_HDD_R2D_C_NSATA_HDD_D2R_P

PCH_INTVRMEN_LPCH_SRTCRST_LRTC_RESET_L

HDA_SDOUT

ITPCPU_CLK100M_N

PCH_CLK100M_SATA_PPCH_CLK96M_DOT_N

ITPXDP_CLK100M_PITPXDP_CLK100M_NTBT_CLKREQ_LPCIE_CLK100M_TBT_NPEG_CLKREQ_LPEG_CLK100M_P

PCH_SATAICOMP

=PP1V05_S0_PCH

PCIE_CLK100M_FW_PPCIE_CLK100M_FW_NPCH_SRTCRST_L

PCIE_CLK100M_SSD_NTP_PCIE_CLK100M_PE4NPCIE_CLK100M_EXCARD_N

2

R18021

2

R18031

2

C18031

2C18021

2

R18301

2

R18201

D36

N34

C36 N32

K34

E34 G34 C34 A34

E36 K36 D20

A20 C20

V14

AM3 AM1 AP7 AP5

P1

AM10 AM8 AP11 AP10 AD7 AD5 AH5 AH4

AB13 AH1 AB12

AB8 AB10 AF3 AF1 Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y10 Y11

P3

V5

T3

Y14 T1

U3 V4

T10

G22

U1800

M7 T11

P10

BF18 BE18

G24 E24

BJ30 BG30

H45

AK7 AK5

AV22 AU22

AM12 AM13

AK14 AK13

Y40 Y39

AB49 AB47

AA48 AA47

Y37 Y36

Y43 Y45

V45 V46

V40 V42

V38 V37

AB37 AB38

AB42 AB40

A12 C8 G12

C13 E14 M16

Y47

V47 V49

Trang 18

OUTOUTOUTOUTOUT

FDI_RXP3

FDI_RXP1FDI_RXP2

FDI_RXP5FDI_RXP4

FDI_RXP7FDI_INTFDI_FSYNC0

FDI_LSYNC0FDI_FSYNC1

FDI_LSYNC1

DMI2TXNDMI1TXNDMI3TXN

DMI3TXP

FDI_RXN0FDI_RXN1FDI_RXN3FDI_RXN2FDI_RXN4FDI_RXN5DMI0RXN

FDI_RXP6DMI1RXN

DMI0TXP

DMI3RXPDMI2RXPDMI1RXPDMI0RXPDMI3RXNDMI2RXN

DMI2TXP

DMI2RBIASDMI_IRCOMP

SUS_STAT*/GPIO61

SLP_S4*

SLP_S5*/GPIO63SUSCLK/GPIO62

SLP_SUS*

SLP_A*

SLP_S3*

PMSYNCHSLP_LAN*/GPIO29

SYS_RESET*

SYS_PWROKPWROKAPWROKDRAMPWROKRSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30PWRBTN*

ACPRESENT/GPIO31BATLOW*/GPIO72RI*

DSWVRMENDPWROKWAKE*

DDPD_AUXNDDPD_AUXPDDPD_CTRLDATADDPD_CTRLCLKDDPC_3PDDPC_3NDDPC_2PDDPC_2N

DDPC_0PDDPC_1PDDPC_1NDDPC_0NDDPC_HPD

DDPC_AUXNDDPC_AUXPDDPC_CTRLDATADDPC_CTRLCLKDDPB_3PDDPB_3N

DDPB_1PDDPB_2PDDPB_2NDDPB_1NDDPB_0P

DDPB_HPDDDPB_0N

DDPB_AUXNDDPB_AUXP

SDVO_CTRLCLKSDVO_CTRLDATASDVO_INTPSDVO_INTNSDVO_STALLPSDVO_STALLNSDVO_TVCLKINPSDVO_TVCLKINN

L_CTRL_CLK

DAC_IREFCRT_IRTNCRT_VSYNCCRT_HSYNCCRT_DDC_DATACRT_DDC_CLKCRT_REDCRT_GREENCRT_BLUE

L_VDD_EN

L_DDC_DATA

L_CTRL_DATALVD_IBGLVD_VREFHLVD_VREFL

LVDSA_CLKLVDSA_CLK*

LVDSB_CLKLVDSB_DATA0*

LVDSB_DATA1*

LVDSB_DATA2*

LVDSB_DATA0LVDSB_DATA3*

LVDSB_DATA3

LVDSB_DATA1LVDSB_DATA2

L_DDC_CLKL_BKLTCTLL_BKLTEN

OUT

ININ

IN

INININ

INBIOUTOUTOUTOUTOUT

OUT

IN

OUTOUT

OUT

OUTOUTOUT

OUT

OUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUTOUTOUT

OUTIN

INININININININ

INININININ

INININ

REVISION

BRANCH

(IPD-PLTRST#)

(IPD)(IPD)(IPD)(IPD)

(IPD)(IPD)

FCBGA

MOBILE OMIT_TABLE

390K5%

1/20WMF201

18 70

100K5%

MF2011/20W

1/20WMF201

201MF5%

100K

201MF1/20W5%

MAKE_BASE=TRUE

PCH_DMI_COMP DMI_S2N_P<3>

DPA_IG_AUX_CH_N DPA_IG_AUX_CH_P

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

TP_SDVO_INTP TP_SDVO_INTN TP_SDVO_STALLP TP_SDVO_STALLN TP_SDVO_TVCLKINP TP_SDVO_TVCLKINN

TP_LVDS_IG_CTRL_CLK

PCH_DAC_IREF TP_CRT_IG_VSYNC TP_CRT_IG_HSYNC TP_CRT_IG_DDC_DATA TP_CRT_IG_DDC_CLK TP_CRT_IG_RED TP_CRT_IG_GREEN TP_CRT_IG_BLUE

LVDS_IG_PANEL_PWR

LVDS_IG_DDC_DATA

TP_LVDS_IG_CTRL_DATA LVDS_IG_DDC_CLK LVDS_IG_BKL_PWM LVDS_IG_BKL_ON

LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P LVDS_IG_A_DATA_N<0>

=FDI_LSYNC<0>

=PP3V3_S5_PCH

PM_PWRBTN_L

MEM_VDD_SEL_1V5_L PM_CLKRUN_L

PM_SLP_S3_L PM_SLP_S4_L PM_SLP_SUS_L PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LVDS_IG_PANEL_PWR LVDS_IG_BKL_ON

E22

B13

A18

AV12BC10AW16

AV14BB10

BJ14AY14BE14BH13BC12BJ12BG10BG9BG14BB14BF14BG13BE12BG12BJ10BH9

AP14E20

G16

G8C12

M47

T42

T49

M49T43

AV42AV40AV45AV46AU48AU47AV47AV49

AT49AT47AT40

AY47AY49AY43AY45BA47BA48BB47BB49

AP47AP49

P46P42

AT38

BB43BB45BF44BE44BF42BE42BJ42BG42

AT45AT43

M43M36

BH41

P45J47

T45P39

T40K47M45

AF37AF36AE48AE47

AK40AK39

AN47AN48

AM49AM47

AK49AK47

AJ47AJ48

AF39AF40

AH43AH45

AH49AH47

AF47AF49

AF43AF45

P38M39

AP39AP40

AM42AM40

AP43AP45

051-9589 4.18.0

Trang 19

RSVD8RSVD9RSVD10RSVD12

USBP0NUSBP0PUSBP1NUSBP2NUSBP1P

USBP2PUSBP3N

USBP4NUSBP3P

USBP4PUSBP5NUSBP5PUSBP6PUSBP6N

USBP7NUSBP7P

USBP8PUSBP8N

USBP9NUSBP9P

USBP10PUSBP10N

USBP11NUSBP11P

USBP12PUSBP12N

USBP13NUSBP13P

OC0*/GPIO59

USBRBIAS*

USBRBIAS

OC1*/GPIO40OC2*/GPIO41OC3*/GPIO42OC4*/GPIO43OC5*/GPIO9OC6*/GPIO10OC7*/GPIO14

PIRQA*

PIRQB*

PIRQC*

REQ1*/GPIO50PIRQD*

REQ3*/GPIO54REQ2*/GPIO52

GNT1*/GPIO51GNT2*/GPIO53GNT3*/GPIO55PIRQE*/GPIO2PIRQF*/GPIO3PIRQG*/GPIO4

PME*

PIRQH*/GPIO5

PLTRST*

CLKOUT_PCI0CLKOUT_PCI2CLKOUT_PCI1

CLKOUT_PCI4CLKOUT_PCI3

RSVD1TP1

TP2 RSVD2

RSVD3TP3

TP4 RSVD4

RSVD5TP5

TP6

RSVD6RSVD7TP7

TP8TP9TP10

RSVD11TP11

RSVD13TP14

RSVD14RSVD15TP15

TP16

RSVD16RSVD17TP17

TP18

RSVD18RSVD19TP19

TP20

RSVD20RSVD21RSVD22RSVD23RSVD24RSVD25RSVD27RSVD26

RSVD28RSVD29

TP13TP12

TP23TP22TP21

USB3RN4USB3RN3USB3RN2

USB3TN2USB3TN1USB3TN3USB3TN4USB3TP1USB3TP2USB3TP3USB3TP4TP24

NCNC

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NC

NCNCNC

NCNCNCNCNC

BIBI

BIBIBIBIBIBI

BIBI

OUTOUTININ

OUTOUT

OUT

IN

OUTOUT

INININ

ININININ

INOUTINBI

IN

BI

BIBI

OUT

OUTOUT

4 5

7 8

REVISION

BRANCH

Ext D (EHCI) RSVD: WiFi

MOBILE FCBGA

10K

MF 1/20W

10K

NO STUFF10K

PLACE_NEAR=U1800.B33:2.54mm22.6

PCH PCI/USB/TP/RSVD

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_LXDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

TP_PCH_STRP_ESI_LPCH_STRP_TOPBLK_SWP_L

AUD_IP_PERIPHERAL_DETTP_PCH_STRP_BBS1

PCH_CLK33M_PCIOUT

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA3_PCH_GPIO42_USB_EXTD_OC_LXDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_LTP_PCH_TP23

=PP3V3_S3_PCH_GPIO

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGEXDP_DA0_PCH_GPIO59_USB_EXTA_OC_LXDP_DA1_PCH_GPIO40_USB_EXTB_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA3_PCH_GPIO42_USB_EXTD_OC_LAUD_IP_PERIPHERAL_DET

USB3_EXTB_RX_PUSB3_EXTC_RX_PUSB3_EXTA_RX_N

PCI_INTD_LPCI_INTC_LPCI_INTB_L

USE_HDD_OOB_LBLC_I2C_MUX_SELJTAG_GMUX_TMS

USB3_EXTC_TX_PUSB3_EXTD_TX_P

USB3_EXTC_TX_NUSB3_EXTB_TX_N

USB3_EXTD_RX_NUSB3_EXTC_RX_NUSB3_EXTB_RX_N

USB_CAMERA_NUSB_HUB_UP_PTP_USB_WLANP

TP_USB_4PTP_USB_4N

USB_EXTB_XHCI_PUSB_EXTA_N

PLT_RESET_L

TBT_PWR_REQ_L

BLC_GPIOUSE_HDD_OOB_LBLC_I2C_MUX_SEL

USB_EXTA_PUSB_EXTB_XHCI_N

USB_EXTD_XHCI_PUSB_EXTD_XHCI_NUSB_EXTC_P

USB3_EXTB_TX_P

TP_USB_12P

USB_EXTB_EHCI_NUSB_EXTB_EHCI_PUSB_EXTD_EHCI_N

TP_USB_BT_HSN

USB_CAMERA_PUSB_HUB_UP_NTP_USB_WLANNTP_USB_SDPTP_USB_SDN

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGEXDP_DB2_PCH_GPIO10_AP_PWR_ENTP_USB_13P

USB_EXTD_EHCI_P

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

TP_USB_13N

R20701

2U1800

H49 H43 J48 K42 H40

D47 E42 F46

A14 K20 B17 C16 L16 A16 D14 C14

K40 K38 H38 G38

G42 G40 C42 D44

C6 K10

C46 C44 E40

AY7

AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 AV7

BE8 BD4 BF6 AV5 AV10

AT8 AY5 BA2 AT12 BF3

AU3 BG4 AT10 BC8

AU2 AT4 AT3 BG26

C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 BJ26

AB45 B21 M20 AY16 BG46

BH25 BJ16 BG16 AH38 AH37 AK43 AK45

BE28 BC30 BE32 BJ32

BC28 BE30 BF32 BG32

AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

C24 A24

C30 A30 L32 K32 G32 E32

C32 A32

C25 B25

C26 A26 K28 H28 E28 D28

C28 A28

C29 B29 N28 M28 L30 K30

G30 E30

B33 C33

Trang 20

OUTBIIN

BI

ININ

OUTOUTIN

OUT

SATA2GP/GPIO36SATA3GP/GPIO37

VSS_NCTF_30VSS_NCTF_31VSS_NCTF_29

VSS_NCTF_27VSS_NCTF_28

VSS_NCTF_15VSS_NCTF_16VSS_NCTF_14NC_1TS_VSS4TS_VSS3

TS_VSS1TS_VSS2DF_TVSINIT3_3V*

THRMTRIP*

PROCPWRGDRCIN*

PECIA20GATE

TACH7/GPIO71TACH6/GPIO70TACH5/GPIO69TACH4/GPIO68

VSS_NCTF_0VSS_NCTF_1SATA5GP/GPIO49/TEMP_ALERT*

SLOAD/GPIO38

GPIO27GPIO24

GPIO57SDATAOUT1/GPIO48

BMBUSY*/GPIO0TACH1/GPIO1

LAN_PHY_PWR_CTRL/GPIO12GPIO15

SATA4GP/GPIO16TACH2/GPIO6

SDATAOUT0/GPIO39GPIO35

SCLOCK/GPIO22TACH0/GPIO17

GPIO8TACH3/GPIO7

GPIO28STP_PCI*/GPIO34

GPIO CPU/MISC(6 OF 10)

OUTOUT

OUT

BIIN

OUTIN

OUTININ

OUT

08Y1 Y2 GND B2

VCC

A1 B1 A2

OUT

OUTIN

ININ

TABLE_BOMGROUP_ITEMBOM OPTIONS

REVISION

BRANCH

(IPD-PLTRST#)

(IPD-PLTRST#?)

(IPU-DeepS4/S5)(IPU-RSMRST#)

(IPU)

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPU)

(IPD)

Set to Vcc when HighSet to Vss when LowDF_TVS:DMI & FDI Term Voltage(IPU-RSMRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

Must stuff R2197 when R2180 NO STUFFed.

JTAG Isolation due to glitch in and out of sleepNOTE: TCK from PCH is Push-Pull CMOSNOTE: TDO from CR is Push-Pull CMOS

(TBT_CIO_PLUG_EVENT_ISOL)

Stuff R2160 or R2574, not both

TBT_PWR_EN goes high for JTAG Programming(IPD-PLTRST#)

current limiting 1K resistor R2574 Connects to PCH through

201 MF

10KRAMCFG3:H

1/20W 5%

201 MF

10KRAMCFG2:H RAMCFG1:H

1/20W 5%

201 MF

10K

1/20W 5%

201 MF

10KRAMCFG0:H

PANTHERPOINTOMIT_TABLE

1/20W 5%

201 MF

1K

1/20W 5%

201 MF

2.2K

201 1/20W

10K

201 MF 1/20W 5%

10K

201 1/20W

100K

MF 5%

201 MF 1/20W 5%

201 MF

43

NO STUFF

1/20W 5%

201 MF

0

1/20W 5%

201 MF

10K

SSM3K15FVSOD-VESM-HFCRITICAL

MF 1/20W 5%

201

10K

CRITICAL

SSM6N15AFESOT563

201 1/20W

5%

201 MF

10K

1/20W

1/20W 5%

201 MF

TBT_CIO_PLUG_EVENT_ISOL

JTAG_TBT_TDI

=PP3V3_S0_PCH_GPIOSPIROM_USE_MLB

TBT_GO2SX_BIDIR

SMC_WAKE_SCI_LAUD_IPHS_SWITCH_EN_PCH

=PP3V3_SUS_PCH_GPIO

=PP3V3_S5_PCH_GPIO

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SELODD_PWR_EN_L

=PP3V3_S0_PCH_GPIO

JTAG_ISP_TDITBT_SW_RESET_R_L

FW_PWR_EN_PCH

SPIROM_USE_MLBXDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

ODD_PWR_EN_L

TP_PCH_GPIO8

FW_PME_LXDP_FC1_PCH_GPIO0

=PP3V3_S0_PCH_GPIO

WOL_ENPCH_A20GATEFW_PWR_EN_PCH

SMC_RUNTIME_SCI_L

XDP_FC1_PCH_GPIO0FW_PME_L

TBT_SW_RESET_R_L

PCH_RCIN_L

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCKXDP_FC0_PCH_GPIO15

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDOJTAG_ISP_TDO

PCH_PECI

PCH_PROCPWRGD

CPU_PECIMLB_RAMCFG2

=PP3V3_S0_PCH_GPIO

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

MLB_RAMCFG0MLB_RAMCFG3

PM_THRMTRIP_LCPU_PWRGD

PCH_INIT3V3_LPM_THRMTRIP_L_RPCH_A20GATE

XDP_DC1_PCH_GPIO35_MXM_GOOD

PCH_RCIN_L

PCH_DF_TVSXDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

SMC_WAKE_SCI_LXDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

2

R21741

2

R21751

2U1800

P4 T7

AY1

G2

E8

E16 P8

K4

D6

C10

T14 C4

P37

AU16

AY11 P5

V8 M5 U2

V3

T5

M3

V13 N2 K1 D40

A42

H36 E38

C40 B41

C41 A40

AY10

AH8 AK11 AH10 AK10

A4

BD49 BE1 BE49 BF1 BF49

BG2 BG48 BH3 BH47 BJ4

BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 A45

E49 F1 F49

A46 A5 A6 B3 B47 BD1

R21781 2

R21791

2

R21611

2

R21631

2

U2100

1

52

2

R21131

2

R21661

2

051-9589 4.18.0

Trang 21

NC

NCNC

NC

VCCTX_LVDSVCCTX_LVDSVCCTX_LVDSVCCTX_LVDS

VSSALVDSVCCALVDS

VCC3_3_7_HVCMOSVCC3_3_6_HVCMOS

VCCCOREVCCCORE

VSSADACVCCADAC

VCCDMI_2_FDIVCCIO_27_PLLFDIVCCAFDIPLLVCCVRM_2_FDI

VCCIO_26_DPVCC3_3_3_PCIE

VCCIO_24_PCIEVCCIO_25_DP

VCCIO_21_PCIEVCCIO_22_PCIEVCCIO_23_PCIE

VCCIO_19_PCIEVCCIO_20_PCIEVCCIO_18_PCIEVCCIO_17_PCIEVCCIO_16_FDIVCCIO_15_FDIVCCAPLLEXPVCCIO_28_PLLPCIE

VCCSPIVCCDFTERMVCCDFTERMVCCDFTERMVCCDFTERM

VCCCORE

VCCCOREVCCCORE

VCCCOREVCCCOREVCCCOREVCCCOREVCCCOREVCCCOREVCCCORE

VCCCOREVCCCOREVCCCOREVCCCOREVCCCORE

VCCVRM_3_DMIVCCDMI_1_DMIVCCCLKDMI

DCPSUSBYPVCCACLK

DCPRTC

VCCADPLLAVCCADPLLB

DCPSST

DCPSUS_2_CLKDCPSUS_1_CLK

VCCDIFFCLKNVCCDIFFCLKNVCCDIFFCLKN

VCCDSW3_3

VCCIO_7_CLK

VCC3_3_5_CLK

VCCASW_2_CLKVCCASW_3_CLKVCCASW_4_CLKVCCASW_5_CLKVCCASW_6_CLKVCCAPLLDMI2

VCCASW_18_CLK

VCCASW_8_CLKVCCASW_9_CLKVCCASW_10_CLKVCCASW_11_CLKVCCASW_12_CLKVCCASW_13_CLKVCCASW_14_CLKVCCASW_15_CLKVCCASW_16_CLKVCCASW_17_CLKVCCASW_7_CLK

VCCVRM_4_CLK

VCCASW_20_CLKVCCASW_19_CLK

VCCSSC

VCCASW_1_CLKDCPSUS_3_CLKVCCIO_14_PLLCLK

VCCIO_30_USBVCCIO_29_USBVCCIO_31_USBVCCIO_32_USBVCCIO_33_USBVCCSUS3_3_7_USBVCCSUS3_3_8_USB

VCCSUS3_3_6_USBVCCSUS3_3_10_USBVCCSUS3_3_9_USB

DCPSUS_4_USBV5REF_SUS

VCCSUS3_3_1_USB

VCC3_3_2_SATAVCCIO_5_PLLSATA

VCCIO_13_SATA3VCCIO_12_SATA3

VCCAPLLSATAVCCIO_6_PLLSATA3

VCCIO_2_SATAVCCVRM_1_SATA

VCCIO_4_SATAVCCIO_3_SATA

VCCASW_22_MISCVCCASW_23_MISCVCCASW_21_MISC

V5REFVCCSUS3_3_2_GPIOVCCSUS3_3_4_GPIOVCCSUS3_3_3_GPIOVCCSUS3_3_5_GPIOVCC3_3_1_GPIOVCC3_3_8_GPIOVCC3_3_4_GPIO

4 5

7 8

REVISION

BRANCH

VCCAPLLDMI2 pin left as NC per DG

1.44 A Max, 474mA Idle

PCH output, for decoupling only

10 mA Max, 1mA Idle

NC-ed per DG AL24 left as NC per DG

VCCACLK pin left as NC per DG

55mA Max, 5mA Idle

NC-ed per DG

VCCAPLLSATA pin left as NC per DG

VCCAFDIPLL pin left as NC per DG

PLACE_NEAR=U1800.A22:2.54mm

0.1UF402CERM10V

PLACE_NEAR=U1800.A22:2.54mm

1UF402CERM10%

FCBGA

MOBILE OMIT_TABLE

SYNC_DATE=03/19/2012SYNC_MASTER=D2_CLEAN

PCH POWER

=LVDS_VCCA PP3V3_S0_PCH_VCCA_DAC_F

PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mmVOLTAGE=3.3V

AC23AD21AD23AF21AF23AG21AG23AG24

AG16AG17AJ16AJ17AT20

AU20

AN16AN17AN21AN26AN27AP21AP23AP24AP26AT24AN33AN34

AP17AN19

V1

AM37AM38AP36AP37

AL24

AN23V12

P34M26

BJ8

AA16

AJ2T34

T38

W16AD49

BD47BF47BH23

AK1

AA19

AC29AC31AD29AD31W21W23W24W26W29W31AA21

W33

T19

T21V21

AA24AA26AA27AA29AA31AC26AC27

AF33AF34AG34

T16

AH13AH14AL29

AC16N26

AC17

P26P28T27T29

AN24V24

N20N22P20P22

P24

T23T24V23

P32

AF11Y49

051-9589 4.18.0

Trang 22

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSS

VSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSS(9 OF 10)

VSS

VSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSS

VSSVSSVSSVSSVSS

VSSVSS

VSS

VSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSS

VSSVSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSS

VSS

VSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSS

(10 OF 10)VSS

REVISION

BRANCH

PCH GROUNDS

U1800

H5AA17

AB43

AM39AM43AM45AM46AM7AN2AN29AN3AN31AP12AB5

AP19AP28AP30AP32AP38AP4AP42AP46AP8AR2AB7

AR48AT11AT13AT18AT22AT26AT28AT30AT32AT34AC19

AT39AT42AT46AT7AU24AU30AV16AV20AV24AV30AC2

AV38AV4AV43AV8AW14AW18AW2AW22AW26AW28AC21

AW32AW34AW36AW40AW48AV11

AY12AY22AY28

AC24AC33AC34AC48AA2

AD10AD11AD12AD13AD19AD24AD26AD27AD33AD34AA3

AD36AD37AD38AD39AD4AD40AD42AD43AD45AD46AA33

AD8AE2AE3AF10AF12AD14AD16AF16AF19AF24AA34

AF26AF27AF29AF31AF38AF4AF42AF46AF5AF7AB11

AF8AG19AG2AG31AG48AH11AH3AH36AH39AH40AB14

AH42AH46AH7AJ19AJ21AJ24AJ33AJ34AK12AK3

AB39

AK38AK4AK42AK46AK8AL16AL17AL19AL2AL21AB4

AL23AL26AL27AL31AL33AL34AL48AM11AM14AM36

U1800

AY4

AY42AY46AY8B11B15B19B23B27B31

B35

B39B7F45BB12BB16BB20BB22BB24BB28BB30BB38BB4BB46BC14BC18BC2BC22BC26BC32BC34BC36BC40BC42BC48BD46BD5BE22BE26BE40BF10BF12BF16BF20BF22BF24BF26BF28BD3BF30BF38BF40BF8BG17BG21BG33BG44BG8BH11BH15BH17BH19H10BH27BH31BH33BH35BH39BH43BH7D3D12D16D18D22D24D26D30D32D34D38D42D8E18E26G18G20G26G28G36G48H12H18H22H24H26H30H32H34F3

H46K18K26K39K46K7L18L2L20L26L28L36L48M12P16M18M22M24M30M32M34M38M4M42M46M8N18P30N47P11P18T33P40P43P47P7R2R48T12T31T37T4W34T46T47T8V11V17V26V27V29V31V36V39V43V7W17W19W2W27W48Y12Y38Y4Y42Y46Y8

BG29N24AJ3AD47

B43BE10BG41

G14H16

T36

BG22

BG24C22

AP13

M14AP3AP1BE16BC16BG28BJ28

051-9589 4.18.0

23 OF 132

22 OF 99

Trang 23

4 5

7 8

REVISION

BRANCH

69 mA

PCH VCCSUS3_3 BYPASS (PCH SUSPEND USB 3.3V PWR)

PCH VCCADPLLB Filter

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

(PCH PCI 3.3V PWR) PCH VCC3_3 BYPASS

(PCH USB 1.05V PWR) PCH VCCIO BYPASS

(PCH 1.05V CORE PWR) PCH VCCCORE BYPASS

PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)

1 mA

<1 mA

68 mA (PCH DPLLA PWR)

PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)

PCH VCCADPLLA Filter

10%

X5R1UF

PLACE_NEAR=U1800.P34:2.54mm

402

1005%

1/16W

0.1UF40220%

PLACE_NEAR=U1800.M26:2.54mm

CERM

SOT-363BAT54DW-X-G402

MF-LF5%

10

SOT-363BAT54DW-X-G

10%

0.1UF16V0402X7R-CERM

PLACE_NEAR=U1800.AJ2:2.54mm

0.1UF40220%

CERM

0.1UF40220%

10VCERM

10%

4026.3V1UF

PLACE_NEAR=U1800.AT20:2.54mm

CERM

10%

PLACE_NEAR=U1800.BH29:2.54mm

10%

PLACE_NEAR=U1800.V24:2.54mm

10%

0.1UFX5R

PLACE_NEAR=U1800.AA16:2.54mm

10%

4026.3V1UF

PLACE_NEAR=U1800.AN27:2.54mm

CERM

10%

4026.3V1UF

PLACE_NEAR=U1800.AG33:2.54mm

CERM

10%

4026.3V

PLACE_NEAR=U1800.AF34:2.54mm

1UFCERM

10%

4026.3V1UF

PLACE_NEAR=U1800.AF17:2.54mm

CERM

10%

4026.3V1UF

CERMX5R

PLACE_NEAR=U1800.AC17:2.54mm

CERM

0.1UF40220%

PLACE_NEAR=U1800.T16:2.54mm

10VCERM

10%

4026.3V1UF

CERM

10%

0.1UFX5R

10%

4026.3V

PLACE_NEAR=U1800.AH13:2.54mm

1UFCERM

10%

4026.3V1UF

CERM

10%

X5R20%

6036.3V10UF

10%

4026.3V1UF

CERM10%

4026.3V1UF

PLACE_NEAR=U1800.AD21:2.54mm

CERM

10%

4026.3V1UF

CERM

10%

4026.3V1UF

CERM10%

4026.3V1UF

CERM

20%

22UF603X5R-CERM-16.3V

10%

4026.3V1UF

CERM10%

4026.3V1UF

CERM10%

4026.3V1UF

CERM

X5R6.3V10UF

PLACE_NEAR=U1800.AB36:2.54mm

10%

20%

22UF603X5R-CERM-16.3V

0.01UF20%

603

PLACE_NEAR=U1800.AM37:2.54mm

X5R-CERM-16.3V22UF

NO STUFF 0.1UH0805

1/20W05%

201MF

10%

PLACE_NEAR=U1800.U48:2.54mm

X7R-CERM0402

0.01UF10%

402

11/16W5%

X5R20%

6036.3V10UF

10%

X5R1UF

060310UH-0.12A-0.36OHM CRITICAL

10%

4026.3V1UF

220UF

10%

4026.3V1UF

NO STUFF

6.3V

PLACE_NEAR=U1800.BF47:2.54MM

CERM20%

B162.5V220UF CRITICAL

TANT

PLACE_NEAR=U1800.BF47:2.54MM

10UH-0.12A-0.36OHM0603CRITICAL

402

01/16W5%

4025%

MF-LF0

10UH-0.58A-0.35OHM CRITICAL

1098AS-SM

1/20W

PLACE_NEAR=U1800.AM37:2.54MM

05%

201MF

402MF-LF5%

PP1V05_S0_PCH_VCCADPLLB_F

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.075 MMVOLTAGE=3.3V

VOLTAGE=1.05VMIN_LINE_WIDTH=0.4 MMPP1V05_S0_PCH_VCCADPLLA_R

VOLTAGE=5VMIN_LINE_WIDTH=0.4 MMMAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3 MMVOLTAGE=5V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.075 MMVOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

PP3V3_S0_PCH_VCCA_DAC_F

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MMMIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MMPP1V05_S0_PCH_VCCCLKDMI_R

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.5 MM

R24052

1

C243812

C244012

C244112

C241912

C242112

C243412

C246912

C2414

1

2

C240112

C245212

C249912

C244212

C2486

1

2

C244412

C244612

C242412

C246012

C2430

1

2

C242812

C2406

1

2

C240012

R2451

C245312

C249112

24 OF 132

23 OF 99

52

Trang 24

IN

INININ

IN

OUT

ININ

IN

OUTOUT

OUT

INOUTIN

OUT

IN

OUTOUT

IN

OUTOUTOUTOUTOUT

ININININ

OUTOUT

IN

OUT

OUTOUT

IN

ININ

NC

ININ

OUTOUT

INOUT

BIIN

ININ

BIIN

REVISION

BRANCH

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page DBR#/HOOK7

VCC_OBS_CD

OBSDATA_D3 OBSDATA_D2

OBSDATA_D2

PWRGD/HOOK0

OBSFN_A1 OBSDATA_A0

OBSDATA_A2 OBSDATA_A3 OBSFN_A0

SDA

needs to split between route from PCH to J2550

and path to non-XDP signal destination.

(R2564-R2567)

- ’Output’ non-XDP signals require pulls.

OBSDATA_B2

998-2516

VCC_OBS_CD OBSDATA_B3

OBSDATA_B1

OBSDATA_A1 OBSFN_A1

OBSDATA_B0

doc id 404081

- For isolated GPIOs:

VCC_OBS_AB HOOK2 HOOK3

SCL TCK1

support chipset debug.

TRSTn TDI TDO

OBSFN_B0 OBSDATA_A1

OBSFN_D0 OBSFN_D1

OBSDATA_C1 OBSDATA_C2 OBSDATA_C3

TDI TMS

TDO TRSTn DBR#/HOOK7 ITPCLK#/HOOK5 OBSFN_D1

OBSFN_C1

OBSDATA_C3 OBSDATA_C0

1K series R on PCH Support Page

XDP_PRESENT#

TMS TCK0

OBSDATA_D3

TCK1 SCL

PWRGD/HOOK0 OBSDATA_B3

Use with 921-0133 Adapter Flex to NOTE: This is not the standard XDP pinout.

XDP SIGNALS

PCH/XDP Signal Isolation Notes:

it is functional in that state, else add BOM options

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path

Initially, stuffing both 33 and 0 ohms and validate whether

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

Use with 921-0133 Adapter Flex to support chipset debug.

OBSDATA_A3 OBSDATA_A2

PCH Micro2-XDP

PCH SIGNALS

XDP_PRESENT#

ITPCLK#/HOOK5 HOOK1

XDP

10%

0.1UF

16V 0402 X7R-CERM

1/20W

0XDP PLACE_NEAR=R1840.1:2.54mm

5%

PLACE_NEAR=U1000.G3:2.54mm

1KXDP

1/20W

51XDP PLACE_NEAR=J2550.52:2.54mm

1/20W

51XDP PLACE_NEAR=U1800.K5:2.54mm

1/20W

51XDP PLACE_NEAR=U1800.H7:2.54mm

1/20W

51XDP PLACE_NEAR=U1800.J3:2.54mm

1/20W

51XDP PLACE_NEAR=J2500.52:2.54mm

1/20W

51XDP PLACE_NEAR=U1000.K61:2.54mm

1/20W

51XDP PLACE_NEAR=U1000.J58:2.54mm

1/20W

330XDP

1/20W

1KXDPPLACE_NEAR=U1000.B57:2.54mm

1/20W

0XDPPLACE_NEAR=U4900.P17:2.54mm

1/20W

1KXDPPLACE_NEAR=U1000.C60:2.54mm

1/20W

0XDP_CPU:BPM

11

1/20W

0XDP_CPU:BPM

1/20W

0XDP_CPU:BPM

1/20W

0XDP_CPU:BPM

1/20W

0XDP_CPU:CFG

1/20W

0XDP_CPU:CFG

1/20W

0XDP_CPU:CFG

1/20W

33XDP

1/20W

33XDP

1/20W

33XDP

201 1/20W

33XDP

1/20W

33XDP

1/20W

33XDP

1/20W

33XDP

1/20W

33XDP

1/20W

33XDP

1/20W

33XDP

1/20W

0XDPPLACE_NEAR=U4900.P17:2.54mm

XDP_CONNDF40RC-60DP-0.4V

33XDP

1/20W 5%

33XDP

201 MF

1/20W

33XDP

1/20W 5%

201 1/20W 5%

1K

10%

0.1UF

16V 0402 X7R-CERM

ISOLATE_CPU_MEM_L

=PPVCCIO_S0_XDP

XDP_CPURST_LXDP_DBRESET_L

XDP_CPU_CLK100M_NXDP_CPU_CFG<0>

XDP_DC3_PCH_GPIO19_SATARDRVR_ENXDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_LXDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_CPU_TDIXDP_CPU_TRST_LXDP_CPU_TMS

USB_EXTA_OC_LUSB_EXTB_OC_LAP_PWR_EN

SATARDRVR_ENXDP_CPU_TDO

XDP_DC1_MXM_GOODXDP_DC2_DP_AUXCH_ISOLXDP_DC3_SATARDRVR_ENTP_XDP_PCH_OBSFN_D<0>

TP_XDP_PCH_OBSFN_D<1>

XDP_CPU_TCK

XDP_DA1_USB_EXTB_OC_L

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_LXDP_DA1_PCH_GPIO40_USB_EXTB_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA2_USB_EXTC_OC_L

XDP_DA1_USB_EXTB_OC_L

XDP_DA0_USB_EXTA_OC_L

TP_XDP_PCH_OBSFN_A<1>

XDP_DA0_USB_EXTA_OC_LXDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DD1_JTAG_ISP_TCK

XDPPCH_PLTRST_LXDP_DBRESET_LXDP_PCH_TDOTP_XDP_PCH_TRST_LXDP_PCH_TMS

XDP_PCH_TCK

XDP_PCH_TDIXDP_PCH_TMSXDP_PCH_TDO

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TMSXDP_CPU_TDIXDP_CPU_TDO

XDP_PCH_TDI

TP_XDP_PCH_HOOK4XDP_DD2_AUD_IPHS_SWITCH_EN

XDP_DC3_PCH_GPIO19_SATARDRVR_ENXDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC1_MXM_GOOD

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DB3_SDCONN_STATE_CHANGE

XDP_PCH_S5_PWRGDXDP_DB3_SDCONN_STATE_CHANGE

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TCK

TBT_CIO_PLUG_EVENT_ISOLXDP_FC1_PCH_GPIO0

C25011

2C25001

2

C25801

2

C25811

20 21 22 23 24 25 26 27 28 29 3

30 31 32 33 34 35 36 37 38 39 4

40 41 42 43 44 45 46 47 48 49 5

50 51 52 53 54 55 56 57 58 59 6

60

61 62

63 64

7 8 9

J2550

1

10 11 12 13 14 15 16 17 18 19 2

20 21 22 23 24 25 26 27 28 29 3

30 31 32 33 34 35 36 37 38 39 4

40 41 42 43 44 45 46 47 48 49 5

50 51 52 53 54 55 56 57 58 59 6

60

61 62

63 64

7 8 9

Trang 25

OUT

OUTIN

IN

OUT

OUTOUT

IN

OUT

OUTIN

IN

OUTOUT

25MHZ_C25MHZ_B25MHZ_A

X1X2VDD_RTC_OUTTHRMGND32KHZ_A

NCNC

08Y1 Y2 GND B2

VCC

A1 B1

OUTIN

ININ

IN

D

SG

D S

OUT

OUTOUT

OUT08

Y1 Y2 GND B2

VCC

A1 B1 A2IN

IN

Y B A

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

Ethernet XTAL Power (Unused on 15" MBP)

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

VDDIO_25M_B: Ethernet power rail for XTAL circuit.

GreenClk 25MHz Power

SB XTAL Power

TBT XTAL Power

LPC 33MHz Clock Series Termination

NOTE: 30 PPM crystal required

Coin-Cell & No G3Hot: 3.3V S5

No Coin-Cell: 3.42V G3Hot (no RC) System RTC Power Source & 32kHz / 25MHz Clock Generator

VTT pullup on CPU page

PCH ME Disable Strap PCH uses HDA_SDO as a power-up strap If low, ME functions normally.

GPIO Glitch Prevention

No bypass necessary

internally ORed to

SMC controls strap enable to allow in-field control of strap setting.

Platform Reset Connections

Series R on Pg38, R3803

Buffered

IPD = 9-50k

Unbuffered

Coin-Cell: VBAT (300-ohm & 10uF RC)

Buffered CPU reset

to reduce VBAT draw.

If high, ME is disabled This allows for full re-flashing of SPI ROM.

Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

11

89

5%

402MF-LF0 XDP

1/16W

5%

402MF-LF335%

402

331/16W

22

PLACE_NEAR=U1800.P53

PLACE_NEAR=U1800.N52

MF2011/20W225%

19

33 5%

402MF-LF01/16W

7 43 92

41 92

19

82 5%

1/20WMF20122

24 5%

402MF-LF1K XDP

1/16W

402CERM

0.1UF20%

SC70-HFMC74VHC1G08CRITICAL

5%

402

100K1/16W

17 92 5%

201MF1/20W

22

19

82 5%

402MF-LF0

5%

402MF-LF0 OMIT

6.3V1UF

X5R402-11UF402

CERM

0.1UF20%

NO STUFF

402CERM20%

402CERM0.1UF10V

5%

402

01/16W5%

12PF

0402C0G-CERM50V

5%

12PF

0402C0G-CERM50V

11 24

5%

402MF-LF100KSC70

CRITICAL 74LVC1G07

402CERM10V0.1UF

5%

402

01/16W

5%

4020

NO STUFF

5%

402

01/16W

41

5%

1K2011/20WMFSSM6N37FEAPE

SOT563

SSM6N37FEAPESOT563

5%

MF1/20W201100K

17 92

38

58

20 35 402

CERM0.1UF10V

0SOT665

TC7SZ08AFEAPE

CRITICAL

201 10%

5%

MF10K

2011/20W

5%

NO STUFF

1/20W 201

SSM6N15FEAPESOT563

5%

MF1/20W470K201

=PP3V3R1V5_S0_PCH_VCCSUSHDA

SPI_DESCRIPTOR_OVERRIDE_LS5V

HDA_SDOUT_R SPI_DESCRIPTOR_OVERRIDE

ENET_LOW_PWR FW_PWR_EN

=PP3V3_S3_PCH_GPIO

TBT_PWR_EN AUD_IPHS_SWITCH_EN_PCH

PCH_CLK33M_PCIIN TP_PCI_CLK33M_OUT2

TBT_PWR_EN_PCH

PM_PCH_PWROK LPC_PWRDWN_L

U2680

32145

C262012

C262212

R2606

1

2

C262412

R2605

C2605

12

43

R2630

R26311

Trang 26

BIBI

VDD33

SUSP_IND/LOCAL_PWR/NON_REM0SDA/SMBDATA/NON_REM1SCL/SMBCLK/CFG_SEL0HS_IND/CFG_SEL1

XTALIN/CLKINXTALOUT

TESTRESET*

NCNCUSBDP_DN3/PRT_DIS_P3USBDM_DN3/PRT_DIS_M3USBDP_DN2/PRT_DIS_P2USBDM_DN2/PRT_DIS_M2USBDP_DN1/PRT_DIS_P1USBDM_DN1/PRT_DIS_M1

BIBI

IN

VCC

GNDSELOE*

D+

D-Y+

M+

Y-

M-BIBI

BIBI

BI

BIBI

TABLE_BOMGROUP_HEAD

REVISION

BRANCH

PCH PORT 7 (EHCI1)

IPUIPUIPU

PCH PORT 1 (XHCI)

IPU

TO TP/KB

TO CONNECTOR

USB XHCI/EHCI2 PORT MUX FOR EXT B

SEL=0 CHOOSE USB EHCI2 PORTSEL=1 CHOOSE USB XHCI PORT

PCH GPIO60 PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

BOM TABLE

PCH PORT 9 (EHCI2)

TO CONNECT TP/KB TO PCH XHCI

TO PCH XHCI

NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB MUX FOR LS/FS INTERNAL DEVICES

1 : 1 PORT 1&2&3 ARE NON REMOVABLE

1 : 0 PORT 1&2 ARE NON REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLENON_REM 1 : NON_REM 0 STRAP PIN CFG

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

SMC DEBUG PORT FOR 15" MBP, IR for MBP OGTRACKPAD/KEYBOARD FOR 15" MBP & MBP OGBLUETOOTH FOR 15" MBP & MBP OG

NC FOR 15" MBP, SMC DEBUG PORT FOR MBP OG

15" MBP ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B MBP OG ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

15" MBP USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION

MBP OG USES 197S0284 FOR Y2700 TO SAVE COST

5%

402 1/16W10K

5%

402

CRITICAL

1/16W1M

4021UFX5R 0402

16V X7R-CERM0.1UF10%

4021UF16V 16V

X7R-CERM 0402

0.1UF10%

BYPASS=U2700.15::2MM

16V X7R-CERM 0402

0.1UF10%

5%

40210K

MF-LF

402 1/16W 1%

0.1UF10%

16V X7R-CERM 0402

0.1UF10%

BYPASS=U2700.5::2MM

16V X7R-CERM 0402

0.1UF10%

5%

402100

MF-LF

5%

18PF

0402 C0G-CERM 50V

CRITICAL

5%

18PF

0402 C0G-CERM 50V

CRITICAL

5%

40210K

MF-LF 5%

402 1/16W10K

5%

402 MF-LF

HUB_NONREM0_1

10K5%

OMIT

QFNUSB2513B

CKPLUS_WAIVE=NdifPr_badTerm

16V X7R-CERM 0402

0.1UF10%

16V X7R-CERM 0402

0.1UF10%

603 20%

6.3V4.7UF

603 20%

X5R 6.3V4.7UF

9 26

16V X7R-CERM 0402

0.1UF10%

MF-LF 5%

402 MF-LF10K1/16W

NOSTUFF

5%

402 1/16W10K

MF-LF

NOSTUFF

5%

402 1/16W10K

HUB_NONREM1_1,HUB_NONREM0_0 HUB_2NONREM

HUB_NONREM1_1,HUB_NONREM0_1 HUB_3NONREM

MIN_LINE_WIDTH=0.4MM VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8

=PP3V3_S3_USB_HUB

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM VOLTAGE=1.8V

USB_HUB_XTAL2

USBHUB_DN4_N

USBHUB_DN2_NUSBHUB_DN2_P

=PP3V3_S3_USB_HUB

USBHUB_DN4_P

USBHUB_DN3_PUSBHUB_DN3_N

USB_EXTB_SEL_XHCIUSB_EXTB_XHCI_N

USB_EXTB_N

USBHUB_DN1_NUSBHUB_DN1_PUSBHUB_DN2_NUSBHUB_DN2_PUSBHUB_DN3_NUSBHUB_DN3_P

USBHUB_DN4_P

NC_USB_HUB_OCS4

USB_HUB_VBUS_DETUSB_HUB_RBIAS

USB_HUB_UP_NNC_USB_HUB_PRTPWR4

USB_HUB_UP_P

USB_HUB_RESET_LUSB_HUB_TEST

USB_HUB_XTAL1

USB_HUB_CFG_SEL1USB_HUB_CFG_SEL0USB_HUB_NONREM1USB_HUB_NONREM0

USBHUB_DN4_N

NC_USB_HUB_OCS3NC_USB_HUB_OCS2TP_USB_HUB_OCS1

R27121

2

R2700

C27141

2

C27131

2C27121

2C27111

2

C27081 2

R27081

2

R27091

2

C27011 2

C27061 2C27051

2

R2701

C27101

2C27091

2

R27071

2

R27061

2

R27031

2R27021

2

R27051

2R27041

20

21

13 17 19

12 16 18

35

26

24 22 28 11

5 10 15 23 29 36

33 32

C27021

2

C27031

2C27001

2

C27041 2

C271512

R27161

2

R27171

2

R27181

2

R27191

2

C276012

U2760

67

45

21

2

R27231

2

051-9589 4.18.0

Trang 27

IN IN

INOUT

OUT

D

SG

D

S G

D

SG

D

S GD

SG

OUTIN

IN

D

SG

D

SG

IN

GD

4 5

7 8

REVISION

BRANCH

II NOT TO REPRODUCE OR COPY ITStep ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

Ensures CKE signals are held low in S3

transition Rails will power-up as if from S3, but MEM_RESET_L will not properly assert Software

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

75mA max load @ 0.75V

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

1V5 S0 "PGOOD" for CPU

402

9

10K

1/16W5%

CRITICAL CPUMEM_S0

CRITICAL

SOT563SSM6N15FEAPE CPUMEM_S0

SOT563CPUMEM_S0 CRITICAL

SSM6N15FEAPE

SOT563SSM6N15FEAPE CPUMEM_S0 CRITICAL

SOT563SSM6N15FEAPE CPUMEM_S0 CRITICAL CPUMEM_S0

SOT563SSM6N15FEAPE CRITICAL

CPUMEM_S0 SSM6N15FEAPESOT563CRITICAL

SSM6N15FEAPE CPUMEM_S0

SOT563

10K

1/16W5%

9

64

SOT563CPUMEM_S0 SSM6N15FEAPE CRITICAL

CPUMEM_S0 100K5%

1/16W402

NO STUFF

50V0.001UF20%

CERM402

SOT563

CRITICAL CPUMEM_S0 SSM6N15FEAPE

CPUMEM_S0 105%

MF-LF6031/10W

MF-LF5%

0 CPUMEM_S3

402

11

OMIT_TABLE

MF-LF1%

1/16W40233.2K

27.4K1%

1/16W402

DMB53D0UVSOT-563CRITICAL

5%

10KMF-LF402

CRITICAL

DMB53D0UVSOT-563

11 18 89

CPUMEM_S0

X7R-CERM040216V0.1UF10%

NOSTUFF

201

0.047UF6.3VX5R10%

MF-LF5%

1K402CPUMEM_S0

402

4700PF10%

100V

CPU Memory S3 Support

SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

114S0365 1 RES,MTL FILM,1/16W,33.2K,1,0402,SMD,LF R2821 PPDDR:1V5114S0376 1 RES,MTL FILM,1/16W,43.2K,1,0402,SMD,LF R2821 PPDDR:1V35

PM_MEM_PWRGD

=PP3V3_S5_CPU_VCCDDR PM_SLP_S4_L

Q2810 6

21

Q2810

3

54

R2816

1

2

C282012

051-9589 4.18.0

Trang 28

NCNCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

REVISION

BRANCH

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

20%

4022.2UF

X5R-CERM

20%

4022.2UF

10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3V10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

2011/20W

MF1/20W1%

240201

1%

201

2401/20WMF

CERM-X5R-14V

20%

201CERM-X5R-1

20%

4VCERM-X5R-1201201

4VCERM-X5R-120%

0.47UF 0.47UF

20%

4V201CERM-X5R-1

0.47UF201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

CERM-X5R-120%

4V201

0.47UF

0.47UF201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

20%

4VCERM-X5R-12010.47UF

CERM-X5R-1

0.47UF20%

4V20120%

CERM-X5R-14V2010.47UF 0.47UF

201CERM-X5R-14V20%

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF 0.47UF

201CERM-X5R-14V20%

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF

MF1/20W1%

240201240

2011%

1/20WMF

0.47UF201CERM-X5R-14V20%

4V2010.47UFCERM-X5R-120%

20%

CERM-X5R-14V201

0.47UFCERM-X5R-14V

20%

0.47UF

201

MF1/20W1%

240201MF

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

X5R10%

0.1UF201

6.3VX5R10%

0.1UF6.3V

X5R10%

0.1UF6.3V

20110%

X5R

0.1UF20%

4022.2UFX5R-CERM402

10V2.2UF

2.2UF40210V

X5R-CERM2.2UF40210V

2.2UF20%

402X5R-CERM

X5R-CERM2.2UF40210V

2.2UFX5R-CERM40210V

X5R-CERM

2.2UF20%

402

20%

X5R-CERM2.2UF40210V

X5R-CERM2.2UF40210VX5R-CERM

2.2UF20%

402

2.2UFX5R-CERM40210V2.2UF

10V402X5R-CERM

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

DDR3-1333 FBGA

DDR3 SDRAM Bank A (1 OF 2)

C29401

2

C294112

C2919

1

2

C291812

C291712

C2929

1

2

C292812

C292712

C2939

1

2

C293812

C293712

C2979

1

2

C297812

C297712

C2969

1

2

C296812

C296712

C2959

1

2

C295812

C2949

1

2

C294812

C29001

2

C291112

C295112

C291012

C295012

C292112

C296112

C292012

C296012

C293112

C293012

C297112

C297012

U2900

K4L8

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A3 A10 D8 G9 G3 K2 K10 M2 M10 B10 C2 E3 E10 E2 J9

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

J10 B3 D2 B9 C10 D10

H4

H9

051-9589 4.18.0

Trang 29

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

NCNCNC

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

NCNCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNC

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

NCNCNC

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

240

1%

MF2401/20W

MF1/20W1%

240201

201CERM-X5R-14V

20%

0.47UF

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V201

0.47UF

20%

2014VCERM-X5R-1

0.47UF20%

CERM-X5R-14V2010.47UF 0.47UF

201CERM-X5R-14V20%

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF 0.47UF

201CERM-X5R-14V20%

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF 0.47UF

201CERM-X5R-14V20%

0.47UF201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

20%

4VCERM-X5R-1201

0.47UF 0.47UF

201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

CERM-X5R-1201

0.47UF20%

4V0.47UF

2014V20%

CERM-X5R-1201

4VCERM-X5R-1

0.47UF20%

201

2401%

1/20WMFMF

1/20W1%

240201

20%

4V2010.47UFCERM-X5R-10.47UF

201CERM-X5R-14V20%

0.47UF2014V20%

CERM-X5R-120%

4VCERM-X5R-1

2010.47UF

201

2401%

1/20WMFMF

X5R-CERM10V

40210V2.2UF

X5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

2.2UF40210VX5R-CERM

X5R-CERM

2.2UF20%

402

X5R-CERM40210V2.2UF

X5R-CERM2.2UF40210V

X5R-CERM2.2UF40210VX5R-CERM2.2UF40210V

X5R-CERM

2.2UF20%

2.2UF40210V

2.2UFX5R-CERM40210VX5R-CERM2.2UF40210V

X5R-CERM

2.2UF20%

2.2UF40210V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

6.3VX5R10%

10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

0.1UF10%

2016.3V

10%

2016.3V0.1UF

10%

2016.3V0.1UF

DDR3-1333 FBGA

OMIT_TABLE

DDR3-1333 FBGA

FBGA DDR3-1333

OMIT_TABLE

DDR3 SDRAM Bank A (2 OF 2)

=PP1V5R1V35_S3_MEM_A

MEM_A_ZQ<13>

MEM_A_WE_L MEM_A_BA<0>

MEM_A_CLK_N<1> MEM_A_A<0>

C3019

1

2

C301812

C301712

C3029

1

2

C302812

C302712

C3039

1

2

C303812

C303712

C3079

1

2

C307812

C307712

C3069

1

2

C306812

C306712

C3059

1

2

C305812

C3049

1

2

C304812

C300112

C305012

C301012

C305112

C301112

C306012

C306112

C302012

C302112

C307012

C307112

C303012

C303112

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

J10 B3 D2 B9 C10 D10

H4

H9

051-9589 4.18.0

Trang 30

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

NCNCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNC

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

REVISION

BRANCH

OMIT_TABLE

DDR3-1333 FBGA

OMIT_TABLE

DDR3-1333 FBGA

1/20W

2402011%

MF2402011%

1/20W

CERM-X5R-1

20%

4V201

0.47UF

0.47UFCERM-X5R-12014V20%

0.47UF2014VCERM-X5R-1

201CERM-X5R-14V20%

CERM-X5R-10.47UF2014V20%

20%

4V201CERM-X5R-10.47UF

0.47UF201CERM-X5R-14V20%

0.47UF4VCERM-X5R-120%

201

0.47UF20%

4VCERM-X5R-1201

0.47UF201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

20%

0.47UF201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

20%

4VCERM-X5R-1201

0.47UF 0.47UF

201CERM-X5R-14V20%

CERM-X5R-10.47UF2014V20%

20%

4VCERM-X5R-1201

0.47UF 0.47UF

201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

201

2401%

1/20WMF201

MF2401/20W1%

CERM-X5R-120%

4V201

0.47UF 0.47UF

201CERM-X5R-14V20%

0.47UF2014VCERM-X5R-120%

CERM-X5R-1

0.47UF

4V20%

201

2401%

1/20WMFMF

4022.2UFX5R-CERM

X5R-CERM2.2UF40210V

40210V2.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

40210V2.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

402X5R-CERM2.2UF

40220%

X5R-CERM10V

2.2UF

20%

4022.2UFX5R-CERM

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

0.1UF10%

201

X5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF6.3VX5R10%

DDR3-1333 FBGA

OMIT_TABLE

DDR3-1333 FBGA

OMIT_TABLE

DDR3-1333 FBGA

OMIT_TABLE

DDR3-1333 FBGA

OMIT_TABLE

DDR3-1333 FBGA

MEM_B_ZQ<7>

MEM_B_WE_L MEM_B_ODT<0>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_RAS_L

C3119

1

2

C311812

C311712

C3129

1

2

C312812

C312712

C3139

1

2

C313812

C313712

C3179

1

2

C317812

C317712

C3169

1

2

C316812

C316712

C3159

1

2

C315812

C3149

1

2

C314812

C315012

C310112

C311012

C315112

C311112

C316012

C316112

C312012

C312112

C317012

C317112

C313012

C313112

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

J10 B3 D2 B9 C10 D10

H4

H9

051-9589 4.18.0

Trang 31

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

NCNCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNC

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5

A1

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

VSSQ

NF/DQ5NF/DQ4

CS*

CKENF/TDQS*

DM/TDQSDQS*

RESET*

A9A8

A6A7A5A1 VREFCA

VDDQVDD

A0

A11A10/AP

A4A3

A14

NF/DQ6NF/DQ7

DQ3DQ2DQ1DQ0

4 5

7 8

REVISION

BRANCH

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

DDR3-1333 FBGA

1/20W

1%

201240

0.47UF

4V20120%

CERM-X5R-14V0.47UF20120%

4V201CERM-X5R-1

0.47UF

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF 0.47UF

4V20%

201

CERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF201

CERM-X5R-14V20%

0.47UF

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V2010.47UF 0.47UF

201CERM-X5R-14V20%

20%

4VCERM-X5R-12010.47UFCERM-X5R-1

20%

4V2010.47UF 0.47UF

201CERM-X5R-14V20%

20%

4VCERM-X5R-1201

0.47UF20%

CERM-X5R-14V201

0.47UF4V

CERM-X5R-120120%

0.47UF20%

4V201CERM-X5R-1

0.47UF20%

4V0.47UFCERM-X5R-1201

MF1/20W1%

240201201

2401%

1/20WMF

0.47UF201CERM-X5R-14V20%

20%

4V2010.47UFCERM-X5R-1201

CERM-X5R-14V20%

0.47UF201

CERM-X5R-14V

20%

0.47UF

MF1/20W1%

201240201

402X5R-CERM

2.2UF

20%

X5R-CERM2.2UF402

4022.2UFX5R-CERM

X5R-CERM2.2UF40210V

40210V2.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

40210V2.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

20%

4022.2UFX5R-CERM

40220%

X5R-CERM10V

2.2UF

20%

4022.2UFX5R-CERM

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

0.1UF10%

201

X5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF

6.3VX5R10%

0.1UF6.3VX5R10%

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

OMIT_TABLE

FBGA DDR3-1333

C3219

1

2

C321812

C321712

C3229

1

2

C322812

C322712

C3239

1

2

C323812

C323712

C3279

1

2

C327812

C327712

C3269

1

2

C326812

C326712

C3259

1

2

C325812

C3249

1

2

C324812

C325012

C320112

C321012

C325112

C321112

C326012

C326112

C322012

C322112

C327012

C327112

C323012

C323112

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4

G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

H8M8K8N4N8J8

L4K3L9L3M9M3N9M4

J3K9J4G4

F8G8G10H3B8

B4C8C3C9

C4D4

A1A4A11F2F10

H2H10

N1

N11

E4E9D3E8

A8

G2F4

N3

A2 B2

L10 N10J2 L2 N2 F3 A9 D9 F9

J10 B3 D2 B9 C10 D10

H4

H9

051-9589 4.18.0

Trang 32

IN

INININ

ININ

IN

ININININ

IN

ININININININININININININININ

REVISION

BRANCH

MEM Clock Termination Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

12

31

1/32W 4X02015%

36

4X02011/32W36

5%

1/32W 4X02015%

36

4X02015%

36

1/32W

36

5% 1/32W 4X02014X02011/32W36

5%

4X02011/32W36

5%

0.47UF201CERM-X5R-14V20%

20%

5% 1/32W 4X020136

20%

CERM-X5R-10.47UF2014V

4VCERM-X5R-10.47UF20120%

0.47UF201CERM-X5R-14V20%

PLACE_NEAR=U3270.F7:3.2mm

3.3PF201CERM25V5%

301/20WMF5%

201

3.3PF201CERM25V5%

1/32W36

4X02015%

301/20WMF5%

201

2015%

MF1/20W30

301/20WMF5%

201

10%

6.3VX5R0.1UF

10%

6.3VX5R0.1UF

10%

6.3VX5R0.1UF

10%

6.3VX5R0.1UF

301/20WMF5%

201

5% 1/32W 4X020136

2015%

MF1/20W30

2013.3PFCERM25V5%

30

2015%

MF1/20W

301/20WMF5%

201

PLACE_NEAR=U3170.F7:3.2mm3.3PF

CERM20125V5%

12

31

36

4X02015% 1/32W

0.47UF201CERM-X5R-14V20%

12

31

36

4X02011/32W5%

36

12

29

1/32W5%

5% 1/32W 4X020136

36

4X02015%

12

31

4X02011/32W36

5%

4X02011/32W36

5%

36

1/32W 4X02014X02011/32W36

5%

4X02011/32W5%

36

5%

36

4X02011/32W

1/32W 4X02015%

36

4X02015% 1/32W36

5% 1/32W 4X020136

20%

0.47UF2014V20%

CERM-X5R-1

2014V20%

0.47UFCERM-X5R-1

5% 1/32W 4X0201

36 36

5% 1/32W 4X02011/32W5%

36

4X02011/32W

36

1/32W 4X02015%

36

1/32W 4X02015%

36

1/32W 4X020136

5%

0.47UF201CERM-X5R-14V20%

36

1/32W 4X02015%

36

4X020136

5% 1/32W 4X0201

36

4X02015% 1/32W36

4X02011/32W5%

R3366

C335512

33 OF 132

32 OF 99

8

Trang 33

V+

SCLSDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPAD

NC

INBI

VDD

VOUTDVOUTCVOUTBVOUTASCL

SDAA0A1GND

INBI

Apple Inc.

1 2

4 5

7 8

REVISION

BRANCH

QTY

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable

Addr=0x30(WR)/0x31(RD)

- =PPDDR_S3_MEMVREF

8.59mV / step @ output MEM B VREF CA

watchdog will disable margining.

3 C

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

0.300V - 1.200V (+/- 450mV)

C

0.000V - 1.501V (0x00 - 0x74)

5 D MEM VREG

+61uA - -61uA (- = sourced)

1.000V - 2.000V (+/- 500mV) 0.000V - 3.000V (0x00 - 0x74)

6 D

10mA max load

DDRVREF_DAC - Stuffs Apple margining circuit

VREFDQ:LDO - LDO outputs sent to DQ inputs

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs

VREFCA:LDO - LDO outputs sent to CA inputs

BOM options provided by this page:

Required zero ohm resistors when no VREF margining circuit stuffed

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs

+3.4mA - -3.4mA (- = sourced)

DDR3 (1.5V) 7.70mV per step NOTE: CPU DAC output step sizes:

soft-resets and sleep/wake cycles.

NOTE: Margining will be disabled across all RST* on ’platform reset’ so that systemVREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs

Power aliases required by this page:

DDRVREF_DAC

402 MF-LF

PLACE_NEAR=R7320.2:1mm

DDRVREF_DAC

1/16W 1%

33.2K

402

100K

MF-LF 5%

1/16W

DDRVREF_DAC

DDRVREF_DACCRITICAL

UCSP

MAX4253

UCSP

MAX4253DDRVREF_DACCRITICAL

CRITICAL

UCSP

MAX4253DDRVREF_DAC

CRITICALMAX4253

UCSP

DDRVREF_DAC

CRITICALMAX4253

UCSP

DDRVREF_DAC

MAX4253CRITICAL

UCSP

DDRVREF_DAC

402 1%

1/16W

PLACE_NEAR=J2900.126:2.54mmVREFCA:LDO_DAC

200

402 1/16W

200

1%

MF-LF

PLACE_NEAR=J3100.126:2.54mmVREFCA:LDO_DAC

402

OMIT

NONE NONE

SHORT

402

OMIT

NONE NONE

1/16W

133VREFDQ:LDO_DAC

402

VREFDQ:LDO_DAC

200 PLACE_NEAR=J3100.1:2.54mm

MF-LF 1%

1/16W

402 1%

133

VREFDQ:LDO_DAC

402 1/16W 5%

MF-LF

0DDRVREF_DAC

402

DDRVREF_DAC0

MF-LF 5%

1/16W

10%

0.1UF

16V 0402 X7R-CERM

VREFDQ:M1_M3PLACE_NEAR=Q3420.3:2mmVREFDQ:M1_M3

VREFDQ:M1_M3PLACE_NEAR=Q3420.6:2mmVREFDQ:M1_M3

1KVREFDQ:M1_M3

402

PLACE_NEAR=R3441.2:1mm 1%1/16W

1KVREFDQ:M1_M3

1KVREFDQ:M1_M3PLACE_NEAR=Q3420.3:1mm

MF-LF

402

100K

MF-LF 5%

1/16W

VREFCA:LDO_DAC

402 MF-LF 5%

0.1UF

402 20%

CERM

DDRVREF_DAC

402 1/16W 1%

133PLACE_NEAR=R3411.2:1mmVREFCA:LDO_DAC

402

100K

1/16W 5%

44

0.1UF

402 CERM 20%

DDRVREF_DAC

6.3V 20%

2.2UF

CERM 402-LF

0.1UF

402 20%

CERM 10V

SYNC_MASTER=D2_KEPLER

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_B

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_VREFMRGN_DAC

VOLTAGE=0.75V MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VOLTAGE=0.75V MIN_LINE_WIDTH=0.3 mm

=PPVTT_S3_DDR_BUF

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_ENVREFMRGN_DQ_SODIMMB_EN

VREFMRGN_FRAMEBUF_BUF

U3401

3 4 5

6 7 9 10 11 12 13 14 15

1 2

2

R34011

2

R3410

R34071

8

1 2 4

5

C34011

2C34001

2

R34151

2

R34161

2C3440

1

2Q3420

C34201

2Q3420

R34221

2

R34421

2

R34211

2

R34411

2

051-9589 4.18.0

Trang 34

INBI

OUTENMR*

GNDTHRMIN

REVISION

BRANCH

20 mOhm Max

1 A (EDP) P-TYPE3V S3 WLAN FET

RDS(ON) @ 2.5V MOSFET

LOADING CHANNEL

Supervisor & CLKFREG # Isolation Delay = 130 ms +/- 20%

PLACE_NEAR=J3502.6:2.54MM

FERR-120-OHM-1.5A

0402-LF

0.1uF20%

CERM 402

402

MF-LF 5%

FERR-120-OHM-3A0603

0.1uF

20%

CERM 402

0.1uF

10V CERM 402 20%

10%

0.1UF

0402 X7R-CERM 16V

90-OHM-100MA DLP11S

CRITICAL

PLACE_NEAR=J3501.27:2.54MMFERR-120-OHM-1.5A0402-LF

BTPWR:S3

7 18

10%

X7R-CERM 0402

232K1%

MF-LF 402

100K

1%

1/16W 402

402

100K

1/16W 1%

OMIT_TABLE

0.6NH+/-0.1NH-0.85A0201

10%

0.1UF

16V X5R-CERM

NOSTUFF

0201

OMIT_TABLE

02010.6NH+/-0.1NH-0.85A

10%

0.1UF

16V 0201 X5R-CERM

0.6NH+/-0.1NH-0.85A0201

10%

0.1UF

0201 X5R-CERM

17 92

514S0335

SSD-K99F-RT-SM1

CRITICAL

34 99

CRITICAL

DMP2018LFK DFN2563-6

10%

X5R6.3V2010.1UF

MF1/20W5%

0

201

BTPWR:S4

1/20WMF

15K1%

201

BTPWR:S4

1/20W1%

MF20115K

NOSTUFF

201MF1%

15K1/20W

0402-LFFERR-120-OHM-1.5A

BTPWR:S4

NOSTUFF

201MF1%

1/20W15K

1%

MF201

15K1/20W

NOSTUFFNOSTUFF

2011%

15K1/20WMF

201MF1/20W5%

AP_CLKREQ_LAP_PWR_ENAP_RESET_L

PP3V3_WLAN_R

VOLTAGE=3.3V MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm

PP5V_S3_ALSCAMERA_F

VOLTAGE=5V MIN_NECK_WIDTH=0.2 mm

PCIE_AP_D2R_PI_PPCIE_AP_D2R_PI_N

=I2C_ALS_SCLUSB_CAMERA_CONN_N

PCIE_AP_R2D_PI_P

P3V3WLAN_SS

USB_BT_PUSB_BT_NPCIE_CLK100M_AP_P

USB_BT_CONN_PUSB_BT_CONN_N

BTMUX_SEL

PP3V3_WLAN

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

USB_BT_WAKE_N

L35081 2

C35521

2L3507

2 1

C35221 2

L350612

C35321

2

R35541

2

R35551

2

R35531

2

C35701

2

L3570

C35711

2

C35731

2

L3571

C35721

2

C35751

2

L3573

C35741

2

C35771

2

L3574

C35761

2

J3501

192021

1

101112

131415161718

23456789

Q3550

4

3

12

U3510

67

45

810

21

C351112

2

051-9589 4.18.0

Trang 35

PETN_2PETP_2

PETP_1PETN_1

PETP_0PETN_0

MONOBS_N

MONDC0MONDC1

PERN_3PERP_3

PERN_2PERP_2

PERN_1PERP_1

PERP_0PERN_0

MONOBS_P

TMU_CLK_INTMU_CLK_OUT

DPSRC_3_P

DPSRC_2_PDPSRC_3_N

DPSRC_1_PDPSRC_2_N

DPSRC_1_NDPSRC_0_PDPSRC_AUX_PDPSRC_0_N

DPSRC_HPD_ODDPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_ODGPIO_6/CIO_SDA_ODGPIO_5/CIO_PLUG_EVENTGPIO_4/WAKE_N_ODGPIO_3

PB_CIO3_TX_N/DP_SRC_2_NPB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_NPB_CONFIG1/CIO_2_LSEOPB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_PPB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_NPB_DPSRC_1_NPB_DPSRC_1_PPB_LSRX/CIO_3_LSOE

PB_CIO3_RX_NPB_LSTX/CIO_3_LSEOPB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1GPIO_13/PB_DP_PWRDN/BYP2GPIO_1/PB_HV_EN/BYP0PB_DPSRC_HPDPB_AUX_NPB_AUX_P

THERMDAEE_DIEE_DOEE_CS_N

TDIEE_CLK

TDO

DPSNK0_2_PDPSNK0_3_N

DPSNK0_AUX_PDPSNK0_0_N

DPSNK0_HPDDPSNK0_AUX_N

DPSNK1_3_NDPSNK1_3_P

DPSNK1_AUX_NDPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_NPA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_NPA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOEPA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_NPA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_NPA_CIO1_RX_P

PA_LSRX/CIO_1_LSOEPA_LSTX/CIO_1_LSEO

PA_DPSRC_1_NPA_DPSRC_1_P

PA_DPSRC_3_NPA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPDPA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1GPIO_0/PA_HV_EN/BYP0GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_PREFCLK_100_IN_NXTAL_25_INXTAL_25_OUT

TMSTCKTEST_ENTEST_PWR_GOODDPSNK0_3_P

PWR_ON_POC_RSTNPERST_N

NCRBIAS

PCIE_RST_0_NPCIE_RST_1_NPCIE_RST_3_NPCIE_RST_2_N

PCIE_CLKREQ_OD_NEN_LC_PWR

OUTOUTOUTINBIBIOUTOUT

OUTOUT

INOUTININOUTOUTINOUTININ

OUTOUT

OUTOUTOUTINBIBIOUTOUTOUTOUTINOUTININOUTOUTINOUTININOUTOUT

ININ

OE GND VCC

OUTOUT

DC

OUT

OUTIN

BIOUTIN

OUTBI

4 5

7 8

REVISION

BRANCH

II NOT TO REPRODUCE OR COPY ITFor unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k) All other port signals can be NC.

Not used in host mode

(TBT_EN_CIO_PWR_L)

DEBUG: For monitoring clock

CR HPD INPUTS (S4) FORWARDED TO GMUX (S0) SNK0 AC Coupling

0

5%

1/20W 5%

100K

MF 201

1/20W100K5%

MF 201

MF 5%

201 1/20W100K

201 1/20W MF

0

5%

MF 201

X5R-CERM 10%

0201

X5R-CERM0.1UF 10% 16V02010.1UF X5R-CERM16V10%

0201

1/20W MF 1%

1K

201

0.1UF X5R-CERM020110% 16V

10% 16V X5R-CERM

X5R-CERM 10%

0.1UF X5R-CERM16V10%

0201

0.1UF X5R-CERM16V10%

0201

X5R-CERM 10%

X5R-CERM0.1UF 10% 16V0201

MF 1/20W 201

1/20W8061%

MF 201

1K

5%

1/20W 201

10K

5%

1/20W MF

5%

MF 2011K

1/20WNOSTUFF

35

SOT833

74LVC2G126GT/S500NOSTUFF

SOT833

74LVC2G126GT/S500NOSTUFF

100K

5%

1/20W MF 201

82

100K

5%

201 1/20W MF

82

OMIT_TABLE

M95256-RMC6XGMLP

201

47K5%

1/20WMF

0201NONENOSTUFF OMIT

10K201

0201 16V X5R-CERM

201MF1/20W5%

10K

201MF1/20W5%

10K

201MF1/20W5%

10K

MF201

10K5%

1/20W

10K2015%

MF1/20W

201

10K5%

1/20WMF

NO STUFF

201

100K5%

1/20WMF

20

X5R-CERM0201 16V 10%

0.1UF

20

MF1/20W5%

0201

0201 16V X5R-CERM

3.3K

1/20W 201 MF 5%

0201 16V X5R-CERM

10%

0201 16V X5R-CERM 10%

0.1UF

16V X5R-CERM 0201 10%

0.1UF

0.1UF 10% 16V X5R-CERM 0201

0.1UF 10% 16V X5R-CERM0201

201 MF 5%

MAKE_BASE=TRUETBT_EN_CIO_PWR_L

NO_TEST=TRUEPCIE_TBT_R2D_N<1>

NO_TEST=TRUE

PCIE_TBT_R2D_P<3>

NO_TEST=TRUE

NO_TEST=TRUEPCIE_TBT_R2D_P<0>

NO_TEST=TRUEPCIE_TBT_D2R_C_N<1>

NO_TEST=TRUEPCIE_TBT_D2R_C_P<1>

PCIE_TBT_R2D_P<2>

NO_TEST=TRUE

TBT_A_R2D_C_N<0>

TP_DP_TBTSRC_ML_CP<1>

=PP3V3_S0_DPMUX_UCDP_TBTSNK0_ML_C_P<0>

=PP3V3_S4_TBT

TBT_B_DP_PWRDN TBT_A_DP_PWRDN

TBTROM_HOLD_L

TBT_TEST_PWR_GOODTP_TBT_THERM_DP

TBT_PCIE_RESET_L

TP_TBT_MONDC0TP_TBT_MONDC1

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK0_AUXCH_PDP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_AUXCH_NDP_TBTSNK0_ML_N<1>

DP_TBTPA_ML_C_N<1>

TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC

TBT_A_LSTX TBT_A_LSRX DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_HPD TBT_A_HV_EN TBT_A_CIO_SEL

TBT_B_LSRX TBT_B_LSTX

TBT_B_DP_PWRDN

TBT_B_CONFIG1_BUF

DP_TBTSNK0_AUXCH_PDP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_P<2>

TBT_B_HV_EN

=PP3V3_S4_TBT

TBT_MONOBSPTBT_MONOBSN

DP_TBTPA_HPD_BUF

DP_TBTPA_HPD_BUF_ENDP_TBTPA_HPD

=PP3V3_S0_DPMUX_UC

DP_TBTPB_HPD_BUF

DP_TBTPB_HPD_BUF_ENDP_TBTPB_HPD

SYSCLK_CLK25M_TBT_R

DP_TBTSNK0_ML_P<3>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_AUXCH_CPTP_DP_TBTSRC_ML_CN<2>

DP_TBTSRC_HPD

TBT_TMU_CLK_OUTTBT_TMU_CLK_IN

TBT_RBIAS

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<3>

DP_TBTPB_HPD DP_TBTPB_AUXCH_C_P DP_TBTPB_ML_C_N<3>

TP_DP_TBTSRC_AUXCH_CNTP_DP_TBTSRC_ML_CN<0>

2

R36931

B5 A6

U6

D11 E12 D9 E10 D7 E8 D5 E6

B3 A4

T5

B9 A8 B11 A10 B13 A12 B15 A14

D3 C2

V3

W4 AD3 R4 P5

M1

Y1 W2 J4 AA2 AB1 AC2 P3 M5

AD23 AC24

W16 W18

F1 F3

E22 G22 E24 G24

J22 L22 J24 L24

K1 G4

B17 A16

B19 A18

H1

J6 N2

E2 D1

N22 R22 N24 R24

U22 W22 U24 W24

P1 H5

B21 A20

B23 A22

K3

G6 L6

W6

N6 T1 Y5 U2

AA6 V1

R2 N4 AB5

Y7

AB3

Y3 AA4

AA24 AB23

R36981

R36961

2R36991

86

U3610

5

47

83

7

2

1

98

43

C361012

Trang 36

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSS

VSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSSVSSVSS

VCC1P0_DPAUXVCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PE

VCC1P0VCC1P0

VCC3P3_DPVCC3P3_DPVCC3P3_DPVCC3P3_CIOVCC3P3_CIOVCC3P3_CIOVCC3P3VCC3P3VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0_ON

VCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ON

VCC3P3

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VCC3P3_DPVCC3P3_DPAUX

REVISION

BRANCH

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10UF

CERM-X5R 0402-1 6.3V 20%

10V X5R-CERM 0201-1

1.0UF

X5R-CERM 0201-1

1.0UF

0

402MF-LF5%

10V X5R-CERM 0201-1

1.0UF

20%

10UF

0402-1 CERM-X5R

10UF

CERM-X5R 0402-1

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

CACTUSRIDGE4C

CRITICALOMIT_TABLE

FCBGA

CERM-X5R 0402-1

10UF

6.3V 20%

0201-1 X5R-CERM 10V

1.0UF

20%

1.0UF

X5R-CERM 0201-1 10V

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

10V X5R-CERM 0201-1

1.0UF

20%

0201-1 10V X5R-CERM

1.0UF

20%

Thunderbolt Host (2 of 2)

PP3V3_S4_TBT

C37141

2

C37151

2

C37161

2

C37101

2

C37111

2

C37121

2

C37171

2

C37131

2C37001

R10 R14 T11 U10 V11 W10

L10 L14 M11 M15 N10 N14 P11 P15

G8 H9

J10 J12 J14 J16 J8 K17 T15 U14 V7 W8 G10 G12

V15 V19 W12 W14

G14 G16 G18 H19 K19 M19 P19 T19

M7 P7 T7

L18 N18 R18

H11 H13 H15 H17 H7

K7

AD1 K13

N16 N8 P13 P17 P9 R12 R16 R8 T13 T17 K9

T9 U12 U16 U8 V9

L12 L16 L8 M13 M17 M9 N12

A2 A24

AC12 AC14 AC16 AC18 AC20 AC22 AC4 AC6 AC8 B1 AA14

B7 C10 C12 C14 C16 C18 C20

C22 C24 C4

AA20

C6 C8 D21 D23 E4 F11 F13 F15 F17 F19

AA22

F21 F23 F5 F7 F9 G20 H21 H23 J18 J20

AA8

K21 K23 L20 M21 M23 N20 P21 P23 R20 T21 AB11

T23 U18 V13 V17 V21 V23 Y11 Y13 Y15 Y17 AB17

Y19 Y21 Y23 Y9

AB7 AC10

C37601

2C37721

2C37711

2C37701

2C37421

2C37411

2C37401

2

C37451

2

C37051

2

C37731

2C37741

2

R3790

051-9589 4.18.0

Trang 37

GND THRM

IN

VDD

SENSE+

PAD

(OD)

0.7VDLY

ININ

SG

GNDVOUTONVIN

VOUT

GNDONVIN

4 5

7 8

REVISION

BRANCH

TPS22924CPart

Intel investigating whether RC is sufficient.

Pull-ups provided by SB page

BOM options provided by this page:

- =PP1V05_TBTLC_FET (1.05V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

TBTBST:Y - Stuffs 15V boost circuitry

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

Max Current = 2A? Vout = 15.47V

- =PP3V3_TBTLC_FET (3.3V FET Output)

Vds(max): -30V

TPS22920

11.5 mOhm Max Load Switch Part

Type

28.6 mOhm Max TPS22924C

@ 1.0V Type

8-13V Input

<R2>

Vgs(max): +/-12V SI8409DB:

RC guarantees minimum 5ms to reach 0.5V

UVLO = 4.55V (falling), 4.95 (rising)

- =PP15V_TBT_REG (15V Boost Output)

Rds(on): 46mOhm @ 4.5V Vgs

Thunderbolt 15V Boost Regulator

Platform (PCIe) Reset

Max Vgs: 10V

1.05V TBT "LC" Switch

24 mOhm MaxLoad Switch

0.1UF

16V 0201

25

35

1UF6.3V 20%

0201 X5R

20%

0201 X5R1UF6.3V

SLG4AP016VTDFN

CRITICAL

5%

MF100K1/20W 201

35

402MF-LF1%

1/16W73.2K TBTBST:Y

MF-LF

40210V2.2UF TBTBST:Y

20%

40220%

TBTBST:Y 2.2UFX5R-CERM

5%

68PF0402COG-CERM50VTBTBST:Y

4022.2UF TBTBST:Y

X5R-CERM10V

5%

4021/16W330KMF-LFTBTBST:Y

SOT563

SSM6N37FEAPE TBTBST:Y

5%

4021/16W330K TBTBST:Y

402

28.7K1%

1/16WTBTBST:Y

MF-LF

49.9K4021/16W1%

TBTBST:Y

402TBTBST:Y

MF-LF

200K1%

1/16W

CRITICAL TBTBST:Y

QFN

LT3957

TBTBST:Y

X5R-CERM0603

10UF20%

TBTBST:Y

10UF20%

X5R-CERM060325V

41 42 70

5%

CERM50V402

NO STUFF 100PF

5%

50V10PF0402C0G-CERMTBTBST:Y

4021/16W

TBTBST:Y 15.8K

1%

MF-LF

402

TBTBST:Y 137K

MF-LF1%

0

TBTBST:Y

PWRDI5CRITICAL

TBTBST:Y

33UF-0.06OHM

POLY-TANTCASE-D3L20%

TBTBST:Y 10UFX5R1206-225V

805

NO STUFF 10UFX5R10%

50VTBTBST:Y

X7R-CERM0402

0.001UF10%

402TBTBST:Y

CERM-X5R6.3V0.33UF10%

TBTBST:Y CRITICAL

SI8409DBBGA

SSM6N37FEAPE

SOT563

TBTBST:Y TBTBST:Y

1UF20%

50VX7R-CERM0402

0.0033UF10%

SOT563SSM6N37FEAPE

5%

100KMF1/20W201

5%

1/20WMF100K201

20

35 10%

1UF6.3V402CERM

NOSTUFF

SOD-VESM-HFSSM3K15FV

35

5%

1/20W MF

10K

201

3.3UH-6.5A

CRITICAL TBTBST:Y

PIMB063T-SM

16VX7R-CERM0201

330PF10%

10%

1UF6.3V402

TBT_A_HV_EN TBT_B_HV_EN

MIN_LINE_WIDTH=0.5 mmPPVIN_SW_TBTBST

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mm

TBTBST_BOOST

DIDT=TRUEMIN_LINE_WIDTH=0.5 mm

=PP3V3_S0_P3V3TBTFET

TBTBST_VC TBTBST_INTVCC TBTBST_EN_UVLO

=PP3V3_S0_TBTPWRCTL

TBT_EN_LC_3V3

TBT_EN_LC_1V05TBT_EN_LC_ISOL

A1 B1

C38001

2

C38101 2

C38151 2

U3800

6

7 3

8

4 2

C3891 12

C3887

1

2

C3892 12

63

C3860 12

C3861 12

A1B1

C3831

12

C383012

U3820

D2

A2B2C2

A1B1C1

Trang 38

BIBI

ININ

OUTOUT

ININ

OUTOUT

ININ

TPTP

TP

OUTOUTINOUTIN

INININ

OUTBI

TPTP

REVISION

BRANCH

518S0829

516S0853

USB3_EXTB_RX_PUSB3_EXTB_TX_N

USB3_EXTB_RX_N

SD_PWR_EN

USB3_EXTB_RX_RC_P

HDMI_EG_DDC_CLK HDMI_HPD_L HDMI_EG_DDC_DATA PM_SLP_S4_L PM_SLP_S3_L

=PP5V_S4_RIO

SDCONN_STATE_CHANGE_RIO ENET_CLKREQ_L

PCIE_ENET_R2D_C_NPCIE_ENET_R2D_C_P

PCIE_CLK100M_ENET_NPCIE_ENET_D2R_PPCIE_ENET_D2R_NPCIE_CLK100M_ENET_PHDMI_EG_DATA_C_P<2>

15PF25V

SIGNAL_MODEL=EMPTY

SM BEAD-PROBE

GND_VOID=TRUEGND_VOID=TRUE

20525-130E-01

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

F-RT-SM

10%

0201 X5R-CERM

16V 0201 X5R-CERM

20 21 22 23 24 25 26 27 28 29 3

30 31

32

33 34 35 36 37 38 39 4

40 41

5 6 7 8 9

Trang 39

SELXSD

B0_PB1_PB0_N

B1_NC0_P

C1_PC0_NC1_N

OUTOUT

IN

ININ

OUT

OUTOUT

ININ

4 5

7 8

REVISION

BRANCH

Per PCIe spec, only TX side should have AC cap

0.1UF10V CERM 402 20%

06120.005

0.1UF

PLACE_NEAR=U4510.6:2 mm

16V X7R-CERM 0402

0.01UF20%

VQFN CBTL02043ABQ

0MF1/20W

0.01UF

10% 25V X7RGND_VOID=TRUE

402

0.01UF

402

0.01UF

402

0.01UF

0.1UF10V CERM 402 20%

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

MF1/20W5%

SM BEAD-PROBE

SIGNAL_MODEL=EMPTY

MF1/20W5%

PCIE_SSD_R2D_N<1>

SATA_SSD_R2D_P PCIE_SSD_R2D_P<1>

ISNS_SSD_NISNS_SSD_P

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

PP3V3_S0_SSD_FLT

PLACE_NEAR=J4501.9:3mmCRITICAL

0603FERR-26-OHM-6A

MIN_NECK_WIDTH=0.25mm

PP3V3_S0_SSD_R

MF-LF

C45021

2

C45011

2

C45191

2

U4510

43

87

1819

1617

1415

12139

2

J4501

272829303132333435

1

101112131415161718

192

20212223242526

3456789

R45261 2

BP45021

R4520

L4500

BP45031

R4505

1

2

051-9589 4.18.0

Trang 40

STDA_SSTX-GND_DRAIN

STDA_SSRX-SHLD

GND

VBUSD-D+

SYM_VER-1

BIBI

INOUT

IN

OUT

IO NC IO

GNDVBUS NC

VCC

GNDSELOE*

D+

D-Y+

M+

Y-

M-FAULT*

IN_1IN_0

ILIM

OUT1OUT2

ENGNDTHRMPAD

REVISION

BRANCH

USB Port Power Switch

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

USB/SMC Debug Mux

SEL=1 Choose USBSEL=0 Choose SMC

Place L4605 and L4615 at connector pin

We can add protection to 5V if we want, but leaving NC for now

0201 X5R-CERM 10%

USB3.0-J5

F-RT-THCRITICAL

BEAD-PROBESM

SMBEAD-PROBE SIGNAL_MODEL=EMPTY

BEAD-PROBESM

SMBEAD-PROBE SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SMBEAD-PROBE

TSSLP-2-1

ESD0P2RF-02LS

25V15PF

121/20W1% MF201

GND_VOID=TRUE

25V15PF

NP0-CERM 02015%

GND_VOID=TRUE

121/20W1% MF201

201

SMC_DEBUG_NO

05%

1/20WMF

MF1/20W5%

402

22.1K1%

1/16W

201

22.1K1%

1/20WMF

20%

603

10UF

6.3V X5R 20%

CERM

0.1UF

10V 402

SMC_DEBUG_YES10K

1/16W 5%

=PP3V42_G3H_SMCUSBMUX

USB_EXTA_NUSB_EXTA_P

NO_TEST=TRUEUSB3_EXTA_RX_P

NO_TEST=TRUEUSB3_EXTA_RX_N

NO_TEST=TRUEUSB3_EXTA_TX_P

NO_TEST=TRUEUSB3_EXTA_TX_N

=PP5V_S3_LTUSB

USB_PWR_EN

GND_VOID=TRUE

USB_LT1_PUSB_LT1_N

X7R-CERM

MIN_LINE_WIDTH=0.5 mm

TCM0605-190-OHM-50MA

2

C46051 2

D46001

6

C46901 2

R46901

2

C46921 2

U4650

6 7

4 5

2 1

U4600

48

5

23

67

7

1415161718

10111213

5689

Tiêu đề	Apple Macbook Pro Retina 15, A1398
Thể loại	Tài liệu
Năm xuất bản	2012
Thành phố	City

Định dạng
Số trang	99
Dung lượng	2,77 MB