Giới thiệu về VHDL (P2)

VHDL tiép theo Phát biểu đông thời Phat biéu tuân tự... Phát biêu đông thời phat biéu tuân no... Phát biêu đồng thời Phat biéu gan cho tín hiệu The WHEN statement WHEN/ELSE or WITH/SELE

VHDL (tiép theo) Phát biểu đông thời

Phat biéu tuân tự

DataAddr <= BaseAddr & Q(/7 downto 0);

end sample; Ey S Lab

Concurrent vs Sequential

END KỊ- Lab

Phát biêu đông thời phat biéu tuân

no

Phát biêu đồng thời

Phat biéu gan cho tín hiệu

The WHEN statement (WHEN/ELSE or WITH/SELEC T/WHEN);

The GENERATE statement;

The BLOCK statement.

y <= (a AND NOT sl AND NOT sO) OR

(b AND NOT s1 AND s0) OR

(c AND sl AND NOT sO) OR

WHEN/ELSE , WITH/SELEC T/WHEN

WHEN / ELSE:

assignment WHEN condition ELSE

assignment WHEN condition ELSE

WITH identifier SELECT

assignment WHEN value,

assignment WHEN value,

La

ẦẲ “sự

- Solution 1: with WHEN/ELSE -

y <= a WHEN sel="00" ELSE

b WHEN sel="01" ELSE

d;

END muxl;

- Solution 2: with WITH/SELECT/WHEN -

USE ieee.std logic 1164.all;

ENTITY tri state IS

PORT ( ena: IN STD LOGIC;

input: IN STD LOGIC VECTOR (7 DOWNTO 0); output: OUT STD LOGIC VECTOR (7 DOWNTO 9));

1 Solution 1: with WHEN/ELSE -

2 LIBRARY ieee;

3 USE ieee.std logic 1164.all;

, Ỏ

5 ENTITY encoder IS

É PORT ( x: IN STD LOGIC VECTOR (7 DOWNTO 0);

7 y: OUT STD LOGIC VECTOR (2 DOWNTO 0));

1 Solution 2: with WITH/SELECT/WHEN -

2 LIBRARY ieee;

3 USE ieee.std logic 1164.all;

4 ene eee eee eee ee eee eee ee eee eee eee eee eee

5 ENTITY encoder I5

€ PORT ( x: IN STD LOGIC VECTOR (7 DOWNTO 0);

7 y: OUT STD LOGIC VECTOR (2 DOWNTO 0));

ARCHITECTURE example BEGIN

PROCESS

[VARIABLE name type [range] [:= initial value; ]]

BEGIN

(sequential code)

END PROCESS [label];

Tín hiệu và biên

SlGNAL được khai báo trong PDACKAOE,

ENTITY hoac ARCHITECTURE; trong khi đó

VARIABLE chỉ được khai báo trong khôi tuân tự

SIGNAL là đôi tượng dữ liệu mang tính toàn

Phat biéu IF

IF conditions THEN assignments;

ELSIF conditicns THEN assignments;

IF (x<y) THEN temp:="11111111";

ELSIF (x=y AND w='0') THEN temp:="11110200";

ELSE temp:=(OTHERS =>'0');

Example 6.2: One-digit Counter

2 LIBRARY ieee;

3 USE ieee.std_logic 1164.all;

4 eee eee eee eee ee eee eee ee eee eee eee eee eee

Example: 8-bit register with synchronous reset

PROCESS —— no sensitivity list

Example: 8-bit register with asynchronous reset

Example 6.5: One-digit Counter

2 LIBRARY ieee;

3 USE ieee.std_ logic 1164.all1;

4 anne eee ee eee ee ee ee eee eee eee eee eee eee

12 PROCESS no sensitivity list

13 VARIABLE temp : INTEGER RANGE 0 TO 10;

Phát biêu CASE

CASE identifier IS

WHEN value => assignments;

WHEN value => assignments;

END CASE;

EXIT: Used for ending the loop

Example of FOR / LOOP:

FOR i IN data'RANGE LOOP

One level below top:

1 - Solution 1: Generic, with VECTORS -

2 LIBRARY ieee;

3 USE leee.std logic 1164.all;

5 ENTITY adder IS

6 GENERIC (length : INTEGER := 8);

7 PORT ( a, b: IN STD LOGIC VECTOR (length-1 DOWNTO 0);

8 cin: IN STD LOGIC;

9 s: OUT STD LOGIC VECTOR (length-1 DOWNTO 0);

10 cout: OUT STD LOGIC);

11 END adder;

13 ARCHITECTURE adder OF adder IS

14 BEGIN

15 PROCESS (a, b, cin)

16 VARIABLE carry : STD LOGIC VECTOR (length DOWNTO 0);

18 carry(0) := cin;

19 FOR i IN 0 TO length-1 LOOP

20 s(i) <= a(i) XOR b(i) XOR carry(i);

21 carry(it+l) := (a(i) AND D(i)) OR (a(i) AND

22 carry(i)) OR (b(i) AND carry(i));