Giới thiệu về VHDL (P1)

Kiêu dữ liệu Kiêu vô hướng scalar types — Kiểu liệt kê enumerated type — Kiêu số nguyên interger type — Kiểu số thực dâu châm động floating point type — Kiéu vat ly physical type Ki

VHDL

Giới thiệu, Câu trúc Mã

Kiểu dữ liệu, Toán tử

Câu trúc tuân tự, câu trúc song song

Tín hiệu, bien; Packages va Components

Giới thiệu

‹ Giới thiệu về VHDL

* Quy trinh thiét ké voi VHDL

¢ Bién dich ma VHDL thanh mach logic

VHDL được tiêu chuẩn hóa từ 1987 bởi IEEE 1076-

1987, nâng câp năm 1993

Tai sao sw dung VHDL?

— Su dung so’ đồ mạch đề mô tả thiết kê phức tạp thì mất quá nhiều thời gian và công sức

Sự kác nhau giữa VHIDL và các ngôn ngữ lập trình là gì?

— VHDL được thiết kế để mô hình hóa các hoạt động song song.

Quy trình thiệt kê với VHDL

Bien dich ma VHDL thanh mach logic

¡L0 1 QO 1

il Ì lL |

Eieure 1.2 Full-adder diagram and truth table.

ENTITY fu_l adder IS

PORT (a, b, cin: IN BIT;

Ss, cout: OUT BIT);

END full adder;

ARCHITECTURE dataflow OF full adder I3 BEGIN

s <= a XOR b XOR cin:

cout <= (a AND b) OR (a AND cin) OR

Câu trúc của chương trình mô tả

bang VHDL

¢ Cac thanh phan co’ ban

¢ Vi du

Các thành phân cơ bản

¢ LIBRARY : khai bao danh sach cac thu

viện được sử dụng

For example: ieee, std, work.,

¢ ENTITY: Xac định các chan I/O cua mach

+ ARCHITECTURE: Chira cac phat biéu

dung nguyén tac mô tả ứng xử của mạch

(chức năng).

LIBRARY

¢ Khali bao:

LIBRARY library name;

USE library name.package name.package parts;

TYPES

Figure 2.2

Fundamental parts of 2 LIBRARY.

e Vi du khai báo thư viện:

¢ Mot so thu vién chuan:

— std_logic_ 1164: định nghĩa kiểu STD LOGIC (8 levels) va

STD_ULOGIC (9 levels)

— std_logic_arith: định nghĩa kiểu SIGNED và UNSIGNEDvà các tóan tử

số học và so sánh; các hàm chuyền kiểu: onv_integer(p),

conv_unsigned(p, b), conv_signed(p,b), onv_std_ logic_vector(p,b)

— std_logic_signed: chứa các hàm toán tử với kiểu

STD_LOGIC_VECTOR có dấu

— std_logic_unsigned: chứa các hàm toán tử với kiểu

STD_LOGIC_VECTOR không dấu.

port name : signal mode signal type;

port name : signal mode signal type;

ENTITY nand gate IS : CƠN

| — X PORT (a, b : IN BIT; bh ——

x : OUT BIT);

END nand_gate;

Figure 2.4 NAND gate.

e Vi du: ENTITY nand_gate IS

PORT (a, b : IN BIT;

x : OUT BIT);

q |

b —

ARCHITECTURE myarch OF nand_ gate IS Figure 2.4

x <= a NAND b;

END myarch;

Figure 2.5 DFF with asynchronous reset.

d »— p— q

DFF

clk +>

rst -——

Figure 2.5 DFF with asynchronous reset

ARCHITECTURE example OF example IS

SIGNAL temp : BIT;

b—— DFE

clk >

Eignre 2.7 DFF plus NAND gate

10 b

II Z

PORT ( _ „, ? _ STD _LOGIC_VECTOR (7 DOWNTO 0);

Kiêu dữ liệu

Kiêu vô hướng (scalar types)

— Kiểu liệt kê (enumerated type)

— Kiêu số nguyên (interger type)

— Kiểu số thực dâu châm động (floating point type)

— Kiéu vat ly (physical type)

Kiéu két hop (composite types)

— Mang (array type)

— Record type

Access type

File type

Các kiểu dữ liệu được định nghĩa trước

Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types

Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types

Package std _logic_arith of library ieee: Defines SIGNED and UNSIGNED data types, plus several data

conversion functions, like conv_integer(p),

conv_unsigned(p, b), conv_signed(p, b), and

conv_std logic _vector(p, b

Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow operations with STD LOGIC VECTOR data to be performed as if the

data were of type SIGNED or UNSIGNED, respectively.

BIT, BIT VECTOR

¢ BIT (and BIT VECTOR): 2-level logic (0’,'1°)

¢ Examples:

SIGNAL x: BIT:

X is declared as a one-digit signal of type BIT

SIGNAL y: BIT VECTOR (3 DOWNTO 0O);

y is a 4-bit vector, with the leftmost bit being the MSB

SIGNAL w: BIT VECTOR (0 TO 7);

w is an 8-bit vector, with the rightmost bit being the MSB

X is a Single-bit signal (as specified above), whose value is '1' Notice that single quotes (' `) are used for a single bit

y <= "0111";

y is a 4-bit signal (as specified above), whose value is "0111"

(MSB='0') Notice that double quotes ("") are used for

vectors

w <= "01110001";

W is an 8-bit signal, whose value is "01110001" (MSB='1')

STD LOGIC STD LOGIC VECTOR

- STD LOGIC (and STD LOGIC_ VECTOR): 8-

valued logic system introduced in the IEEE 1164 standard

‘X Forcing Unknown (synthesizable unknown)

‘0’ Forcing Low (synthesizable logic ‘1°)

‘1’ Forcing High (synthesizable logic ‘0’)

‘Z High impedance (synthesizable tri-state buffer)

‘VW’ Weak unknown

‘L’ Weak low

‘H’ Weak high

— Dont care

¢ Examples:

SIGNAL x: STD_ LOGIC;

Xx is declared as a one-digit (scalar) signal of type STD LOGIC

SIGNAL y: STD _LOGIC_ VECTOR (3 DOWNTO 0) := "0001": y is declared as a 4-bit vector, with the leftmost bit being

the MSB The initial value (optional) of y is "0001" Notice

that the ":=" operator is used to establish the initial value

Môi số kiểu khác

BOOLEAN: True, False

INTEGER: 32-bit integers (from -2,147,483,647 to

x4 <= B"101111" ; binary representation of decimal 47

x5 <= O"5/" ; octal representation of decimal 47

x6 <= X"2F" ; hexadecimal representation of decimal 47

n <= 1200; integer

m <= 1 200; integer, underscore allowed

IF ready THEN Boolean, executed if ready=TRUE

y <= 1.2E-5; real, not synthesizable

q <= d after 10 ns; physical, not synthesizable

SIGNAL a: BIT;

SIGNAL b: BIT VECTOR(7 DOWNTO 0);

SIGNAL c: STD_LOGIC;

SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0):

SIGNAL e: INTEGER RANGE 0 TO 255:

a <= b(5); legal (same scalar type: BIT)

b(Q) <= a; legal (same scalar type: BIT)

c <= d(5); legal (Same scalar type: STD LOGIC)

d(0) <= c; legal (Same scalar type: STD LOGIC)

a <=c; illegal (type mismatch: BIT x STD LOGIC)

b <= d; illegal (tyoe mismatch: BIT VECTOR x STD LOGIC VECTOR)

e <= b; illegal (type mismatch: INTEGER x BIT_ VECTOR)

e <= d; illegal (type mismatch: INTEGER x STD_LOGIC_ VECTOR)

Kiều được định nghĩa bởi người

dùng

¢ integer

¢ enumerate (liét kê)

° Kiểu integer được định nghĩa bởi người

dùng:

TYPE integer IS RANGE -2147483647 1O +214748364/;

This is indeed the pre-defined type INTEGER

TYPE natural IS RANGE 0 TO +2147483647;

This is indeed the pre-defined type NATURAL

TYPE my_integer IS RANGE -32 TO 32;

A user-defined subset of integers

TYPE student_grade IS RANGE 0 TO 100;

A user-defined subset of integers or naturals

- Kiéu enumerated được định nghĩa bởi người dùng::

TYPE bít IS (0', '1');

This is indeed the pre-defined type BIT

TYPE my logic lS (0, 1, 2);

A user-defined subset of std_logic

TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT;

This is indeed the pre-defined type BIT VECTOR

RANGE <> is used to indicate that the range is unconstrained NATURAL RANGE <>, on the other hand, indicates that the only restriction is that the range must fall within the NATURAL

range

TYPE state IS (idle, forward, backward, stop);

An enumerated data type, typical of finite state machines

TYPE color IS (red, green, blue, white);

Another enumerated data type

SUBTYPE

SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH;

As expected, NATURAL is a subtype (subset) of INTEGER

SUBTYPE my_logic IS STD LOGIC RANGE '0' TO 'Z':

Recall that STD LOGIC=(X,0,1,Z,W,L,H,-}

Therefore, my_logic=('0','1','2Z’)

SUBTYPE my_color IS color RANGE red TO blue;

Since color=(red, green, blue, white), then

my_color=(red, green, blue)

SUBTYPE small_ integer IS INTEGER RANGE -32 TO 32:

A subtype of INTEGER

SUBTYPE my_logic IS STD LOGIC RANGE '0' TO '1'; SIGNAL a: BIT;

SIGNAL b: STD LOGIC;

SIGNAL c: my_logic;

b <= a; illegal (type mismatch: BIT versus STD LOGIC)

b <= c; legal (same "base" type: STD LOGIC)

Mang (Array)

¢ They can be one-dimensional (1D), two- dimensional (2D), or one-dimensional-by- one-dimensional (1Dx1D)

¢ They can also be of higher dimensions, but then they are generally not

synthesizable.

01000

To specify a new array type:

1Dx1D:

TYPE row IS ARRAY (7 DOWNTO 0) OF STD LOGIC; 1D array

TYPE matrix IS ARRAY (0 TO 3) OF row; 1Dx1D array

SIGNAL x: matrix; 1Dx1D signal

TYPE matrix IS ARRAY (0 TO 3) OF STD LOGIC VECTOR(7 DOWNTO 0);

2D:

TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD LOGIC;

2D array

Gan tri ban dau:

e+e 2="0001"; for 1D array

ee 2=('O0', 'O','O','1') for 1D array

r=(('O','1','1','1"'), ('1','1','1','0')); —- for 1Dx1D or

2D array

2D array SIGNAL x: row;

CTONAT tr* arratriles

WY LUILVGCAL J CÁ L L CẢ ay

SIGNAL v: array2;

SIGNAL w: array3;

TYPE row IS ARRAY (7 DOWNTO 0) OF STD LOGIC;

1D array

TYPE arrayl IS ARRAY (0 TO 3) OF row;

1Dx1D array TYPE array2 IS ARRAY (0 TO 3) OF STD LOGIC VECTOR(7 DOWNTO 0);

- Legal scalar assignments: -

=—= The scalar (sincle bit) assignments below are all legal,

because the "base" (scalar) type is STD LOGIC for all signals

_— (X,Y,V,W)

x(0) <= y(1)(2); notice two pairs of parenthesis

(y 1S 1DxID) x(1) <= v(2)(3); two pairs of parenthesis (v 1s 1DxID) x(2) <= w(2,1); a single pair of parenthesis (w is 2D)

x <= y(0); legal (same data types: ROW)

x <= v(1); illegal (type mismatch: ROW x

STD LOGIC VECTOR)

x <= w(2); illegal (w must have 2D index)

x <= w(2, 2 DOWNTO 0); illegal (type mismatch: ROW x

STD LOGIC)

v(0) <= w(2, 2 DOWNTO 0); illegal (mismatch: STD LOGIC VECTOR

x STD LOGIC)

v(0) <= w(2); illegal (w must have 2D index)

V(1) <= v(3);3 illegal (type mismatch: ROW x

STD LOGIC VECTOR) y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0); — legal (same type,

same size) v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0); legal (Same type,

-—- same size) w(1, 5 DOWNTO 1) <= v(2)(4 DOWNTO 0); illegal (type mismatch)

Kiéu Record

Example:

TYPE birthday IS RECORD

day: INTEGER RANGE 1 TO 31;

month: month name;

END RECORD;

Cac ham chuyén kiéu

Example: Legal and illegal operations with subsets

TYPE long IS INTEGER RANGE -100 TO 100;

TYPE short IS INTEGER RANGE -10 TO 10;

SIGNAL x : short;

SIGNAL y : long;

y <= 2*x + 5; error, type mismatch

y <= long(2*x + 5); -=- OK, result converted into type long

Một sô hàm chuyền kiêu

conv_integer(p) : Converts a parameter p of type INTEGER,

UNSIGNED, SIGNED, or STD _ULOGIC to an INTEGER value Notice that STD_ LOGIC _VECTOR is not included

conv_unsigned(p, b): Converts a parameter p of type INTEGER,

UNSIGNED, SIGNED, or STD _ULOGIC to an UNSIGNED value

with size b bits

conv_signed(p, b): Converts a parameter p of type INTEGER,

UNSIGNED, SIGNED, or STD _ULOGIC to a SIGNED value with

size b bits

conv_std_logic_vector(p, b): Converts a parameter p of type

INTEGER, UNSIGNED, SIGNED, or STD LOGIC toa

STD _ LOGIC VECTOR value with size b bits

Example: Data conversion

LIBRARY ieee;

USE ieee.std logic 1164.all;

USE ieee.std logic arith.all;

SIGNAL a: IN UNSIGNED (7 DOWNTO 0);

SIGNAL b: IN UNSIGNED (7 DOWNTO 0);

SIGNAL y: OUT STD LOGIC VECTOR (7 DOWNTO 0);

y <= CONV STD LOGIC VECTOR ((atb), 8);

Legal operation: atb is converted from UNSIGNED to an 8-bit STD LOGIC VECTOR value, then assigned to y.

Tổng kêt phân kiêu dữ liệu

Tablc 3.2

Synthesizable data types

Data types

BIT, BIT VECTOR

STD_LOGIC, STD_LOGIC VECTOR

STD ULOGIC, STD ULOGIC VECTOR

Lser-defined integer type

Lser-defined enumerated type

From —2,147.483,647 to +2,147,483,647 From —2,147.483,647 to +2,147,483,647

From 0 to +2,147,483,647

Subset of INTEGER

Collection enumerated by user Subset of any type (pre- or user-defined) Single-ty pe collection of any type above

Multiple-type collection of any types above

TYPE byte IS ARRAY

TYPE meml IS ARRAY

TYPE mem2 IS ARRAY

TYPE mem3 IS ARRAY

: STD LOGIC VECTOR (7 DOWNTO 0);

: BIT VECTOR (3 DOWNTO 0)

TO 3) OF STD LOGIC VECTOR(0 TO 7);

1D array 2D array 1Dx1D array 1Dx1D array scalar signal scalar signal 1D

1D 1D

1D sĩ 2D signal

1Dx1D signal

1Dx1D signal

same

types types

(STD LOGIC), correct (STD LOGIC), correct

(STN TOGCTC\ rar rant

nryt

(BIT), correct indexing (STD LOGIC), correct indexing

(STD LOGIC), (STD LOGIC), (STD LOGIC), (STD LOGIC),

correct correct

- Legal vector assignments: -

- Illegal array assignments: -

w2(0, 7 DOWNTO 0) <= "11110000"; index should be 1Dx1D

Example of data type independent array initialization:

END LOOP;

END LOOP;

Bit va Bit Vector

x: OUT BIT VECTOR (0 TO 3)); END and2;

x <= a AND b;

END and2;

Bai tap

TYPE arrayl IS ARRAY (7 DOWNTO 0) OF STD LOGIC;

TYPE array2 IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD LOGIC; TYPE array3 IS ARRAY (3 DOWNTO OQ) OF arrayl;

Dimension Legal or illegal

Figure 3.3 7 PORT ( a, b : IN SIGNED (3 DOWNTO 0);

4-bit adder of example 3.3 8 sum : OUT SIGNED (4 DOWNTO 0))};

a (3:0) >

3 USE leee.std logic 1164.all;

4 USE leee.std logic arith.all;

5 ee eee ee eee eee eee eee ee eee eee ee

6 ENTITY adder2 IS

7 PORT ( a, b : IN SIGNED (3 DOWNTO 0);

8 sum : OUT INTEGER RANGE -16 TO 15);