Lecture Digital logic design - Lecture 21: Sequential circuits: Flip flops

The following will be discussed in this chapter: Flip flops are powerful storage elements, D flip flop is simplest and most widely used, asynchronous inputs allow for clearing and presetting the flip flop output, multiple flops allow for data storage, combine storage and logic to make a computation circuit.

Lecture 21

Sequential Circuits: Flip flops

Combinational vs Sequential

A combinational circuit:

• At any time, outputs depends only on inputs

• Changing inputs changes outputs

• No regard for previous inputs

• No memory (history)

Examples of sequential systems

What is common between these systems?

• 4-bit adder (ripple-carry)

Combinational Adder

 1-bit memory and 2 4-bit memory

 Only one full-adder!

Sequential Adder

Problem with Latches

• What happens if Clock=1? What

will be the value of Q when Clock

goes to 0?

• Problem: A latch is transparent;

state keep changing as long as

the clock remains active

Example

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° Latches respond to trigger levels on control inputs

• Example: If G = 1, input reflected at output

° Difficult to precisely time when to store data with

latches

° Flip flips store data on a rising or falling trigger edge.

• Example: control input transitions from 0 -> 1, data input appears at

output

• Data remains stable in the flip flop until until next rising edge.

° Different types of flip flops serve different functions

° Flip flops can be defined with characteristic functions.

° The most fundamental sequential components are

the latch and flip-flop

° They store one bit of data and make it available to

other components

° The main difference between a latch and a flip-flop

is that the first are level triggered and the latter are edge triggered

° Flip-flops and latches have a clock input

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•Latch is a type of temporary storage device that has two

stable states (bistable).

•Latch is normally placed in a category separate from that

flip – flops.

•The main difference between latch and FF is in the method

used for changing their state.

•The output of a latch depends on its current inputs and on

its previous output and its change of state can happen at

any time when its inputs change.

° It is usually derived from an oscillator or other

circuitry that alternates its output between 1 and 0

° It is used to synchronize the flow of data in a

digital system

0 1

Rising (positive)

Edge Falling (negative)

D Latch

Q  Q’

EN: Enable

Transparent D-Latch: Example Timing

74LS75: D Latch

D-Latch using MUX

D passes to Q when C=0

D passes to Q when C=1

° The latch circuits are not appropriate for use in

synchronous sequential logic circuits

° The possibility of two cascaded combinational

circuits feeding each other, generating oscillations and unstable transient behavior can be controlled

by using a special timing control signal called a

clock

° The clock can then be used to restrict the times at

which the states of the memory elements may

change thus preventing the unstable behavior just described.

Latches Relationship with Flip Flops

° Latches and Flip Flops are related as latches are

basic circuits from which all the flip flops are

constructed

° Though they (latches) are useful for storing binary

information and for the design of asynchronous

sequential circuits but they are not practical for

synchronous sequential circuits.

Master-Slave D Latches

° Consider two latches combined together

° Only one C value active at a time

° Output changes on falling edge of the clock

° Stores a value on the positive edge of C

° Input changes at other times have no effect on output

D Flip-Flop: Example Timing

POS & NEG Edge Triggered D Flip Flop

Positive Edge Trigger

Negative Edge Trigger

Clocked D Flip-Flop

° Stores a value on the positive edge of C

° Input changes at other times have no effect on output

Positive and Negative Edge D

Flip-Flop

° D flops can be triggered on positive or negative edge

° Bubble before Clock (C) input indicates negative edge trigger

Flip-Flop Vs Latch

° The primary difference between a D flip-flop and D

latch is the EN/CLOCK input

° The flip-flop’s CLOCK input is edge sensitive,

meaning the flip-flop’s output changes on the edge (rising or falling) of the CLOCK input

° The latch’s EN input is level sensitive, meaning the

latch’s output changes on the level (high or low) of the EN input.

74LS74: D Flip-Flop

JK flip-flop

° Resolves the problem of undefined outputs associated with

SR latch

° J=1 sets the output to 1 and K=1 resets the output to 0

JK=11 inverts the stored current value of the output

° It is often used instead of SR latch

o Include a toggle state.

• J=HIGH (and K=LOW) a SET state

• K=HIGH (and J=LOW) a RESET state

• both inputs LOW a no change

• both inputs HIGH a toggle

J/K Flip-Flop: Example Timing

NO CHANGE SET

JK Flip-flop Implement by D Flip-flop

Clocked J-K Flip

Flop

° Two data inputs, J and K

° J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

Positive Edge-Triggered J-K Flip-Flop

Determine the Q output, assuming that the flip-flop is initially RESET

Positive Edge-Triggered T Flip-Flop

T Flip-flop Implementation by JK Flip-flop

Q T

Implement JK Flip-flop by T Flip-flop

° Asynchronous design is often unavoidable:

• User interfaces

• Different speed devices

• Clocks are difficult to distribute over long

distances

° More difficult to design, design tools generally have

been synchronous only, but asynchronous design

tools are being developed.

° Most current devices us synchronous logic inside

local blocks, and asynchronous communication

between blocks.

Types of Sequential Circuits

• Two types of sequential circuits:

• Synchronous: The behavior of the circuit

depends on the input signal at discrete

instances of time (also called clocked)

• Asynchronous: The behavior of the circuit

depends on the input signals at any instance of time and the order of the inputs change

• A combinational circuit with feedback

Asynchronous inputs (Preset & Clear) are

used to override the clock/data inputs and

force the outputs to a predefined state.

The Preset (PR) input forces the output to:

The Clear (CLR) inpt forces the output to:

0 Q

&

1 Q

1 Q

&

0 Q

D Flip-Flop: PR & CLR Timing

Asynchronous Inputs

Asynchronous Inputs

•  Note reset signal (R) for 

D flip flop

• If R = 0, the output Q is  cleared

•This event can occur at  any time, regardless of the  value of the CLK

Parallel Data Transfer

° Flip flops store outputs from combinational logic

° Multiple flops can store a collection of data

Characteristic Tables

• A characteristic table defines

the operation of a flip flop in a

tabular form

• Next state is defined in terms

of the current state and the

inputs

• Q(t) refers to current state

( before the clock arrives)

• Q(t+1) refers to next state

( after the clock arrives)

Characteristic Equations

• A characteristic equation

defines the operation of a flip

flop in an algebraic form

° Flip flops are powerful storage elements

• They can be constructed from gates and latches!

° D flip flop is simplest and most widely used

° Asynchronous inputs allow for clearing and presetting

the flip flop output

° Multiple flops allow for data storage

• The basis of computer memory!

° Combine storage and logic to make a computation

circuit